Abstract: According to embodiments of the present invention, there are provided a TFT array substrate, a method for manufacturing the TFT array substrate and an electronic device.

Abstract: Embodiments of the present invention provide a thin film transistor array substrate, a method for manufacturing the same, a display panel and a display device. The method for manufacturing the thin film transistor array substrate comprises: sequentially depositing a first metal oxide layer, a second metal oxide layer and a source and drain metal layer, conductivity of the first metal oxide layer being smaller than conductivity of the second metal oxide layer; patterning the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, so as to form an active layer, a buffer layer, a source electrode and a drain electrode, respectively. According to technical solutions of the embodiments of the invention, it is possible that the manufacturing process of the metal oxide TFT array substrate is simplified, and the production cost of products is reduced.

Abstract: The present invention provides a pixel structure including a substrate, a thin-film transistor disposed on the substrate, a first insulating layer covering the thin-film transistor and the substrate, a common electrode, a connecting electrode, a second insulating layer, and a pixel electrode. The thin-film transistor includes a drain electrode. The first insulating layer has a first opening exposing the drain electrode. The common electrode and the connecting electrode are disposed on the first insulating layer. The connecting electrode extends into the first opening to be electrically connected to the drain electrode. The connecting electrode is electrically insulated from the common electrode. The second insulating layer covers the first insulating layer, the common electrode, the connecting electrode, and has a second opening exposing the connecting electrode. The pixel electrode is disposed on the second insulating layer and electrically connected to the connecting electrode through the second opening.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Abstract: A semiconductor device including a first gate electrode and a second gate electrode formed apart from each other over an insulating surface, an oxide semiconductor film including a region overlapping with the first gate electrode with a gate insulating film interposed therebetween, a region overlapping with the second gate electrode with the gate insulating film interposed therebetween, and a region overlapping with neither the first gate electrode nor the second gate electrode, and an insulating film covering the gate insulating film, the first gate electrode, the second gate electrode, and the oxide semiconductor film, and being in direct contact with the oxide semiconductor film is provided.

Abstract: An object of the present invention is to provide a display device which can be manufactured with usability of a material improved and with a manufacturing step simplified and to provide a manufacturing technique thereof. One feature of a display device of the present invention is to comprise an insulating layer having an opening, a first conductive layer formed in the opening, and a second conductive layer formed over the insulating layer and the first conductive layer, wherein the first conductive layer is wider and thicker than the second conductive layer, and the second conductive layer is formed by spraying a droplet including a conductive material.

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Abstract: A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

Abstract: In a semiconductor device in which an IGBT, a control circuit for the IGBT and so on are formed on an SOI substrate divided by trenches, the invention is directed to providing the IGBT with a higher breakdown voltage, an enhanced turn-off characteristic and so on. An N type epitaxial layer is formed on a dummy semiconductor substrate, a trench is formed in the N type epitaxial layer, an N type buffer layer and then a P type embedded collector layer are formed on the sidewall of the trench and the front surface of the N type epitaxial layer, and the bottom of the trench and the P+ type embedded collector layer are covered by an embedded insulation film. The embedded insulation film is covered by a polysilicon film, and a P type semiconductor substrate is attached to the polysilicon film with an insulation film being interposed therebetween.

Abstract: A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.

Abstract: A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Abstract: A method for manufacturing a substrate for a flat panel display device is disclosed. The present method uses photolithography with four masks to manufacture a TFT-LCD. After the third half-tone mask is used, the manufacturing of the TFTs and the defining of the pixel area of the substrate can be completed. The present method can avoid the alignment deviation and the generation of parasitic capacitance happened on the substrate made through the conventional photolithography with five masks. Therefore, the present method can reduce the costs and increase the yield. Moreover, the substrate for the TFT-LCD made by the present method can define a channel region in the semiconductor layer after the second half-tone mask. Hence, the subsequent manufacturing for forming a transparent conductive layer, a source, and a drain can be achieved by wet etching to effectively reduce the non-homogeneous etching for the channel region in the semiconductor layer.

Abstract: The invention relates to an electronic device including a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT including a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.

Abstract: A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

Abstract: An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the gate electrode; first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance; first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively. The active layer is exposed through the first and second barrier patterns; source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively.

Abstract: An array substrate includes scan lines and data lines defining pixel structures. Each pixel structure includes a first TFT, a second TFT and a pixel electrode. The first TFT includes a first gate connected to the scan line, a first source disposed above and partially overlapping the first gate, and a first drain disposed above the first gate. An end of the first source is connected to the data line. The first drain has at least one first concavity in which the first source is disposed partially. The second TFT includes a second gate connected to the scan line, a second source disposed above the second gate and connected to the first drain, and a second drain disposed above and partially overlapping the second gate. The second source has at least one second concavity in which the second drain is disposed partially. The pixel electrode connects to the second drain.

Abstract: Provided is a thin film transistor, wherein the on-off ratio thereof is increased by decreasing the OFF current thereof. A bottom-gate TFT (10) is provided with a channel layer (40) obtained by forming a second silicon layer (35) on a first silicon layer (30). Since amorphous silicon regions (32), which surround multiple grains (31) contained in the first silicon layer (30), contain hydrogen in an amount sufficient to enable termination of dangling bonds, most of dangling bonds in the amorphous silicon region (32) are terminated by hydrogen. For this reason, it becomes less likely to have defect levels formed in the amorphous silicon regions (32), and an OFF current that flows through defect levels is therefore decreased. A high number of the grains (31) are retained in the first silicon layer (30), and cause a large ON current to flow. Consequently, the on-off ratio of the TFT (10) is increased.

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Abstract: A semiconductor component includes a semiconductor body, a first emitter region of a first conductivity type in the semiconductor body, a second emitter region of a second conductivity type arranged distant to the first emitter region in a vertical direction of the semiconductor body, a base region of one of the first and second conductivity types arranged between the first and second emitter regions and having a lower doping concentration than the first second emitter regions, a first field stop zone of the same conductivity type as the base region arranged in the base region, and a second field stop zone of the same conductivity type as the base region arranged in the base region.

Abstract: Disclosed is a thin film transistor which has an oxide semiconductor as an activation layer, a method of manufacturing the same and a flat panel display device having the same. The thin film transistor includes an oxide semiconductor layer formed on a substrate and including a channel region, a source region and a drain region, a gate electrode insulated from the oxide semiconductor layer by a gate insulating film, and source electrode and drain electrode which are coupled to the source region and the drain region, respectively. The oxide semiconductor layer includes a first layer portion and a second layer portion. The first layer portion has a first thickness and a first carrier concentration, and the second layer portion has a second thickness and a second carrier concentration. The second carrier concentration is lower than the first carrier concentration.

Abstract: The semiconductor device includes a thin film transistor; a first interlayer insulating film over the thin film transistor; a first electrode electrically connected to one of a source region and a drain region, over the first interlayer insulating film; a second electrode electrically connected to the other of the source region and the drain region; a second interlayer insulating film formed over the first interlayer insulating film, the first electrode, and the second electrode; a first wiring electrically connected to one of the first electrode and the second electrode, on the second interlayer insulating film; and a second wiring not electrically connected to the other of the first electrode and the second electrode, on the second interlayer insulating film; in which the second wiring is not electrically connected to the other of the first electrode and the second electrode by a separation region formed in the second interlayer insulating film.

Abstract: An organic thin field transistor is disclosed. The organic thin field transistor includes a first and a second insulting layers, a metal structure and an organic layer serving as an active layer. Materials of the first and the second insulting layers are different, and by performing an etching process, a surface of the metal structure and a surface of the second insulting layer are effectively aligned. Because of the high flatness of the surface of the metal structure and the second insulting layer, a continuous film-forming property and crystallinity of the active layer of the organic thin field transistor are improved, so as to achieve a better the electrical characteristic.

Abstract: A thin film transistor including a lightly doped drain (LDD) region or offset region, wherein the thin film transistor is formed so that primary crystal grain boundaries of a polysilicon substrate are not positioned in the LDD or offset region.

Abstract: Provided may be a panel structure, a display device including the panel structure, and methods of manufacturing the panel structure and the display device. Via holes for connecting elements of the panel structure may be formed by performing one process. For example, via holes for connecting a transistor and a conductive layer spaced apart from the transistor may be formed by performing only one process.

Abstract: A semiconductor device comprises: a semiconductor substrate; a plurality of IGBT cells on the semiconductor substrate, each of the IGBT cells including a gate electrode and a first emitter electrode; a first gate wiring on the substrate and being connected to the gate electrode; an interlayer insulating film covering the first emitter electrode and the first gate wiring; and a second emitter electrode on the interlayer insulating film and being connected to the first emitter electrode through an opening of the interlayer insulating film, wherein the second emitter electrode extends above the first gate wiring via the interlayer insulating film.

Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: A method for semiconductor fabrication. The method includes providing a silicon substrate and forming a tunnel oxide layer over the silicon substrate. Thereafter, a nitride layer is formed over the tunnel oxide layer. The nitride layer and the tunnel oxide layer are etched except where at least one nonvolatile silicon oxide nitride oxide silicon (SONOS) transistor is formed. Additionally, oxide layers are simultaneously formed over the nitride layer corresponding to where at bast one SONOS memory transistor is formed and over the exposed silicon substrate corresponding to where at least one metal oxide semiconductor (MOS) transistor is formed.

Abstract: A trench IGBT is disclosed. One embodiment includes an embedded structure arranged above a collector region and selected from a group consisting of a porous semiconductor region, a cavity, and a semiconductor region including additional scattering centers for holes, the embedded structure being arranged below the body contact region such that the embedded structure and the body contact region overlap in a horizontal projection.

Abstract: In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.

Abstract: A structurally robust power switching assembly, that has a power transistor, comprising a thin and delicate layer of metal oxide, and a major surface of the layer of metal oxide being substantially coincident with a major surface of the power transistor, the major surface of the power transistor defining both an emitter and a gate. Also, dielectric material is placed over a portion of the emitter, so that it abuts the gate and a highly conductive pillar is constructed out of a relatively soft material, supported by the gate and the dielectric material, so that it has a larger area than would be possible if it was supported only by the gate.

Abstract: Provided is a display device capable of suppressing generation of optical leakage current as well as increase in capacitance in a case where a plurality of thin film transistors (TFTs) including a gate electrode film on a light source side are formed in series. Relative areas of opposing regions between a semiconductor film and the gate electrode film with respect to channel regions are different in at least a part of the plurality of TFTs, to thereby provide a flat panel display having a structure for suppressing increase in capacitance while suppressing generation of optical leakage current.

Abstract: A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is foamed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: In a thin film transistor (1), a gate insulating layer (4) is formed on a gate electrode (3) formed on an insulating substrate (2). Formed on the gate insulating layer (4) is a semiconductor layer (5). Formed on the semiconductor layer (5) are a source electrode (6) and a drain electrode (7). A protective layer (8) covers them, so that the semiconductor layer (5) is blocked from an atmosphere. The semiconductor layer (5) (active layer) is made of, e.g., a semiconductor containing polycrystalline ZnO to which, e.g., a group V element is added. This allows practical use of a semiconductor device which has an active layer made of zinc oxide and which includes an protective layer for blocking the active layer from an atmosphere.

Abstract: A semiconductor transistor device includes a drift region, an insulating structure, a gate insulator, a gate electrode, a source, and a drain. The drift region includes a first lateral portion having a first dopant concentration and a second lateral portion having a second dopant concentration that is higher than the first lateral portion. The insulating structure is formed on the drift region and is disposed over a border between the first and second lateral portions such that hole generation is minimized in the drift region during operation.

Abstract: In a lateral bipolar transistor including an emitter, a base and a collector which are formed in a semiconductor thin film formed on an insulating substrate, the semiconductor thin film is a semiconductor thin film which is crystallized in a predetermined direction. In addition, in a MOS-bipolar hybrid transistor formed in a semiconductor thin film formed on an insulating substrate, the semiconductor thin film is a semiconductor thin film which is crystallized in a predetermined direction.

Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.

Abstract: The semiconductor device includes a thin film transistor; a first interlayer insulating film over the thin film transistor; a first electrode electrically connected to one of a source region and a drain region, over the first interlayer insulating film; a second electrode electrically connected to the other of the source region and the drain region; a second interlayer insulating film formed over the first interlayer insulating film, the first electrode, and the second electrode; a first wiring electrically connected to one of the first electrode and the second electrode, on the second interlayer insulating film; and a second wiring not electrically connected to the other of the first electrode and the second electrode, on the second interlayer insulating film; in which the second wiring is not electrically connected to the other of the first electrode and the second electrode by a separation region formed in the second interlayer insulating film.

Abstract: A method of forming a display substrate includes forming an array layer on a substrate, forming a passivation layer on the array layer, forming a photoresist pattern on the passivation layer corresponding to a gate line, a source line and a thin-film transistor of the array layer, etching the passivation layer using the photoresist pattern as a mask, Non-uniformly surface treating a surface of the photoresist pattern, forming a transparent electrode layer on the substrate having the surface-treated photoresist pattern formed thereon and forming a pixel electrode. The forming a pixel electrode includes removing the photoresist pattern and the transparent electrode layer, such as by infiltrating a strip solution into the surface-treated photoresist pattern.

Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.

Abstract: A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.

Abstract: An array substrate includes a gate line, a data line, a switching device, a transmissive electrode, a reflective electrode and a compensating wiring. A pixel region includes first and second regions. The switching device is connected to the gate line and the data line. The transmissive electrode is connected to the switching device. The transmissive electrode is formed in the first region. The reflective electrode is insulated from the transmissive electrode. The reflective electrode is formed in the second region that is adjacent to the first region. The compensating wiring is connected to the switching device. The compensating wiring faces the reflective electrode in the second region with an insulation layer interposed therebetween. Thus, both of a reflectivity of the reflective electrode and a transmissivity of the transmissive electrode are enhanced simultaneously, while the liquid crystal display apparatus maintains a uniform cell gap.

Abstract: The object is to provide a lightened semiconductor device and a manufacturing method thereof by pasting a layer to be peeled to various base materials. In the present invention, a layer to be peeled is formed on a substrate, then a seal substrate provided with an etching stopper film is pasted with a binding material on the layer to be peeled, followed by removing only the seal substrate by etching or polishing. The remaining etching stopper film is functioned as a blocking film. In addition, a magnet sheet may be pasted as a pasting member.

Abstract: The present invention provides an electronic device having more than two conductive layers that cross but not in contact with each other. At least one of the conductive layers comprises a width change part, a width of which changes in a length direction of at least one of the conductive layer. The width change part is formed away from a region of at least one of the conductive layers that crosses a neighboring conductive layer. The present invention also provides a flat panel display device that includes the electronic device described above and manufactured in accordance with the principles of the present invention. The electronic device of the present invention may comprise a thin film transistor.

Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.

Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.

Abstract: The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

Abstract: A thin film power transistor includes a plurality of first doped regions over a substrate and a second doped region forming a body. At least a portion of the body is disposed between the plurality of first doped regions. The thin film power transistor also includes a gate over the substrate. The thin film power transistor further includes a dielectric layer, at least a portion of which is disposed between (i) the gate and (ii) the first and second doped regions. In addition, the thin film power transistor includes a plurality of contacts contacting the plurality of first doped regions, where the plurality of first doped regions forms a source and a drain of the thin film power transistor. The first doped regions could represent n-type regions (such as N? regions), and the second doped region could represent a p-type region (such as a P? region). The first doped regions could also represent p-type regions, and the second doped region could represent an n-type region.

Abstract: To achieve TFT having a high light-resistance characteristic with a suppressed light leak current at low cost by simplifying the manufacturing processes. The TFT basically includes a light-shielding film formed on a glass substrate that serves as an insulating substrate; an insulating film formed on the light-shielding film; a semiconductor film formed on the insulating film; and a gate insulating film formed on the semiconductor film. Each layer of a laminate that is configured with three layers of the light-shielding film, the insulating film, and the semiconductor film is patterned simultaneously. Further, each layer of the laminate is configured with silicon or a material containing silicon.