With At Least Part Of Active Region On Insulating Substrate (e.g., Lateral Dmos In Oxide Isolated Well) (epo) Patents (Class 257/E29.261)
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Publication number: 20120032262Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.Type: ApplicationFiled: August 5, 2010Publication date: February 9, 2012Applicants: LAAS-CNRS, ATMEL ROUSSET SASInventors: Willem-Jan Toren, Bruno Villard, Elsa Hugonnard-Bruyere, Gaetan Toulon, Frederic Morancho, Ignasi Cortes Mayol, Thierry Pedron
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Patent number: 8105939Abstract: A LDMOS transistor and a method for manufacturing the same are disclosed. A lateral double diffused metal oxide semiconductor (LDMOS) transistor includes a first dielectric layer formed on a top surface of a substrate; a plurality of second dielectric layers on a top surface of the first dielectric layer; a plurality of contact plugs spaced apart by a predetermined distance in an active region of the substrate, passing through the first and second dielectric layers; and a bridge metal line formed in the second dielectric layers, inter-connecting the contact plugs in a horizontal direction. The bridge metal line formed to inter-connect the contact plugs allows for more current to flow in the presently disclosed LDMOS transistor than in a conventional LDMOS transistor of identical size.Type: GrantFiled: November 9, 2009Date of Patent: January 31, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Cheol Ho Cho
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Publication number: 20120018804Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).Type: ApplicationFiled: July 23, 2010Publication date: January 26, 2012Inventors: Vishnu K. Khemka, Stephen J. Cosentino, Tahir A. Khan, Adolfo C. Reyes, Ronghua Zhu
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Publication number: 20120018776Abstract: A first annular isolation trench is formed in a periphery of an element region, and a second annular isolation trench is formed around the first annular isolation trench with a predetermined distance provided from the first annular isolation trench, and a semiconductor layer between the first annular isolation trench and the second annular isolation trench is separated into a plurality of portions by a plurality of linear isolation trenches formed in the semiconductor layer between the first annular isolation trench and the second annular isolation trench, and the semiconductor layer (source-side isolation region) which opposes a p-type channel layer end portion and is located between the first annular isolation trench and the second annular isolation trench is separated from other semiconductor layers (drain-side isolation regions) by the linear isolation trenches.Type: ApplicationFiled: July 21, 2011Publication date: January 26, 2012Inventors: Takuo Nagase, Junichi Sakano
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Patent number: 8097880Abstract: A semiconductor component including a lateral transistor component is disclosed. One embodiment provides an electrically insulating carrier layer. A first and a second semiconductor layer are arranged on above another and are separated from another by a dielectric layer. The first semiconductor layer includes a polycrystalline semiconductor material, an amorphous semiconductor material or an organic semiconductor material. In the first semiconductor layer: a source zone, a body zone, a drift zone and a drain zone are provided. In the second semiconductor layer; a drift control zone is arranged adjacent to the drift zone, including a control terminal at a first lateral end for applying a control potential, and is coupled to the drain zone via a rectifying element at a second lateral end. A gate electrode is arranged adjacent to the body zone and is dielectrically insulated from the body zone by a gate dielectric layer.Type: GrantFiled: April 9, 2009Date of Patent: January 17, 2012Assignee: Infineon Technologies Austria AGInventors: Joachim Weyers, Anton Mauder, Franz Hirler, Paul Kuepper
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Publication number: 20120001260Abstract: A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate.Type: ApplicationFiled: July 2, 2010Publication date: January 5, 2012Inventors: Hsueh I. Huang, Ming-Tung Lee, Shyi-Yuan Wu
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Publication number: 20110316078Abstract: A semiconductor device can include a transistor and an isolation region. The transistor is formed in a semiconductor substrate having a first conductivity type. The transistor includes a drift region extending from a drain region toward a source region and having a second conductivity type. The drift region includes a first resurf region near a working top surface and having the first conductivity type. The high voltage isolation island region includes a first well region laterally offset from the drift region. The first well region has the second conductivity type. An isolation region is located laterally between the drain region and the first well region. The isolation region comprises a portion of the semiconductor substrate extending to the top working surface.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: Fairchild Semiconductor CorporationInventors: Sunglyong Kim, Jongjib Kim
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Patent number: 8084817Abstract: A semiconductor device includes a high voltage first conduction type well in a semiconductor substrate, a second conduction type body in the high voltage first conduction type well, a source region in the second conduction type body, a trench in the high voltage first conduction type well, a first isolation oxide, an impurity doped polysilicon film, and a second isolation oxide stacked in the trench in succession, a drain region in the high voltage first conduction type well on one side of the trench, and a polygate on and/or over the high voltage first conduction type well.Type: GrantFiled: December 27, 2009Date of Patent: December 27, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Mi-Young Kim
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Publication number: 20110309443Abstract: The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern.Type: ApplicationFiled: June 17, 2010Publication date: December 22, 2011Inventors: Tsung-Yi Huang, Ying-Shiou Lin
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Publication number: 20110309442Abstract: An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.Type: ApplicationFiled: June 17, 2010Publication date: December 22, 2011Inventors: Bernhard H. Grote, Tahir A. Khan, Vishnu K. Khemka, Ronghua Zhu
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Publication number: 20110303977Abstract: An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a lightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.Type: ApplicationFiled: June 10, 2010Publication date: December 15, 2011Inventors: Yin-Fu Huang, Miao-Chun Chung, Shih-Chin Lien
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Publication number: 20110303978Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.Type: ApplicationFiled: June 14, 2010Publication date: December 15, 2011Applicant: Broadcom CorporationInventor: Akira Ito
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Patent number: 8072029Abstract: A high voltage semiconductor device includes a source region of a first conductivity type having an elongated projection with two sides and a rounded tip in a semiconductor substrate. A drain region of the first conductivity type is laterally spaced from the source region in the semiconductor substrate. A gate electrode extends along the projection of the source region on the semiconductor substrate between the source and drain regions. Top floating regions of a second conductivity type are disposed between the source and drain regions in the shape of arched stripes extending along the rounded tip of the projection of the source region. The top floating regions are laterally spaced from one another by regions of the first conductivity type to thereby form alternating P-N regions along the lateral dimension.Type: GrantFiled: January 11, 2008Date of Patent: December 6, 2011Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Yong-Cheol Choi, Chang-Ki Jeon, Sang-Hyun Lee
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Patent number: 8063446Abstract: Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate.Type: GrantFiled: July 21, 2009Date of Patent: November 22, 2011Assignee: Dongbu Electronics Co., Ltd.Inventor: Choul Joo Ko
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Patent number: 8063444Abstract: Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N+ doped drain region is disposed in the NDDD region. A P-body diffused region is formed in the second active region, wherein the NDDD region and the P-body diffused region are separated with a predetermined distance exposing the epi-layer. An N+ doped source region and a P+ diffused region are disposed in the P-body diffused region. A gate structure is disposed between the N+ doped source region and the N+ doped drain region. An additional heavily doped region is formed between the semiconductor and the epi-layer.Type: GrantFiled: April 17, 2009Date of Patent: November 22, 2011Assignee: Vanguard International Semiconductor CorporationInventor: Yih-Jau Chang
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Publication number: 20110278671Abstract: A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.Type: ApplicationFiled: July 20, 2010Publication date: November 17, 2011Inventors: Wei-Chieh Lin, Ho-Tai Chen, Jia-Fu Lin, Po-Hsien Li
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Patent number: 8053835Abstract: A semiconductor element includes an insulating outer layer that includes electric contact connections of a first conductive type. These connections are connected to contact areas located beneath the insulating surface layer, of which connections at least one is of a first conductive type. At least one of the contact areas and a further area that includes two layers of mutually different conductive types disposed between the contact areas, are covered by a layer of a second conductive type of material. This second layer is, in turn, covered with an insulating layer on at least that side which lies distal from the surface layer.Type: GrantFiled: May 3, 2000Date of Patent: November 8, 2011Inventor: Klas-Hakan Eklund
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Publication number: 20110266614Abstract: A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Inventors: Tahir A. Khan, Vishnu K. Khemka, Ronghua Zhu
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Publication number: 20110266620Abstract: An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.Type: ApplicationFiled: November 1, 2010Publication date: November 3, 2011Applicant: VISHAY-SILICONIXInventor: Kyle Terrill
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Publication number: 20110260245Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. In an embodiment, an apparatus includes a substrate having a first surface and a second surface, the second surface being opposite the first surface; a first device and a second device overlying the substrate; and an isolation structure that extends through the substrate from the first surface to the second surface and between the first device and the second device.Type: ApplicationFiled: April 23, 2010Publication date: October 27, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ruey-Hsin LIU, Puo-Yu CHIANG, Chih-Wen YAO, Yu-Chang JONG, Hsiao-Chin TUAN
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Publication number: 20110260247Abstract: A transistor including a source region, drain region, channel region, drift region, isolation region, a first gate structure over the channel region, and a second gate structure over the isolation region is provided. The drift region includes a first portion located under the isolation region and a second portion located laterally adjacent to the isolation region. The first gate structure is separated by a first separation space from the second gate structure. The first separation space is located over a portion of the second portion of the drift region and a portion of the isolation region.Type: ApplicationFiled: April 26, 2010Publication date: October 27, 2011Inventors: Hongning Yang, Jiang-Kai Zuo
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Publication number: 20110241113Abstract: A transistor includes an n-well implanted in a substrate, a source region including a p-body region in the n-well, and a n+ region and a p+ region in the p-body region, a drain region including a n+ region, and a dual gate between the source region and the drain region. The dual gate includes a first gate on a side closer to the source region and a second gate on a side closer to the drain region, the first gate separated from the second gate by a pre-determined distance sufficient that a capacitance between the gate and the drain is at least 15% lower than a capacitance of a transistor of the same unit cell size and configuration excepting that the first gate and second gate abut.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Inventor: Marco A. Zuniga
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Publication number: 20110241108Abstract: A transistor includes a source region including a first impurity region implanted into a substrate, a drain region including a second impurity region implanted into the substrate, and a gate including an oxide layer formed over the substrate and a conductive material formed over the oxide layer, the oxide layer comprising a first side and a second side, the first side formed over a portion of the first impurity region and the second side formed over a portion of the second impurity region, the first side having a thickness of less than about 100 ?, and the second side having a thickness equal to or greater than 125 ?.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Inventor: Marco A. Zuniga
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Publication number: 20110241114Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well.Type: ApplicationFiled: April 2, 2010Publication date: October 6, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: RU-YI SU, Fu-Chih Yang, Chun Lin Tsai, Ker-Hsiao Huo, Chia-Chin Shen, Eric Huang, Chih-Chang Cheng, Ruey-Hsin Liu, Hsiao-Chin Tuan
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Publication number: 20110241112Abstract: A transistor includes an n-well implanted in a substrate, a source region including a p-body region, a n+ region and a p+ region in the p-body region, a drain region comprising a n+ region, and a gate between the source region and the drain region. The p-body region includes a first implant region having a first depth, a first lateral spread and a first concentration of a p-type impurity, and a second implant region having a second depth, a second lateral spread and a second concentration of the p-type impurity. The second depth is less than the first depth, the second lateral spread is greater than the first lateral spread and the second concentration is greater than the first concentration. The p+ region and n+ region abut the second implant region.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Inventor: Marco A. Zuniga
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Publication number: 20110233673Abstract: A method for fabricating a lateral-diffusion metal-oxide semiconductor (LDMOS) device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first region and a second region both having a first conductive type in the semiconductor substrate, wherein the first region not contacting the second region; and performing a thermal process to diffuse the dopants within the first region and the second region into the semiconductor substrate to form a deep well, wherein the doping concentration of the deep well is less than the doping concentration of the first region and the second region.Type: ApplicationFiled: March 24, 2010Publication date: September 29, 2011Inventors: Tseng-Hsun Liu, Chiu-Ling Lee, Zheng-Hong Chen, Yi-Ming Wang, Ching-Ming Lee
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Patent number: 8022477Abstract: A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.Type: GrantFiled: February 21, 2008Date of Patent: September 20, 2011Assignee: DENSO CORPORATIONInventors: Nozomu Akagi, Shigeki Takahashi, Takashi Nakano, Yasushi Higuchi, Tetsuo Fujii, Yoshiyuki Hattori, Makoto Kuwahara
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Publication number: 20110220997Abstract: The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage.Type: ApplicationFiled: March 10, 2010Publication date: September 15, 2011Inventors: Tsung-Yi Huang, Huan-Ping Chu, Ching-Yao Yang, Hung-Der Su
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Publication number: 20110198692Abstract: A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain.Type: ApplicationFiled: February 17, 2010Publication date: August 18, 2011Inventors: Yih-Jau CHANG, Shang-Hui TU, Gene SHEU
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Publication number: 20110193161Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.Type: ApplicationFiled: February 8, 2010Publication date: August 11, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming Zhu, Lee-Wee Teo, Han-Guan Chew, Harry Hak-Lay Chuang
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Publication number: 20110186926Abstract: According to one embodiment, a semiconductor device comprises a high-k gate dielectric overlying a well region having a first conductivity type formed in a semiconductor body, and a semiconductor gate formed on the high-k gate dielectric. The semiconductor gate is lightly doped so as to have a second conductivity type opposite the first conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise an isolation region formed in the semiconductor body between the semiconductor gate and a drain of the second conductivity type, and a drain extension well of the second conductivity type surrounding the isolation region in the semiconductor body. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including one or more CMOS logic devices.Type: ApplicationFiled: January 29, 2010Publication date: August 4, 2011Applicant: BROADCOM CORPORATIONInventors: Akira Ito, Xiangdong Chen
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Patent number: 7989879Abstract: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).Type: GrantFiled: July 10, 2006Date of Patent: August 2, 2011Assignee: NXP B.V.Inventors: Freerk Van Rijs, Stephan J. C. H. Theeuwen, Petra C. A. Hammes
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Publication number: 20110169077Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a modified breakdown shallow trench isolation (STI) region to effectively reduce a drain to source resistance when compared to a conventional semiconductor device, thereby increasing the breakdown voltage of the semiconductor device when compared to the conventional semiconductor device. The modified breakdown STI region allows more current to pass from a source region to a drain region of the semiconductor device, thereby further increasing the break down voltage of the semiconductor device from that of the conventional semiconductor device. The semiconductor device may include a modified well region to further reduce the drain to source resistance of the semiconductor device.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Applicant: Broadcom CorporationInventor: Akira Ito
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Patent number: 7973333Abstract: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.Type: GrantFiled: April 2, 2007Date of Patent: July 5, 2011Assignee: Telefunken Semiconductors GmbH & Co. KGInventors: Franz Dietz, Volker Dudek, Thomas Hoffmann, Michael Graf, Stefan Schwantes
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Publication number: 20110156141Abstract: An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaume Roig-Guitart, Peter Moens
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Publication number: 20110140201Abstract: A lateral power MOSFET with a low specific on-resistance is described. Stacked P-top and N-grade regions in patterns of articulated circular arcs separate the source and drain of the transistor.Type: ApplicationFiled: May 6, 2010Publication date: June 16, 2011Inventors: Cheng-Chi Lin, Chen-Yuan Lin, Shih-Chin Lien, Shyi-Yuan Wu
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Publication number: 20110133269Abstract: A semiconductor apparatus includes, below a high-voltage wiring, a p? diffusion layer in contact with an n drain buffer layer and a p+ diffusion layer in contact with a p? diffusion layer for reducing the electric field strength in an insulator film, which the high-voltage wiring crosses over. Reducing electric field strength in the insulator film prevents lowering of breakdown voltage of a high-voltage NMOSFET, break down of an interlayer insulator film, and impairment of isolation breakdown voltage of a device isolation trench. The semiconductor apparatus according to the invention facilitates bridging a high-voltage wiring from a high-voltage NMOSFET and such a level-shifting device to a high-voltage floating region crossing over a device isolation trench without impairing the breakdown voltage of the high-voltage NMOSFET, without breaking down the interlayer insulator film and without impairing the isolation breakdown voltage of the device isolation trench.Type: ApplicationFiled: November 2, 2010Publication date: June 9, 2011Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventor: Masaharu YAMAJI
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Publication number: 20110133277Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.Type: ApplicationFiled: September 2, 2010Publication date: June 9, 2011Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 7956412Abstract: A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or may be formed utilizing the same processing steps as the formation of the drift region dielectric. A gate dielectric layer is formed on exposed semiconductor surfaces and a gate conductor layer is formed on the gate dielectric layer and the drift region dielectric. The field plate may be electrically tied to the gate electrode, may be an independent electrode having an external bias, or may be a floating electrode. The field plate biases the drift region to enhance performance and extend allowable operating voltage of a lateral diffusion field effect transistor during operation.Type: GrantFiled: December 4, 2007Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Natalie B. Feilchenfeld, Jeffrey P. Gambino, Louis D. Lanzerotti, Benjamin T. Voegeli, Steven H. Voldman, Michael J. Zierak
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Publication number: 20110127607Abstract: A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.Type: ApplicationFiled: December 2, 2009Publication date: June 2, 2011Applicant: Fairchild Semiconductor CorporationInventor: Jun Cai
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Publication number: 20110115020Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: ApplicationFiled: July 13, 2010Publication date: May 19, 2011Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young Chae, In-Taek OH
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Publication number: 20110115019Abstract: A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over a first portion of a channel region of the substrate, and a second portion forming a static gate formed over a second portion of the channel region and a transition region of the substrate. The static plate also extends over a drift region of the substrate, where the drift region is under a field oxide filled trench formed in the substrate. A switching voltage is applied to the switching gate and a constant voltage is applied to the static gate.Type: ApplicationFiled: November 13, 2009Publication date: May 19, 2011Applicant: MAXIM INTEGRATED PRODUCTS, INC.Inventors: Frederick Perry Giles, Joel M. McGregor, Stephen McCormack
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Patent number: 7943988Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.Type: GrantFiled: September 5, 2008Date of Patent: May 17, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Daniel Pham, Bich-Yen Nguyen
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Patent number: 7943986Abstract: A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ends of a cross bar of the T-shaped active region and a body contact region forms a leg of the T-shaped active region. A gate oxide layer is grown on the active region. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form a gate, where an end of the gate partially overlies the body contact region to complete formation of a Finfet device with body contact.Type: GrantFiled: June 12, 2007Date of Patent: May 17, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Nan Yang, Yi-Lang Chen, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu
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Publication number: 20110108916Abstract: Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques.Type: ApplicationFiled: November 6, 2009Publication date: May 12, 2011Applicant: Infineon Technologies AGInventors: Giovanni Calabrese, Domagoj Siprak, Wolfgang Molzer, Uwe Hodel
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Publication number: 20110101453Abstract: The invention provides a lateral double-diffused metal oxide semiconductor (LDMOS). The pre-metal dielectric layer (PMD) of the LDMOS is a silicon rich content material. Additionally, the inter-layer dielectric layer (ILD), inter-metal dielectric layer (IMD), or protective layer of the LDMOS may be formed of a silicon rich content material.Type: ApplicationFiled: October 30, 2009Publication date: May 5, 2011Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Kwang-Ming Lin, Ming-Cheng Lin, Yu-Long Chang
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Publication number: 20110101454Abstract: A P type semiconductor substrate includes a P type body region, an N type drift region formed away from the P type body region in a direction parallel to a substrate surface, an N type drain region formed in a region separated by a field oxide film in the N type drift region so as to have a concentration higher than the N type drift region, an N type source region formed in the P type body region so as to have a concentration higher than the N type drift region. A P type buried diffusion region having a concentration higher than the N type drift region is formed of a plurality of parts each of which is connected to a part of the bottom surface of the P type body region and extends parallel to the substrate surface and its tip end reaches the inside of the drift region.Type: ApplicationFiled: November 4, 2010Publication date: May 5, 2011Inventors: Hisao Ichijo, Alberto Adan
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Patent number: 7932136Abstract: In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.Type: GrantFiled: April 24, 2008Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Xuefeng Hua, Johnathan E. Faltermeier, Toshiharu Furukawa, Oleg Gluschenkov
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Publication number: 20110073944Abstract: According to one embodiment, a semiconductor device includes: a substrate in which, on a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type and a semiconductor layer of the second conductivity type are stacked; trench that define an element forming region in the substrate; element isolation insulation film formed in the trench; and a semiconductor element formed in the element forming region. The trench include first trench formed from the surface of the substrate to boundary depth and second trench formed from the boundary depth to the bottom and having a diameter smaller than that of the first trench. First diffusion layers connected to the buried layer are formed around the first or second trench according to inter-element breakdown voltage required of the semiconductor element.Type: ApplicationFiled: August 24, 2010Publication date: March 31, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tetsuya Tsukihara
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Publication number: 20110062517Abstract: According to one embodiment, a semiconductor device includes: a semiconductor substrate of a first conductivity type; a source region; a drain region of a second conductivity type; a gate electrode formed via a gate insulating film on the semiconductor substrate between the source region and the drain region; and a drift region of the second conductivity type formed adjacent to the drain region from the drain region to a lower part of the gate electrode. The upper surface of the gate electrode is formed such that the height of a side on the source region side of a stack of the gate electrode and the gate insulating film is larger than the height of a side on the drain region side of the stack.Type: ApplicationFiled: September 1, 2010Publication date: March 17, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Hiromichi YOSHINAGA