Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor includes a photodiode formed in a substrate structure, first to fourth gate electrodes formed over the substrate structure, spacers formed on both sidewalls of the first to fourth gate electrodes and filled between the third and fourth gate electrodes, a first ion implantation region formed in a portion of the substrate structure below the spacers filled between the third and fourth gate electrodes, and second ion implantation regions formed in portions of the substrate structure exposed between the spacers, the second ion implantation regions having a higher concentration than the first ion implantation region.

Abstract: A semiconductor structure in which the poly depletion and parasitic capacitance problems with poly-Si gate are reduced is provided as well as a method of making the same. The structure includes a thin poly-Si gate and optimized deep source/drain doping. The method changes the sequence of the different implantations steps and makes it possible to fabricate the structure without having dose loss or doping penetration problems. In accordance with the present invention, a sacrificial hard mask capping layer is used to block the high energy implantation and a 3-1 spacer (off-set spacer, first spacer and second spacer) scheme is used to optimize the source/drain doping profile. With this approach, the dose implanted into the thin poly-Si gate can be increased while the deep source/drain implantation can be optimized without worrying about the penetration problem.

Abstract: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

Abstract: A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.

Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus comprises a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween. The semiconductor apparatus further comprises a gate sidewall insulating film having a three-layered structure formed of a first nitride film, an oxide film, and a second nitride film, which are formed on a sidewall of an upper portion of the gate electrode, and a gate sidewall insulating film having a two-layered structure formed of the oxide film and the second nitride film, which are formed on a sidewall of a lower portion of the gate electrode. The semiconductor apparatus further comprises a raised source/drain region formed of an impurity region formed in a surface layer of the semiconductor substrate and an impurity region grown on the impurity region.

Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

Abstract: A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.

Abstract: A method for forming a thin-film transistor on an insulating substrate includes the steps of: forming a non-single-crystal semiconductor thin film on the insulating substrate; forming a gate insulating film on the non-single-crystal semiconductor thin film; forming a gate electrode including a lower gate electrode and an upper gate electrode on the gate insulating film, the lower gate electrode having a portion that is not covered by the upper gate electrode; forming a source-drain region and an LDD (lightly doped drain) region in the non-single-crystal thin film semiconductor film at a time by introducing an impurity into the non-single-crystal semiconductor thin film through the gate electrode and the gate insulating film; and etching away an exposed portion of the lower gate electrode by using the upper gate electrode as a mask.

Abstract: A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate structures are isolated from one another. One or more first double diffused regions are formed adjacent to the first gate structure in the semiconductor substrate. One or more second double diffused regions are formed adjacent to the second gate structure in the semiconductor substrate. One or more first source/drain regions are formed within the first double diffused regions. One or more second source/drain regions are formed within the second double diffused regions. The first double diffused regions function as one or more lightly doped source/drain regions for the low voltage device.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Abstract: A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands.

Abstract: A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers.

Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

Abstract: A semiconductor device that suppresses variation and a drop in the breakdown voltage of transistors. In the semiconductor device in which a logic transistor and a high-breakdown-voltage transistor are formed on one Si substrate, an insulating film which has an opening region and which is thick around the opening region is formed on a low concentration drain region formed in the Si substrate on one side of a gate electrode of the high-breakdown-voltage transistor. The insulating film around the opening region has a two-layer structure including a gate insulating film and a sidewall insulating film. When ion implantation is performed on the low concentration drain region beneath the opening region to form a high concentration drain region, the insulating film around the opening region prevents impurities from passing through.

Abstract: A CMOS structure including a Slim spacer and method for forming the same to reduce an S/D electrical resistance and improve charge mobility in a channel region, the method including providing a semiconductor substrate including a polysilicon gate structure including at least one overlying hardmask layer; forming spacers selected from the group consisting of oxide/nitride and oxide/nitride oxide layers adjacent the polysilicon gate structure; removing the at least one overlying hardmask layer to expose the polysilicon gate structure; carrying out an ion implant process; carrying out at least one of a wet and dry etching process to reduce the width of the spacers; and, forming at least one dielectric layer over the polysilicon gate structure and spacers in one of tensile and compressive stress.

Abstract: A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer is provided. The method further includes pre-amorphizing the source/drain region before the super annealing. The strained capping layer may further be formed on a pre-amorphized gate electrode, and the gate electrode is super annealed. The strain is generated and preserved after the removal of the strained capping layer.

Abstract: A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.

Abstract: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

Abstract: A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After formation of an LDD region a composite insulator spacer, comprised of an underlying silicon oxide spacer component and an overlying silicon nitride spacer component, is formed on the sides of a gate structure. Formation of a heavily doped source/drain is followed by removal of the silicon nitride spacer resulting in recessing of, and damage formation to, the heavily doped source/drain region, as well as recessing of the gate structure. Removal of a horizontal component of the silicon oxide spacer component results in additional recessing of the heavily doped source/drain region, and of the gate structure.

Abstract: A semiconductor structure includes a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers.

Abstract: Aspects of the invention can provide a transistor that can include a supporting substrate, a semiconductor film formed on an underlying insulating film provided on the supporting substrate and including a channel region and source and drain regions, and a gate electrode provided above the channel region. The semiconductor film can include a lightly doped region in which an impurity is injected at a low concentration between the channel region and the source and drain regions. The source and drain regions can include a heavily doped region in which an impurity is injected at a higher concentration than the lightly doped region. At least part of the lightly doped region provided along an inner wall of a groove can be provided on the supporting substrate.

Abstract: A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a vertical portion covering a side wall of the gate pattern, and a lateral portion extending from the bottom of the vertical portion over the source/drain region. Support portions interposed between the L-shaped spacers and the gate pattern support the lateral portions of the L-shaped spacers such that an air gap is defined between at least the lateral portions of the L-shaped spacers and the source/drain regions. The air gap minimizes the parasitic capacitance associated with the gate electrode of the semiconductor device.

Abstract: A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.