Abstract: A semiconductor device including a plurality of doped regions, a metal layer and a polysilicon layer is provided. The doped regions are disposed in a substrate. The metal layer includes a plurality of metal line patterns. The polysilicon layer disposed between the substrate and the metal layer includes a gate pattern and at least one guard ring pattern. The at least one guard ring pattern connects to the gate pattern and surrounds at least one of the metal line patterns. One of the metal line patterns connects to the gate pattern. The others of the metal line patterns connect to one of the doped regions in the substrate.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: Embodiments of the present invention provide a method that cools a substrate to a temperature below 10° C. and then implants ions into the substrate while the temperature of the substrate is below 10° C. The implanting causes damage to a first depth of the substrate to create an amorphized region in the substrate. The method forms a layer of metal on the substrate and heats the substrate until the metal reacts with the substrate and forms a silicide region within the amorphized region of the substrate. The depth of the silicide region is at least as deep as the first depth.

Abstract: System and method for metal-oxide-semiconductor field effect transistor. In a specific embodiment, the invention provides a field effect transistor (FET), which includes a substrate material, the substrate material being characterized by a first conductivity type, the substrate material including a first portion, a second portion, and a third portion, the third portion being positioned between the first portion and the second portion. The FET also includes a source portion positioned within the first portion, the source portion being characterized by a second conductivity type, the second conductivity type being opposite of the first conductivity type. A first drain portion is positioned within second portion and characterized by the second conductivity type and a first doping concentration.

Abstract: A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.

Abstract: The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.

Abstract: In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.

Abstract: A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.

Abstract: A method of manufacturing a semiconductor device may include implanting fluorine ions into a portion of a poly gate region on a semiconductor substrate; forming a gate oxide film over the semiconductor substrate such that the gate oxide film is thicker in the fluorine-implanted region; forming the poly gate over the gate oxide film in the poly gate region; and forming lightly doped drains in active regions of the semiconductor substrate on both sides of the poly gate. Further, the method of manufacturing the semiconductor device includes forming spacers over both sidewalls of the poly gate; and forming source and drain regions in the active regions.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A method may include forming a first well by injecting first conduction type impurity ions on and/or over a semiconductor substrate, forming an extended drain region overlapped with a region of said first well by injecting second conduction type impurities on and/or over a semiconductor substrate, and/or forming a first conduction type second well on and/or over a semiconductor substrate under an extended drain region to overlap with another region of a first well by injecting second conduction type impurities on and/or over a semiconductor substrate. A method may include forming a gate over a first well overlapped with an extended drain region, and/or forming a drain region by injecting second conduction type impurities on and/or over an extended drain region at one side of a gate.

Abstract: A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.

Abstract: The present invention discloses a semiconductor device with an asymmetric channel extension structure capable of storing charges, improving gate oxide reliability, reducing parasitic capacitance and adjusting its channel extension current or turn-on resistance. A gate dielectric is formed on the semiconductor substrate. A gate is formed on the gate dielectric. A first isolation layer is formed over the sidewall of the gate. Dielectric spacers are formed on the sidewall of the first isolation layer. And at least one of the p-n junctions of source and drain regions is formed under the dielectric spacers. A fringing field induced extension region formed adjacent to asymmetric channel under gate dielectric and close to at least one of said doped regions. A threshold voltage adjustment implantation region formed under gate dielectric An anti-punch-through implantation region formed under threshold voltage adjustment implantation region.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. The semiconductor device may include a semiconductor substrate, a gate insulation layer and a gate electrode, a first spacer, a second spacer, an epitaxial pattern, and/or source/drain regions. The gate insulation layer and the gate electrode may be formed on the semiconductor substrate. The first spacer may be formed on sidewalls of the gate electrode. The second spacer may be formed on sidewalls of the first spacer. The epitaxial pattern may be formed between the second spacer and the semiconductor substrate such that an outside profile of the epitaxial pattern is aligned with an outside profile of the second spacer. The source/drain regions may include primary source/drain regions that are aligned with the first spacer. The primary source/drain regions may be formed in the epitaxial pattern and the semiconductor substrate.

Abstract: A semiconductor device may include a semiconductor substrate, a salicide, a gate electrode, and an insulating layer. The semiconductor substrate has a lightly doped drain (LDD) region formed therein. The salicide is formed on the LDD region. The gate electrode is formed on the semiconductor substrate. The gate electrode has a stacked structure of a gate oxide and a metal layer. The insulating layer is formed on the semiconductor substrate and at a side of the gate electrode.

Abstract: The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

Abstract: The present disclosure relates to a semiconductor device and a method of forming the semiconductor device that includes forming a gate insulating film on a semiconductor substrate, forming a polysilicon layer containing fluorine on the gate insulating film, forming a gate pattern by patterning the gate insulating film and the polysilicon layer, forming a metal layer on the semiconductor substrate including the gate pattern, and reacting the metal layer with the patterned polysilicon layer to form an FUSI dual gate having a lower Si-rich silicide layer and an upper Ni-rich silicide layer. The present method can reliably control a work function of an FUSI dual gate formed thereby, improve a device performance and an NBTI characteristic by preventing Vfb from shifting. The present invention is generally applicable to high performance devices, as well as lower power devices and memory devices.

Abstract: Embodiments of the present invention are directed to an image sensor having pixel transistors and peripheral transistors disposed in a silicon substrate. For some embodiments, a protective coating is disposed on the peripheral transistors and doped silicon is epitaxially grown on the substrate to form lightly-doped drain (LDD) areas for the pixel transistors. The protective oxide may be used to prevent epitaxial growth of silicon on the peripheral transistors during formation of the LDD areas of the pixel transistors.

Abstract: A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; first and second spacers respectively formed on two side faces of the gate electrode; a gate sidewall formed on a side face of the first spacer; a channel region formed in the semiconductor substrate under the gate insulating film; first and second impurity diffused layers respectively formed on the first spacer side and the second spacer side of the channel region, the first impurity diffused layer including a first extension region in the gate electrode side thereon, the second impurity diffused layer including a second extension region in the gate electrode side thereon; a first silicide layer formed on the first impurity diffused layer; and a second silicide layer formed on the second impurity diffused layer, the channel region being closer to the second silicide layer than the first silicide layer.

Abstract: A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.

Abstract: Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region.

Abstract: A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).

Abstract: A semiconductor device, such as a PMOS or an NMOS transistor, having a stressed channel region is provided. The semiconductor device is formed by recessing the source/drain regions after forming a gate stack. The substrate is removed under the gate stack. Thereafter, an epitaxial layer is formed under the gate stack and in the source/drain regions. The epitaxial layer may be doped in the source/drain regions. In an embodiment, a lower portion of the epitaxial layer and the epitaxial layer under the gate stack may be doped with a conductivity type opposite of the conductivity type of the source/drain regions. In another embodiment of the present invention, a lower portion of the epitaxial layer is left undoped.

Abstract: An electrical device, including a semiconductor device such an electrostatic discharge protection semiconductor device, and a method for manufacturing the same. An electrostatic discharge protection semiconductor device may include a substrate and a gate in and/or over the substrate. The gate may be multi-layered, and may include a gate oxide layer and a gate electrode. An electrostatic discharge protection semiconductor device may include a source region formed in and/or over a predetermined area of the substrate on a side of the gate, and a plurality of drain regions which may be sequentially multi-layered in and/or over the substrate on an opposing side of the gate in a vertical direction. At least one drain region may be overlapped with the gate in a horizontal direction.

Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.

Abstract: A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, and a device isolation insulating film 132 and device isolation insulating film 134. Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134; and in the n-doped source region 114, the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.

Abstract: An electro-optical device includes a semiconductor layer including a channel region having a channel length along one of a first direction and a second direction, a source region having a source length along the second direction and electrically connected to a data line, a drain region having a drain length including a portion along the first direction and electrically connected to a pixel electrode, and a junction region formed between the channel region and the drain region, and bent in the drain region in plan view; a gate electrode including a main body portion facing the channel region with a gate insulating film interposed therebetween and an enclosure portion including an L-shaped portion enclosing the junction region along the portion bent in the drain region; and a sidewall portion rising or falling from the enclosure portion and including a portion arranged along the side of the second junction region.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: A method for manufacturing a semiconductor device includes: forming a device isolation layer in a semiconductor substrate; forming a gate insulating layer and a gate electrode on the semiconductor substrate; depositing a triple layer over the resulting structure, the triple layer including a bottom oxide layer, a nitride oxide layer and a top oxide layer; and etching the triple layer to form spacers.

Abstract: A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.

Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract: A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.

Abstract: Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain region, which contributes to a promotion of thermal conductivity (or thermal emission) in the drain region during a surge input and leads to suppression of local temperature increase, to thereby prevent thermal destruction. Therefore, it is possible to manufacture a power management semiconductor device or an analog semiconductor device with the extended possibility of transistor design.

Abstract: A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.

Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

Abstract: Sidewall spacers on the gate of a MOS device are formed from stressed material so as to provide strain in the channel region of the MOS device that enhances carrier mobility. In a particular embodiment, the MOS device is in a CMOS cell that includes a second MOS device. The first MOS device has sidewall spacers having a first (e.g., tensile) type of residual mechanical stress, and the second MOS device has sidewall spacers having a second (e.g., compressive) type of residual mechanical stress. Thus, carrier mobility is enhanced in both the PMOS portion and in the NMOS portion of the CMOS cell.

Abstract: An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region of and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.

Abstract: A semiconductor device includes a MOSFET having: a gate electrode provided over a silicon substrate; and a first impurity diffusion region and a second impurity diffusion region provided in the silicon substrate in different sides of said first gate electrode, wherein the MOSFET has an extension region in an upper section of the first impurity diffusion region and no extension region in an upper section of the second impurity diffusion region, and has a first silicide layer over the first impurity diffusion region and has no silicide layer over the second impurity diffusion region in vicinity of a side edge of the gate electrode.

Abstract: A MOS device having reduced recesses under a gate spacer and a method for forming the same are provided. The MOS device includes a gate structure overlying the substrate, a sidewall spacer on a sidewall of the gate structure, a recessed region having a recess depth of substantially less than about 30 ? underlying the sidewall spacer, and a silicon alloy region having at least a portion in the substrate and adjacent the recessed region. The silicon alloy region has a thickness of substantially greater than about 30 nm. A shallow recess region is achieved by protecting the substrate when a hard mask on the gate structure is removed. The MOS device is preferably a pMOS device.

Abstract: A semiconductor device 1 according to one embodiment of the invention includes: a semiconductor substrate 10; a convex region 12 provided on the semiconductor substrate 10; a gate insulating film 100 provided on the convex region 12; a channel region 101 located in the convex region 12 under the gate insulating film 100; source/drain regions 115 provided on both sides of the convex region 12 and having extensions 115a on both sides of the channel region 101; and a halo layer 110 provided between the convex region 12 and the source/drain region 115 so as to contact with the convex region 12.

Abstract: A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.

Abstract: The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.

Abstract: A Metal Oxide Semiconductor device includes a semiconductor substrate; a gate electrode formed on the surface of the substrate, having an offset spacer on each side; source/drain electrodes in the substrate having lightly doped regions respectively; metal silicide located on the gate electrode and the source/drain electrodes; and first impurity ions and second impurity ions in the lightly doped regions. A method for manufacturing a Metal Oxide Semiconductor device includes forming a gate electrode on a semiconductor substrate; implanting first impurity ions and second impurity ions to form lightly doped regions; depositing a dielectric layer and etching the dielectric layer to form offset spacers; implanting the first impurity ions to form the source/drain electrodes; forming metal silicide on the surfaces of the gate electrode and the source/drain regions. This invention can effectively prevent metal nickel diffusion into the lightly doped regions.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Abstract: First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1? of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2? of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.

Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

Abstract: A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-conductivity type first impurity being diffused in the extension diffusion layers, and source and drain diffusion layers provided in regions farther outside than the respective extension diffusion layers of the semiconductor region and having junction depths deeper than the respective extension diffusion layers. At least one of the extension diffusion layers on both sides of the gate electrode contains carbon.

Abstract: A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes: Lower device bulk layer. Upper source and upper drain region both located atop lower device bulk layer. Both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer. Both upper drain and upper body region are shaped to form a drain-body interface. The drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region. Gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.

Abstract: A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.