With Top Gate (epo) Patents (Class 257/E29.293)
  • Patent number: 9070717
    Abstract: A method of fabricating an organic light emitting diode (OLED) display device having a thin film transistor including a polysilicon layer. The method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 30, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Hyun Lee, Ki-Yong Lee, Jin-Wook Seo, Tae-Hoon Yang, Yun-Mo Chung, Byoung-Keon Park, Kil-Won Lee, Jong-Ryuk Park, Bo-Kyung Choi, Byung-Soo So
  • Patent number: 8921962
    Abstract: A magnetostrictive-piezoelectric multiferroic single- or multi-domain nanomagnet whose magnetization can be rotated through application of an electric field across the piezoelectric layer has a structure that can include either a shape-anisotropic mangnetostrictive nanomagnet with no magnetocrystalline anisotropy or a circular nanomagnet with biaxial magnetocrystalline anisotropy with dimensions of nominal diameter and thickness. This structure can be used to write and store binary bits encoded in the magnetization orientation, thereby functioning as a memory element, or perform both Boolean and non-Boolean computation, or be integrated with existing magnetic tunneling junction (MTJ) technology to perform a read operation by adding a barrier layer for the MTJ having a high coercivity to serve as the hard magnetic layer of the MTJ, and electrical contact layers of a soft material with small Young's modulus.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: December 30, 2014
    Assignee: Virginia Commonwealth University
    Inventors: Jayasimha Atulasimha, Supriyo Bandyopadhyay
  • Patent number: 8853590
    Abstract: A device for irradiating a laser beam onto an amorphous silicon thin film formed on a substrate. The device includes: a stage mounting the substrate; a laser oscillator for generating a laser beam; a projection lens for focusing and guiding the laser beam onto the thin film; a reflector for reflecting the laser beam guided onto the thin film; a controller for controlling a position of the reflector; and an absorber for absorbing the laser beam reflected by the reflector.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: October 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Jae Kim, Myung-Koo Kang
  • Patent number: 8846514
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang Ho Park, Yoon Ho Khang, Se Hwan Yu, Yong Su Lee, Chong Sup Chang, Myoung Geun Cha, Hyun Jae Na
  • Patent number: 8815663
    Abstract: A method of manufacturing a TFT, including forming a buffer layer, an amorphous silicon layer, an insulating layer, and a first conductive layer on a substrate, forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer, forming a semiconductor layer, a gate insulating layer, and a gate electrode that have a predetermined shape by simultaneously patterning the polycrystalline silicon layer, the insulating layer, and the first conductive layer, wherein the polycrystalline silicon layer is further etched to produce an undercut recessed a distance compared to sidewalls of the insulating layer and the first conductive layer, forming source and drain regions within the semiconductor layer by doping corresponding portions of the semiconductor layer, forming an interlayer insulating layer on the gate electrode, the interlayer insulating layer covering the gate insulating layer and forming source and drain electrodes that are electrically connected to source and drain regions respectively.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 26, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Tak-Young Lee, Jin-Wook Seo, Ki-Yong Lee
  • Patent number: 8748222
    Abstract: A method for manufacturing oxide thin film transistors includes steps of: forming a gate, a drain electrode, a source electrode, and an oxide semiconductor layer respectively. The oxide semiconductor layer is formed on the gate electrode; the drain electrode and the source electrode are formed at two opposite sides of the oxide semiconductor layer. The method further includes a step of depositing a dielectric layer of silicon oxide, and a reacting gas for depositing the silicon oxide includes silane and nitrous oxide. A flow rate of nitrous oxide is in a range from 10 to 200 standard cubic centimeters per minute (SCCM). Oxide thin film transistors manufactured by above method has advantages of low leakage, high mobility, and other integrated circuit member can be directly formed on the thin film transistor array substrate of a display device.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: June 10, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Ted-Hong Shinn, Henry Wang, Fang-An Shu, Yao-Chou Tsai
  • Patent number: 8653569
    Abstract: An electric-field blocking film is provided between a BL insulation film and BL insulation film of a transistor, and a blocking film includes those three layers. The electric-field blocking film blocks an electric field produced by a drain electrode, a source electrode, and an n+-Si film. Even if misalignment of the drain electrode, the source electrode, and the n+-Si film in each drive transistor varies to make a portion overlying an i-Si film larger, therefore, the electric field at this portion is blocked by the electric-field blocking film, thereby making a variation in characteristic smaller.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: February 18, 2014
    Assignee: Casio Computer Co., Ltd.
    Inventors: Yukio Kashio, Tatsuya Miyakawa
  • Patent number: 8623746
    Abstract: A method of crystallizing a silicon layer. An amorphous silicon layer is formed on a buffer layer on a substrate. A catalyst metal layer is formed on the amorphous silicon layer to have a density of from about 1011 to about 1015 atom/cm2. A crystalline seed having a pyramid shape is formed on an interface between the amorphous silicon layer and the buffer layer as a catalyst metal of the catalyst metal layer diffuses into the amorphous silicon layer. The amorphous silicon layer is thermal-treated so that a polysilicon layer is formed as a silicon crystal grows by the crystallization seed.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Mo Chung, Ki-Yong Lee, Jin-Wook Seo, Kil-Won Lee, Bo-Kyung Choi
  • Patent number: 8597968
    Abstract: An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 3, 2013
    Assignee: Au Optronics Corporation
    Inventors: Yu-Cheng Chen, Chen-Yueh Li, Ching-Sang Chuang, Ching-Chieh Shih, An-Thung Cho
  • Publication number: 20130175534
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. In one embodiment, the semiconductor device includes a substrate, a first silicon nitride layer formed over the substrate, a first silicon oxide layer formed directly on the first silicon nitride layer and having a thickness of about 1000 ? or less, and a hydrogenated polycrystalline silicon layer formed directly on the first silicon oxide layer.
    Type: Application
    Filed: May 22, 2012
    Publication date: July 11, 2013
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Yun-Mo Chung, Ki-Yong Lee, Jin-Wook Seo, Jong-Ryuk Park
  • Patent number: 8445944
    Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 21, 2013
    Assignee: Sony Corporation
    Inventors: Takayuki Ezaki, Teruo Hirayama
  • Publication number: 20130092942
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.
    Type: Application
    Filed: July 27, 2012
    Publication date: April 18, 2013
    Inventors: SANG HO PARK, Yoon Ho Khang, Se Hwan Yu, Yong Su Lee, Chong Sup Chang, Myoung Geun Cha, Hyun Jae Na
  • Publication number: 20130020578
    Abstract: The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: an active fin region which is arranged on an insulating layer; a threshold voltage adjusting layer arranged on top of the active fin region, which threshold voltage adjusting layer is used to adjust the threshold voltage of the semiconductor device; a gate stack which is arranged on the threshold voltage adjusting layer, on the sidewalls of the active fin region and on the insulating layer, and comprises a gate dielectric and a gate electrode formed on the gate dielectric; and a source region and a drain region formed in the active fin region on both sides of the gate stack respectively. The semiconductor device according to the invention comprises the threshold voltage adjusting layer which may adjust the threshold voltage of the semiconductor device.
    Type: Application
    Filed: November 30, 2011
    Publication date: January 24, 2013
    Inventors: Qingqing Liang, Huilong Zhu, Huicai Zhong
  • Publication number: 20130001561
    Abstract: A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 3, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Etsuko Fujimoto, Satoshi Murakami, Shunpei Yamazaki, Shingo Eguchi
  • Publication number: 20130001556
    Abstract: A thin film transistor and a press sensing device using the thin film transistor are disclosed. The thin film transistor, comprises a source electrode; a drain electrode spaced from the source electrode; a semiconductor layer electrically connected with the source electrode and the drain electrode, a channel defined in the semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode electrically insulated from the semiconductor layer; and an insulative layer configured for insulating the source electrode, the drain electrode, and the semiconductor layer from each other, wherein the insulative layer is made of a polymeric material with an elastic modulus ranged from about 0.1 megapascal (MPa) to about 10 MPa.
    Type: Application
    Filed: December 13, 2011
    Publication date: January 3, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: CHUN-HUA HU, CHANG-HONG LIU, SHOU-SHAN FAN
  • Publication number: 20120326157
    Abstract: A method of manufacturing a TFT, including forming a buffer layer, an amorphous silicon layer, an insulating layer, and a first conductive layer on a substrate, forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer, forming a semiconductor layer, a gate insulating layer, and a gate electrode that have a predetermined shape by simultaneously patterning the polycrystalline silicon layer, the insulating layer, and the first conductive layer, wherein the polycrystalline silicon layer is further etched to produce an undercut recessed a distance compared to sidewalls of the insulating layer and the first conductive layer, forming source and drain regions within the semiconductor layer by doping corresponding portions of the semiconductor layer, forming an interlayer insulating layer on the gate electrode, the interlayer insulating layer covering the gate insulating layer and forming source and drain electrodes that are electrically connected to source and drain regions respectively.
    Type: Application
    Filed: December 7, 2011
    Publication date: December 27, 2012
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Tak-Young Lee, Jin-Wook Seo, Ki-Yong Lee
  • Publication number: 20120305928
    Abstract: A Field Effect Transistor (FET) device includes a gate stack formed over a channel region, a source region adjacent to the channel region, wherein a portion of a boundary between the source region and the channel region is defined along a plane defined by a sidewall of the gate stack, a drain region adjacent to the channel region, a portion of the drain region arranged below the gate stack, a native oxide layer disposed over a portion of the source region, along sidewalls of the gate stack, and over a portion of the drain region, a spacer arranged over a portion of the native oxide layer above the source region and the drain region and along the native oxide layer along the sidewalls of the gate stack.
    Type: Application
    Filed: August 2, 2012
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C. Fuller, Steve Koester, Isaac Lauer, Ying Zhang
  • Publication number: 20120299007
    Abstract: There is provided a thin film transistor including an active layer on a substrate (the active layer including polysilicon and a metal catalyst dispersed in the polysilicon, a source area, a drain area, and a channel area), a gate electrode disposed on the channel area of the active layer, a source electrode electrically connected to the source area, and a drain electrode electrically connected to the drain area, wherein the gate electrode, the source area, and the drain area of the active layer include metal ions, the source area and the drain area are separate from each other, and the channel is disposed between the source area and the drain area.
    Type: Application
    Filed: April 18, 2012
    Publication date: November 29, 2012
    Inventors: Yun-Mo CHUNG, Jin-Wook SEO, Tak-Young LEE
  • Patent number: 8319219
    Abstract: According to present invention, system on panel without complicating the process of TFT can be realized, and a light-emitting device that can be formed by lower cost than that of the conventional light-emitting device can be provided. A light-emitting device is provided in which a pixel portion is provided with a pixel including a light-emitting element and a TFT for controlling supply of current to the light-emitting element; a TFT included in a drive circuit and a TFT for controlling supply of current to the light-emitting element include a gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor film, which overlaps with the gate electrode via the gate insulating film, a pair of second semiconductor films formed over the first semiconductor film; the pair of second semiconductor films are doped with an impurity to have one conductivity type; and the first semiconductor film is formed by semiamorphous semiconductor.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8227808
    Abstract: An organic light emitting diode (OLED) display and thin film transistor (TFT) manufacturing method thereof are disclosed. According to the present invention, poly-silicon layers for forming active areas of non-driving TFT (e.g. peripheral circuit TFT and switch TFT) and driving TFT used in the OLED display are respectively made by using standard laser crystallization method and non-laser crystallization method or low energy laser crystallization method. Therefore, the peripheral circuit TFT has excellent electrical performance such as high carrier mobility, while the OLED-driving TFT has good stability so that the resultant display can operate with improved luminance uniformity.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: July 24, 2012
    Assignee: Chimei Innolux Corporation
    Inventors: Te-Chang Wan, Yu-Chung Liu, Te-Yu Lee
  • Publication number: 20120168754
    Abstract: A transistor is formed having a thin film metal channel region. The transistor may be formed at the surface of a semiconductor substrate, an insulating substrate, or between dielectric layers above a substrate. A plurality of transistors each having a thin film metal channel region may be formed. Multiple arrays of such transistors can be vertically stacked in a same device.
    Type: Application
    Filed: December 29, 2010
    Publication date: July 5, 2012
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventors: Olivier Le Neel, Ravi Shankar, Calvin Leung
  • Patent number: 8188476
    Abstract: The present invention provides an organic EL display and a method of manufacturing the same capable of assuring excellent electric connection between an auxiliary wiring and a second electrode without using large-scale equipment. The organic EL display includes: a plurality of pixels each having, in order from a substrate side, a first electrode, an organic layer including a light emission layer, and a second electrode; an auxiliary wiring disposed in a periphery region of each of the plurality of pixels and conducted to the second electrode; and another auxiliary wiring disposed apart from the auxiliary wiring at least in a part of outer periphery of a formation region of the auxiliary wiring in a substrate surface.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: May 29, 2012
    Assignee: Sony Corporation
    Inventors: Kazunari Takagi, Kazuo Nakamura
  • Patent number: 8178877
    Abstract: Disclosed are a thin film transistor having high reliability and providing a simplified fabricating process, and a method of fabricating the thin film transistor. In the method, a dielectric substrate is prepared, a semiconductor layer is formed on the dielectric substrate, a gate dielectric film is formed on the semiconductor layer, a first gate electrode is formed on the gate dielectric film, a second gate electrode contacting a side wall of the first gate electrode is formed, and impurities are implanted into the semiconductor layer using the first gate electrode as a mask.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: May 15, 2012
    Assignee: SNU R & DB Foundation
    Inventors: Sun Jae Kim, Min Koo Han
  • Publication number: 20120091462
    Abstract: A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. The dielectric layer is associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P? polysilicon layer overlying the co-planar surface, an oxide-nitride-oxide (ONO) layer overlying the P? polysilicon layer; and at least one control gate overlying the ONO layer. The control gate may be made of a metal layer or a P+ polysilicon layer.
    Type: Application
    Filed: December 20, 2011
    Publication date: April 19, 2012
    Applicant: Semiconductor Manufacturing International (Shanghai ) Corporation
    Inventor: MIENO FUMITAKE
  • Publication number: 20120049199
    Abstract: A method of forming a polycrystalline layer includes forming a buffer layer on a substrate; treating the buffer layer with hydrogen plasma; forming an amorphous silicon layer on the buffer layer; forming a metallic catalyst layer for crystallizing the amorphous silicon layer on the amorphous silicon layer; and heat treating the amorphous silicon layer to form a polycrystalline silicon layer.
    Type: Application
    Filed: August 15, 2011
    Publication date: March 1, 2012
    Inventors: Yun-Mo Chung, Ki-Yong Lee, Jin-Wook Seo, Min-Jae Jeong, Seung-Kyu Park, Yong-Duck Son, Byung-Soo So, Byoung-Keon Park, Kil-Won Lee, Dong-Hyun Lee, Tak-Young Lee, Jong-Ryuk Park
  • Patent number: 8089071
    Abstract: A thin film semiconductor device is provided. The semiconductor device includes a semiconductor thin film configured to have an active region turned into a polycrystalline region through irradiation with an energy beam, and a gate electrode configured to be provided to traverse the active region. Successive crystal grain boundaries extend along the gate electrode in a channel part that is the active region overlapping with the gate electrode, and the crystal grain boundaries traverse the channel part and are provided cyclically in a channel length direction.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: January 3, 2012
    Assignee: Sony Corporation
    Inventors: Akio Machida, Toshio Fujino, Tadahiro Kono
  • Patent number: 8088639
    Abstract: A solid-state image pickup device includes a semiconductor substrate within which a pixel comprised of a photodiode and a transistor is formed. The transistor is formed at a surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode is provided within the semiconductor substrate and a part of the pn junction portion of the photodiode is extended to a lower portion of the transistor formed at the surface of the semiconductor substrate.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: January 3, 2012
    Assignee: Sony Corporation
    Inventors: Takayuki Ezaki, Teruo Hirayama
  • Publication number: 20110284861
    Abstract: A method for manufacturing a low-temperature polysilicon thin film comprises the steps of providing a substrate and forming a buffer layer on the substrate; forming a first amorphous silicon thin film on the buffer layer; forming catalyst particles on the first amorphous silicon thin film; forming a second amorphous silicon thin film to cover the first amorphous silicon thin film and the catalyst particles; and performing a crystallization of the first and second amorphous silicon thin films by using the catalyst particles so as to form the low-temperature polysilicon thin film.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 24, 2011
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Won Seok KIM, Pil Seok KIM
  • Publication number: 20110253987
    Abstract: A method of crystallizing a silicon layer. An amorphous silicon layer is formed on a buffer layer on a substrate. A catalyst metal layer is formed on the amorphous silicon layer to have a density of from about 1011 to about 1015 atom/cm2. A crystalline seed having a pyramid shape is formed on an interface between the amorphous silicon layer and the buffer layer as a catalyst metal of the catalyst metal layer diffuses into the amorphous silicon layer. The amorphous silicon layer is thermal-treated so that a polysilicon layer is formed as a silicon crystal grows by the crystallization seed.
    Type: Application
    Filed: January 24, 2011
    Publication date: October 20, 2011
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Yun-Mo CHUNG, Ki-Yong Lee, Jin-Wook Seo, Kil-Won Lee, Bo-Kyung Choi
  • Publication number: 20110254004
    Abstract: A semiconductor device manufactured utilizing an SOI substrate, in which defects due to an end portion of an island-shaped silicon layer are prevented and the reliability is improved, and a manufacturing method thereof. The following are included: an SOI substrate in which an insulating layer and an island-shaped silicon layer are stacked in order over a support substrate; a gate insulating layer provided over one surface and a side surface of the island-shaped silicon layer; and a gate electrode which is provided over the island-shaped silicon layer with the gate insulating layer interposed therebetween. The gate insulating layer is formed such that the dielectric constant in the region which is in contact with the side surface of the island-shaped silicon layer is lower than that over the one surface of the island-shaped silicon layer.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 20, 2011
    Inventors: Shunpei YAMAZAKI, Kazuko IKEDA, Shinya SASAGAWA, Hideomi SUZAWA
  • Publication number: 20110241012
    Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 6, 2011
    Inventors: Shunpei Yamazaki, Hiroki Adachi
  • Publication number: 20110198592
    Abstract: Disclosed are a thin film transistor having high reliability and providing a simplified fabricating process, and a method of fabricating the thin film transistor. In the method, a dielectric substrate is prepared, a semiconductor layer is formed on the dielectric substrate, a gate dielectric film is formed on the semiconductor layer, a first gate electrode is formed on the gate dielectric film, a second gate electrode contacting a side wall of the first gate electrode is formed, and impurities are implanted into the semiconductor layer using the first gate electrode as a mask.
    Type: Application
    Filed: June 4, 2010
    Publication date: August 18, 2011
    Applicant: SNU R&DB FOUNDATION
    Inventors: Sun Jae Kim, Min Koo Han
  • Publication number: 20110180799
    Abstract: An electronic device comprises at least one static induction transistor (14; 114; 214) and at least one thin film transistor (16; 116). The static induction transistor (14; 114; 214) has a first channel (14.4; 114.4; 214.4) of a semi conducting material extending between a first main electrode (14.2; 114.2; 214.2) and a second main electrode (14.3; 114.3) through a first and a second insulating layer (11, 13; 111, 113), and has a first control electrode (14.1; 114.1) surrounding the first channel and extending between the first and the second insulating layer. The thin film transistor (16; 116) has a third main electrode (16.2; 116.2) and a fourth main electrode (16.3; 116.3) coupled by a second channel (16.4; 116.4) of a semi conducting material and a second control electrode (16.1; 116.1). At least one of the first and the second insulating layer functions as a dielectric layer between the second control electrode and the second channel.
    Type: Application
    Filed: July 8, 2009
    Publication date: July 28, 2011
    Applicant: Creator Technology B.V.
    Inventors: Kevin Michael O'Neill, Petrus Johannes Gerardus van Lieshout
  • Patent number: 7955890
    Abstract: Embodiments of the present invention relate to methods for depositing an amorphous film that may be suitable for using in a NIP photodiode in display applications. In one embodiment, the method includes providing a substrate into a deposition chamber, supplying a gas mixture having a hydrogen gas to silane gas ratio by volume greater than 4 into the deposition chamber, maintaining a pressure of the gas mixture at greater than about 1 Torr in the deposition chamber, and forming an amorphous silicon film on the substrate in the presence of the gas mixture, wherein the amorphous silicon film is configured to be an intrinsic-type layer in a photodiode sensor.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: June 7, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Soo Young Choi, Jriyan Jerry Chen, Tae Kyung Won, Dong-Kil Yim
  • Publication number: 20110121308
    Abstract: Provided are a thin film transistor including a polycrystalline silicon layer having improved crystallinity by applying Joule heat to form stress gradient in a glass substrate that is disposed under an amorphous silicon layer from a surface to a predetermined depth of the glass substrate, thereby crystallizing the amorphous silicon layer into a polycrystalline silicon layer, and a method of fabricating the same. The film transistor includes a glass substrate having stress gradient from an upper surface to a predetermined depth, a semiconductor layer disposed on the glass substrate, and formed of a polycrystalline silicon layer crystallized by Joule heating, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer, and electrically connected to source and drain regions of the semiconductor layer.
    Type: Application
    Filed: July 8, 2009
    Publication date: May 26, 2011
    Applicant: ENSILTECH CORPORATION
    Inventors: Jae-Sang Ro, Won-Eui Hong
  • Patent number: 7939402
    Abstract: A method for manufacturing a semiconductor apparatus is disclosed. The apparatus comprises double poly bipolar transistors and double poly metal oxide semiconductor (MOS) transistors. The bipolar transistors and the MOS transistors are manufactured in a unified process in which a first polysilicon layer (Poly1) is doped to form the extrinsic bases in the bipolar transistors and to form the gates in the MOS transistors. A second polysilicon layer (Poly2) is doped to form emitters in the bipolar transistors and to form the sources and drains in the MOS transistors. The method of the invention minimizes the number of manufacturing process steps.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: May 10, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Richard W. Foote, Robert Oliver
  • Patent number: 7927931
    Abstract: A liquid crystal display device may comprise a semiconductor layer on a substrate and including a channel portion and ohmic contact portions at both sides of the channel portion, wherein an edge portion of the semiconductor layer has a side surface of a substantially tapered shape; a gate insulating layer covering the semiconductor layer; a gate electrode on the gate insulating layer and substantially corresponding to the channel portion; source and drain electrodes contacting the semiconductor layer; and a pixel electrode contacting the drain electrode.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: April 19, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Joon Young Yang, Jae Young Oh, Soopool Kim
  • Patent number: 7902002
    Abstract: When a semi-conductor film is irradiated with conventional pulsed laser light, unevenness, which is called as ridge, is caused on the surface of the semiconductor film. In the case of a top-gate type TFT, element characteristics are changed depending on the ridge. In particular, there is a problem in that variation in the plural thin film transistors electrically connected in parallel with one another. According to the present invention, in manufacturing a circuit including plural thin film transistors, the width LP of a region (not including a microcrystal region) that is melted by irradiating a semiconductor film with light of a continuous wave laser is enlarged, and active layers of a plurality of thin film transistors (that are electrically connected in parallel with one another) are arranged in one region.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: March 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Publication number: 20110037073
    Abstract: A thin film transistor (TFT), an OLED device having the TFT and a method of fabricating the same and a method of fabricating an organic light emitting diode (OLED) display device that includes the TFT. The method of fabricating a TFT includes providing a substrate, forming a buffer layer on the substrate, forming an amorphous silicon layer pattern on the buffer layer, forming a metal layer on an entire surface of the substrate, forming a semiconductor layer by applying an electrical field to the metal layer to crystallize the amorphous silicon layer pattern, forming source and drain electrodes connected to the semiconductor layer by patterning the metal layer, forming a gate insulating layer on the entire surface of the substrate, forming a gate electrode on the gate insulating layer to correspond to the semiconductor layer and forming a protective layer on the entire surface of the substrate.
    Type: Application
    Filed: March 5, 2010
    Publication date: February 17, 2011
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventors: JI-SU AHN, WON-PIL LEE
  • Publication number: 20110037074
    Abstract: A thin film transistor includes a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, source and drain electrodes directly on the semiconductor layer, each of the source and drain electrodes including at least one hole therethrough, a gate insulating layer on the substrate, and a gate electrode on the gate insulating layer and corresponding to the semiconductor layer.
    Type: Application
    Filed: March 12, 2010
    Publication date: February 17, 2011
    Inventors: Ji-Su Ahn, Hoon-Kee Min
  • Patent number: 7888682
    Abstract: A thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; a gate electrode disposed on the insulating layer over the channel region; an passivation layer disposed on the gate electrode and the gate insulating layer; a source electrode disposed in contact with upper, lower and side surfaces of the source region via a first contact hole through passivation layer, the gate insulating layer and the semiconductor layer; and a drain electrode disposed in contact with upper, lower and side surfaces of the drain region via a second contact hole through the passivation layer, the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: February 15, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: Jae-Bum Park
  • Patent number: 7863113
    Abstract: A transistor for active matrix display and a method for producing the transistor (1). The transistor (1) includes a microcrystalline silicon film (5) and an insulator (3). The crystalline fraction of the microcrystalline silicon film (5) is above 80%. According to the invention, the transistor (1) includes a plasma treated interface (4) located between the insulator (3) and the microcrystalline silicon film (5) so that the transistor (1) has a linear mobility equal or superior to 1.5 cm2V?1s?1, shows threshold voltage stability and wherein the microcrystalline silicon film (5) includes grains (6) whose size ranges between 10 nm and 400 nm. The invention concerns as well a display unit having a line-column matrix of pixels that are actively addressed, each pixel comprising at least a transistor as described above.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: January 4, 2011
    Assignees: Centre National de la Recherche Scientifique, Ecole Polytechnique
    Inventors: Pere Roca I Cabarrocas, Régis Vanderhaghen, Bernard Drevillon
  • Patent number: 7834356
    Abstract: To provide a thin film transistor having a high field effect mobility and a small variation in characteristics thereof, a second amorphous semiconductor layer patterned in a predetermined shape is formed on a first crystalline semiconductor layer 17 for constituting source and drain regions. By irradiating an irradiated region 21 of continuous wave laser beam while scanning along a channel length direction, the second amorphous semiconductor layer is crystallized to form a second crystalline semiconductor layer 22. The first crystalline semiconductor layer 17 is crystallized by selectively adding nickel and therefore, an orientation rate of {111} is increased.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: November 16, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masahiko Hayakawa
  • Publication number: 20100244036
    Abstract: A thin film transistor, a method of fabricating the same, and an organic light emitting diode (OLED) display device including the same. The thin film transistor includes a substrate; a semiconductor layer disposed on the substrate and including a channel region; source/drain regions including ions and an offset region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer; a first insulating layer disposed on the gate electrode; a second insulating layer disposed on the first insulating layer; and source/drain electrodes disposed on the second insulating layer, and electrically connected to the source/drain regions of the semiconductor layer, respectively. The sum of thicknesses of the gate insulating layer and the first insulating layer that are on the source/drain regions is less than the vertical dispersion depth of the ions included in the source/drain regions.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 30, 2010
    Applicant: Samsung Mobile Display Co., Ltd
    Inventors: Byoung-Keon PARK, Tae-Hoon Yang, Jin-Wook Seo, Ki-Yong Lee, Hyun-Gue Kim, Maxim Lisachenko, Dong-Hyun Lee, Kil-Won Lee, Jong-Ryuk Park, Bo-Kyung Choi
  • Publication number: 20100244037
    Abstract: A thin film transistor (TFT) is provided which is capable of reducing leakage currents in a polycrystalline silicon TFT without causing an increase in manufacturing processes. Source/drain regions of an activated layer of the TFT to be formed in a circuit region and pixel region formed on a glass substrate of a liquid crystal display panel for a mobile phone is formed so that its boron impurity falls within a range of 2.5×1018/cm3 to 5.5×1018/cm3 and its impurity activation falls within a range of 1% to 7%.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 30, 2010
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventor: KUNIHIRO SHIOTA
  • Publication number: 20100237353
    Abstract: A thin film transistor includes a gate electrode, a gate insulation layer on the gate electrode, source and drain electrodes formed on the gate insulation layer, a polysilicon channel layer overlapping the ohmic contact layers and on the gate insulation layer between the source and drain electrodes, ohmic contact regions over the source and drain electrodes for contacting the polysilicon channel to the source and drain electrodes, and doping layers over the source and drain electrodes.
    Type: Application
    Filed: June 1, 2010
    Publication date: September 23, 2010
    Inventors: Gee Sung CHAE, Seung Hwan CHA
  • Publication number: 20100224882
    Abstract: A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device having the same, the thin film transistor including: a substrate; a silicon layer formed on the substrate; a diffusion layer formed on the silicon layer; a semiconductor layer that is crystallized using a metal catalyst, formed on the diffusion layer; a gate electrode disposed on the diffusion layer, facing a channel region of the semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and source and drain electrodes electrically connected to source and drain regions of the semiconductor layer.
    Type: Application
    Filed: February 25, 2010
    Publication date: September 9, 2010
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Dong-Hyun LEE, Ki-Yong Lee, Jin-Wook Seo, Tae-Hoon Yang, Byoung-Keon Park, Kil-Won Lee, Maxim Lisachenko, Jae-Wan Jung
  • Patent number: 7791076
    Abstract: A thin film transistor and a liquid crystal display, in which a gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: September 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-Koo Kang, Hyun-Jae Kim, Sook-Young Kang, Woo-Suk Chung
  • Patent number: 7790487
    Abstract: A method for fabricating a photo sensor on an amorphous silicon thin film transistor panel includes forming a photo sensor with a bottom electrode, a silicon-rich dielectric layer, and a top electrode, such that the light sensor has a high reliability. The fabrication method is compatible with the fabrication process of a thin film transistor.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: September 7, 2010
    Assignee: AU Optronics Corp.
    Inventors: Ching-Chieh Shih, An-Thung Cho, Chia-Tien Peng, Kun-Chih Lin
  • Patent number: 7777231
    Abstract: A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n+ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: August 17, 2010
    Assignee: AU Optronics Corp.
    Inventors: Feng-Yuan Gan, Han-Tu Lin