With Top Gate (epo) Patents (Class 257/E29.293)
  • Patent number: 7772653
    Abstract: A method for manufacturing a semiconductor apparatus is disclosed. The apparatus comprises double poly bipolar transistors and double poly metal oxide semiconductor (MOS) transistors. The bipolar transistors and the MOS transistors are manufactured in a unified process in which a first polysilicon layer (Poly1) is doped to form the extrinsic bases in the bipolar transistors and to form the gates in the MOS transistors. A second polysilicon layer (Poly2) is doped to form emitters in the bipolar transistors and to form the sources and drains in the MOS transistors. The method of the invention minimizes the number of manufacturing process steps.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: August 10, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Richard W. Foote, Robert Oliver
  • Publication number: 20100193793
    Abstract: The present invention provides a circuit board having a reduced wiring area in a circuit portion and therefore suitably used for reduction in a display region of a display device, and further provides a display device including such a circuit board.
    Type: Application
    Filed: October 14, 2008
    Publication date: August 5, 2010
    Inventor: Hiroyuki Moriwaki
  • Patent number: 7754549
    Abstract: A method of manufacturing a thin film transistor array panel includes forming an amorphous silicon film on an insulating substrate; forming a sacrificial film having an embossed surface on the amorphous silicon film; contacting a metal plate with the sacrificial film and performing heat-treatment for crystallizing the amorphous silicon film to change the amorphous silicon film to a polycrystalline silicon film; removing the metal plate and the sacrificial film; patterning the polycrystalline silicon film to form a semiconductor; forming a gate insulating layer which covers the semiconductor; forming a gate line on the gate insulating layer, a portion of the gate line overlapping the semiconductor; heavily doping a conductive impurity into portions of the semiconductor to form a source region and a drain region; forming an interlayer insulating layer which covers the gate line and the semiconductor; and forming a data line and an output electrode connected to the source and drain regions, respectively, on the
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: July 13, 2010
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Jae-Beom Choi, Young-jin Chang, Yoon-Seok Choi, Seung-Hwan Shim, Han-Na Jo, Jung-Hoon Shin, Joon-Young Koh
  • Publication number: 20100163885
    Abstract: A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and including source and drain regions, each having a first metal catalyst crystallization region and a second metal catalyst crystallization region, and a channel region having the second metal catalyst crystallization region, a gate electrode disposed in a position corresponding to the channel region of the semiconductor layer, a gate insulating layer interposed between the semiconductor layer and the gate electrode to electrically insulate the semiconductor layer from the gate electrode, and source and drain electrodes electrically insulated from the gate electrode and electrically connected to the source and drain regions, respectively. An OLED display device includes the thin film transistor and a first electrode, an organic layer, and a second electrode electrically connected to the source and drain electrodes.
    Type: Application
    Filed: December 30, 2009
    Publication date: July 1, 2010
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Byoung-Keon PARK, Jin-Wook Seo, Tae-Hoon Yang, Kil-Won Lee, Dong-Hyun Lee, Maxim Lisachenko, Ki-Yong Lee
  • Publication number: 20100148155
    Abstract: A thin film transistor (TFT), a method of forming the same and a flat panel display device having the same are disclosed.
    Type: Application
    Filed: February 19, 2009
    Publication date: June 17, 2010
    Applicant: Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Byoung deog CHOI, Jun sin Yi, Sung wook Jung, Kyung soo Jang, Jae hyun Cho
  • Patent number: 7709842
    Abstract: An organic electroluminescent display (“OELD”) includes an organic light-emitting diode (“OLED”), a circuit region, and an interlayer dielectric (“ILD”) layer. The OLED is disposed in each of a plurality of pixels arranged on a substrate. The circuit region includes two or more thin film transistors (“TFTs”) and a storage capacitor. The ILD layer has two or more insulating layers and includes a first region disposed between both electrodes of the storage capacitor and a second region covering the TFTs. At least one of the insulating layers has a window exposing the insulating layer directly beneath the at least one insulating layer so that that the ILD layer is thinner in the first region than in the second region. Accordingly, it is possible to reduce an occupation area of the storage capacitor while maintaining the necessary capacitance of the storage capacitor and expanding the area of the luminescent region.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-sim Jung, Jany-yeon Kwon, Jong-man Kim, Kyung-bae Park, Takashi Noguchi
  • Publication number: 20100051959
    Abstract: The present invention provides a circuit board that includes high-performance thin film transistors whose characteristics are hardly varied thereamong in a monolithic circuit and also provide a display device including the circuit board. The circuit board of the present invention is a circuit board including a monolithic circuit including a thin film transistor on a substrate, wherein the thin film transistor includes a semiconductor layer, a gate insulating film, and a gate electrode, stacked in this order, a portion where the gate electrode overlaps with the semiconductor layer has an area of 40 ?m2 or less, and the gate electrode has a thickness of 300 nm or less.
    Type: Application
    Filed: April 25, 2008
    Publication date: March 4, 2010
    Inventor: Hiroyuki Moriwaki
  • Publication number: 20100006855
    Abstract: A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device having the TFT. The TFT includes: a substrate; a polycrystalline silicon (poly-Si) semiconductor layer disposed on the substrate, including source, drain, and channel regions, a crystallization-inducing metal, first gettering sites disposed on opposing edges of the semiconductor layer, and a second gettering site spaced apart from the first gettering sites; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer disposed on the gate electrode; and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to the source and drain regions of the semiconductor layer.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 14, 2010
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jin-Wook Seo, Tae-Hoon Yang, Kil-Won Lee
  • Patent number: 7592628
    Abstract: A system for displaying images comprises a thin film transistor (TFT) device comprising first and second active layers disposed on a substrate in the driving circuit region and in the pixel region, respectively. Each active layer comprises a channel region, a source/drain region and a lightly doped region formed therebetween. Two gate structures are disposed on the first and second active layers, respectively. Each gate structure comprises a stacked first and second gate dielectric layers and a gate layer, and the second gate dielectric layer has a length shorter than that of the first gate dielectric layer but longer than the gate length of the gate layer. The lightly doped region of the first active layer has a length different from that of the second active layer.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: September 22, 2009
    Assignee: TPO Displays Corp.
    Inventors: Yoshihiro Morimoto, Ryan Lee
  • Patent number: 7573067
    Abstract: It is an object of the present invention to provide a semiconductor display device using a protective circuit in which dielectric breakdown is prevented more effectively. In the invention, in the cases that a first interlayer insulating film is formed covering a TFT used for a protective circuit and a second interlayer insulating film, which is an insulating coating film, is formed covering a wiring formed over the first interlayer insulating film, a wiring for connecting the TFT to other semiconductor elements is formed so as to be in contact with the surface of the second interlayer insulating film so as to secure a path discharging charge accumulated in the surface of the second interlayer insulating film. Note that the TFT used for the protective diode is a so-called diode-connected TFT in which either of the first terminal or the second terminal is connected to a gate electrode.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: August 11, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7563658
    Abstract: The present invention relates to a method for manufacturing a semiconductor film, including the steps of forming a transparent conductive film, forming a first conductive film over the transparent conductive film, forming a second conductive film over the first conductive film, etching the second conductive film with a gas including chlorine, and etching the first conductive film with a gas including fluorine. During etching of the second conductive film with a gas including chlorine, the transparent conductive film is protected by the first conductive film. During etching of the first conductive film with the gas including fluorine, the transparent conductive film does not react with the gas including fluorine. Therefore, no particle is formed.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: July 21, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Satoru Okamoto, Shigeharu Monoe, Shunpei Yamazaki
  • Patent number: 7535024
    Abstract: The present invention provides a fabrication method of a display device which aims at the reduction of fabricating man-hours.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: May 19, 2009
    Assignee: Hitachi Displays, Ltd.
    Inventors: Eiji Oue, Toshihiko Itoga, Toshiki Kaneko, Daisuke Sonoda, Takeshi Kuriyagawa
  • Patent number: 7491562
    Abstract: In a light emitting device, it is preferable that a surface of a film below a light-emitting element has flatness. Therefore, treatment such as planarization of a surface of a film is performed after forming the film. The present invention proposes a structure of a light-emitting device that can make the foregoing planarization easier. The same layer as a wiring formed on a first film is used to manufacture a second film. Herewith, a portion of the first film below a light-emitting element can be prevented from being etched to form unevenness at a surface of the first film during the formation of the wiring. In addition, a surface of a third film is made higher by providing the second film to enable local planarization.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: February 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Noriko Miyagi
  • Publication number: 20080206938
    Abstract: A display comprises a substrate, a polysilicon layer which is crystallized by a solid phase crystallization (SPC) method, a gate dielectric layer made of silicon oxy-nitride (SiON) and formed on the polysilicon layer, and a gate electrode formed on the gate dielectric layer (i.e. SiON).
    Type: Application
    Filed: April 11, 2008
    Publication date: August 28, 2008
    Applicant: AU OPTRONICS CORP.
    Inventor: Chia-Tien Peng
  • Publication number: 20080185667
    Abstract: An Mo film (6) is formed on a SiO2 film (5) by particularly using the film thickness and the deposition temperature (ambient temperature in a sputtering chamber) as the primary parameters and adjusting the film thickness to be within the range from 100 nm to 500 nm (more preferably 100 nm to 300 nm) and the deposition temperature to be within the range from 25° C. to 300° C., so as to control residual stress to have a predetermined value of 300 MPa or greater and to be oriented to increase the in-plane lattice constant. There can be thus provided a reliable CMOSTFT in which desired strain is easily and reliably imparted to polysilicon thin films (4a and 4b) to improve the mobility therein without adding an extra step of imparting the strain to the silicon thin film.
    Type: Application
    Filed: September 17, 2004
    Publication date: August 7, 2008
    Inventors: Kenichi Yoshino, Akito Hara, Michiko Takei, Takuya Hirano
  • Publication number: 20080116460
    Abstract: A non-volatile memory device is capable of reducing an excessive leakage current due to a rough surface of a polysilicon and realizing improved blocking function with an oxide film that is thinner by forming a first oxide film and a second oxide film including a silicon oxy-nitride (SiOxNy) layer using nitrous oxide (N2O) plasma. A fabricating method and a memory apparatus of the non-volatile memory device are also discussed.
    Type: Application
    Filed: July 13, 2007
    Publication date: May 22, 2008
    Applicant: Samsung SDI Co., Ltd.
    Inventor: Byoung Deog CHOI
  • Publication number: 20080079004
    Abstract: A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide layer is formed on the silicon epitaxial layer, and a gate electrode is formed on the gate oxide layer. A field insulator is formed on exposed areas of the buried oxide layer to thereby separate adjacent silicon epitaxial layers. Side surfaces of the silicon epitaxial layer are flattened through heat treatment. The fabrication method for a FinFET device includes forming the gate oxidation layer and the gate electrode on the SOI substrate; forming the mask pattern on the gate electrode; forming the trench by etching using the mask pattern as a mask; performing heat treatment to flatten the side surfaces of the silicon epitaxial layer; and forming the field insulator in the trench.
    Type: Application
    Filed: November 5, 2007
    Publication date: April 3, 2008
    Applicant: Dongbu Electronics Co., Ltd.
    Inventor: Jea-Hee Kim
  • Patent number: 7291523
    Abstract: After crystallization of a semiconductor film is performed by irradiating first laser light (energy density of 400 to 500 mJ/cm2) in an atmosphere containing oxygen, an oxide film formed by irradiating the first laser light is removed. It is next performed to irradiate second laser light under an atmosphere that does not contain oxygen (at a higher energy density than that of the first laser light irradiation), thus to increase the flatness of the semiconductor film.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: November 6, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Hidekazu Miyairi
  • Publication number: 20070200139
    Abstract: A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.
    Type: Application
    Filed: April 27, 2007
    Publication date: August 30, 2007
    Inventors: Hiroshi Shibata, Shinji Maekawa
  • Patent number: 7129522
    Abstract: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010 positioned above a heat absorbing layer 1011 and a semiconductor film 1013 of the other region to produce a difference in thermal expansion at the boundary of the outside end 1015 of the heat absorbing layer. This difference produces a strain to form a surface wave. The surface wave starting at the outer periphery of the heat absorbing layer is formed in the vicinity of the heat absorbing layer. When the semiconductor layer is solidified after it is melted, the protrusions of the surface wave remain as protrusions after the semiconductor film is solidified.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: October 31, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Setsuo Nakajima, Ritsuko Kawasaki