Abstract: A method for nanoparticle fabrication deposits a seed layer of a transparent conductive oxide onto a substrate and deposits a layer of a plasmonic metal onto the transparent conductive oxide layer. The method forms nanoparticles from the deposited metal by transporting the substrate along a transport path and, as the substrate is moving, energizing one or more flash lamps disposed along the transport path to apply a plurality of light pulses that impart a dewetting energy to the deposited metal layer.

Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.

Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

Abstract: Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.

Abstract: A method of producing a glass substrate having a hole is provided. The method includes preparing the glass substrate having a first surface and a second surface facing each other; forming a hole in the glass substrate with a laser; and annealing the glass substrate placed on a first support substrate having a thermal expansion coefficient whose difference from a thermal expansion coefficient of the glass substrate is less than or equal to 1 ppm/K, where the first support substrate is placed on a second support substrate having a thermal expansion coefficient of less than or equal to 10 ppm/K.

Abstract: A light-emitting element display device includes: a display area which has an organic insulating layer that is made of an organic insulating material; a peripheral circuit area which is disposed around the display area and which has the organic insulating layer; and a blocking area that is formed between the display area and the peripheral circuit area. The blocking area includes: a first blocking area configured by only one or a plurality of inorganic material layers between an insulating base substrate and an electrode layer which covers the display area and is formed continuously from the display area, and which configures one of two electrodes for allowing the light emitting area to emit the light; and a second blocking area including a plurality of layers configuring the first blocking area, and a light emitting organic layer.

Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.

Abstract: A thin film transistor (TFT) is provided, which includes a gate, a semiconductor layer, an insulation layer, a source and a drain. The semiconductor layer has a first end and a second end opposite to the first end. The insulation layer is disposed between the gate and the semiconductor layer. The source clamps the first end of the semiconductor layer and the drain clamps the second end of the semiconductor layer.

Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.

Abstract: It is an object to provide an electrophoretic display device having a thin film transistor which has highly reliable electric characteristics, lightweight, and flexibility. A gate insulating film is formed over a gate electrode, a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film, a buffer layer is formed over the microcrystalline semiconductor film, a pair of source and drain regions are formed over the buffer layer, a pair of the source and drain electrodes in contact with the source and drain regions are formed. Then, the inverted-staggered thin film transistor is interposed between the flexible substrates, and the thin film transistor is provided with electrophoretic display element which is electrically connected by the pixel electrode. Then, the electrophoretic display electrode is surrounded by the partition layer so as to cover the end portion of the pixel electrode and provided over the pixel electrode.

Abstract: A thin-film semiconductor device includes: a gate electrode; a channel layer; a first amorphous semiconductor layer; a channel protective layer; a pair of second amorphous semiconductor layers formed on side surfaces of the channel layer; and a pair of contact layers which contacts the side surfaces of the channel layer via the second amorphous semiconductor layers. The gate electrode, the channel layer, the first amorphous semiconductor layer, and the channel protective layer are stacked so as to have outlines that coincide with one another in a top view. The first amorphous semiconductor layer has a density of localized states higher than those of the second amorphous semiconductor layers. The second amorphous semiconductor layers have band gaps larger than that of the first amorphous semiconductor layer.

Abstract: To reduce parasitic capacitance between a gate electrode and a source electrode or drain electrode of a dual-gate transistor. A semiconductor device includes a first insulating layer covering a first conductive layer; a first semiconductor layer, second semiconductor layers, and an impurity semiconductor layer sequentially provided over the first insulating layer; a second conductive layer over and at least partially in contact with the impurity semiconductor layer; a second insulating layer over the second conductive layer; a third insulating layer covering the three semiconductor layers, the second conductive layer, and the second insulating layer; and a third conductive layer over the third insulating layer. The third conductive layer overlaps with a portion of the first semiconductor layer, which does not overlap with the second semiconductor layers, and further overlaps with part of the second conductive layer.

Abstract: A thin film transistor (TFT) and a flat panel display device including the same. The TFT includes a substrate, a gate electrode formed over the substrate, the gate electrode formed with silicon doped with impurities, a gate wiring connected to the gate electrode, an active layer formed over the gate electrode, and source and drain electrodes connected to the active layer. According to such a structure, since heat flow to the gate electrode during crystallization of the active layer may be prevented, stable crystallization of the active layer may be performed, and thus an error rate of a product may be decreased.

Abstract: A method and system for setting the direction of pinned layers in a magnetic junction are described. In one aspect, a magnetic field greater than the coercivity of the layers in a pinned layer but less than the coupling field between the layers is applied. In another aspect the pinned layers are switched from an anti-dual state to a dual state using a spin transfer torque current. In another aspect, a magnetic junction having a partial perpendicular anisotropy (PPMA) layer in the pinned layer is provided. In some aspects, the PPMA layer is part of a synthetic antiferromagnetic structure. In some embodiments, a decoupling layer is provided between the PPMA layer and another ferromagnetic layer in the pinned layer.

Abstract: A semiconductor device of the present invention includes: a lower electrode (110); a contact layer (130) including a first contact layer (132), a second contact layer (134) and a third contact layer (136) overlapping with a semiconductor layer (120); and an upper electrode (140) including a first upper electrode (142), a second upper electrode (144) and a third upper electrode (146). The second contact layer (134) includes a first region (134a), and a second region (134b) separate from the first region (134a), and the second upper electrode (144) is directly in contact with the semiconductor layer (120) in a region between the first region (134a) and the second region (134b) of the second contact layer (134).

Abstract: Disclosed is a method of forming array substrates having a peripheral wiring area and a display area. The method is processed by only three lithography processes with two multi-tone photomasks and one general photomask. In the peripheral wiring area, the top conductive line directly contacts the bottom conductive line without any other conductive layer. The conventional lift-off process is eliminated, thereby preventing a material (not dissolved by a stripper) from suspending in the stripper or remaining on the array substrate surface.

Abstract: Disclosed is a transistor structure including: a first thin film transistor including, a first gate electrode; a first insulating film which covers the first gate electrode; and a first semiconductor film formed on the first insulating film in a position corresponding to the first gate electrode; and a second thin film transistor including, a second semiconductor film formed on the first insulating film; a second insulating film which covers the second semiconductor film; and a second gate electrode formed in a position corresponding to a channel portion of the second semiconductor film on the second insulating film, wherein the first semiconductor film and the second semiconductor film include a first portion on the first insulating film side and a second portion on the opposite surface side, and one of the first portion or the second portion has a higher degree of crystallization of silicon compared to the other.

Abstract: A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.

Abstract: Provided are thin film transistor, a method of fabricating the same, a flat panel display device including the same, and a method of fabricating the flat panel display device, that are capable of applying an electric field to a gate line to form a channel region of a semiconductor layer of a thin film transistor using a polysilicon layer crystallized by a high temperature heat generated by Joule heating of a conductive layer. As a result, a process can be simplified using a gate line included in the thin film transistor as the conductive layer, and the channel region of the semiconductor layer can be formed of polysilicon having a uniform degree of crystallinity. The thin film transistor includes a straight gate line disposed in one direction, a semiconductor layer crossing the gate line, and source and drain electrodes connected to source and drain regions of the semiconductor layer.

Abstract: A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Abstract: The invention relates to an electronic device including a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT including a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.

Abstract: A display device including an inverter circuit and a switch is provided. The inverter circuit includes a first thin film transistor and a second thin film transistor which have the same conductivity type. The first thin film transistor and the second thin film transistor each include: a gate insulating layer in contact with a gate electrode; a microcrystalline semiconductor layer in contact with the gate insulating layer; a mixed layer in contact with the microcrystalline semiconductor layer; a layer which includes an amorphous semiconductor and is in contact with the mixed layer; and a wiring. A conical or pyramidal microcrystalline semiconductor region and an amorphous semiconductor region filling a space except the conical or pyramidal microcrystalline semiconductor region are included in the mixed layer.

Abstract: A thin film transistor (TFT) substrate and a manufacturing method thereof are disclosed. The manufacturing method comprises: after a first metallic layer is formed on the TFT substrate, annealing the TFT substrate so that lattices of the first metallic layer are re-arranged to prevent occurrences of grain boundary defects in the first metallic layer. According to the present disclosure, after the first metallic layer is formed on the TFT substrate, the TFT substrate is annealed in sequence to re-arrange lattices of the first metallic layer. This effectively prevents occurrences of grain boundary defects and, consequently, metal protrusions in the first metallic layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.

Abstract: A semiconductor apparatus having a substrate and a laminate structure formed on the substrate, the laminate structure including an insulating film made of a metal oxide and a semiconductor thin film, both the insulating film and the semiconductor thin film being crystallized.

Abstract: A thin film transistor includes a substrate; a gate electrode on the substrate; a gate insulating layer covering the gate electrode; a semiconductor layer corresponding to the gate electrode on the gate insulating layer; a protective layer covering the semiconductor layer and the gate insulating layer and having a source contact hole and a drain contact hole exposing a portion of the semiconductor layer; and a source electrode and a drain electrode on the protective layer and coupled to the semiconductor layer through the source contact hole and the drain contact hole, respectively, wherein the semiconductor layer has a source offset groove at a portion corresponding to the source contact hole of the protective layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

Abstract: A method for forming a conductor structure is provided. The method comprises: (1) providing a substrate; (2) forming a patterned dielectric layer with a first opening which exposes a portion of the substrate; forming a patterned organic material layer on the dielectric layer with a second opening which corresponds to the first opening and expose the exposed portion of the substrate; (3) forming a first barrier layer on the organic material layer and the exposed portion of the substrate; (4) forming a metal layer on the first barrier layer; and (5) removing the organic material layer, the first barrier layer thereon and the metal layer thereon.

Abstract: Provided is an image display device including thin film transistors on a substrate, including: gate lines and drain lines intersecting the gate lines, each thin film transistor having, in a channel region, a laminate structure in which a gate electrode, a gate insulating film, and a semiconductor layer are laminated in the stated order from the substrate side; and a pair of removal regions in which parts of the gate insulating film are removed, which are formed on both sides of the gate electrode and formed in a channel width direction of the channel region, in which when W represents a width of the gate electrode in the channel width direction of the channel region, and R represents a width of the gate insulating film in the channel width direction, which is sandwiched between the pair of removal regions, R?W is satisfied.

Abstract: In a thin film transistor substrate, an active pattern of a thin film transistor includes a lower semiconductor pattern and an upper semiconductor pattern that are patterned through different process steps. The lower semiconductor pattern defines a channel area of the thin film transistor, and the upper semiconductor pattern is connected to a side portion of the lower semiconductor pattern and makes contact with the source electrode and the drain electrode. An etch stop layer is formed on the lower semiconductor pattern corresponding to the channel area, and the etch stop layer is formed through the same patterning process as the lower semiconductor pattern. Also, an ohmic contact pattern is formed on the upper semiconductor pattern, and the ohmic contact pattern is formed by the same patterning process as the upper semiconductor pattern.

Abstract: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.

Abstract: A thin film transistor and a press sensing device using the thin film transistor are disclosed. The thin film transistor, comprises a source electrode; a drain electrode spaced from the source electrode; a semiconductor layer electrically connected with the source electrode and the drain electrode, a channel defined in the semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode electrically insulated from the semiconductor layer; and an insulative layer configured for insulating the source electrode, the drain electrode, and the semiconductor layer from each other, wherein the insulative layer is made of a polymeric material with an elastic modulus ranged from about 0.1 megapascal (MPa) to about 10 MPa.

Abstract: A semiconductor device including: a first electric conductor of a lower layer side and a second electric conductor of an upper layer side; a thick film insulating layer provided between the first electric conductor and the second electric conductor; and a contact portion formed so as to imitate an inner surface shape of a through hole with respect to the insulating layer and electrically connecting the first electric conductor and the second electric conductor, in which a tapered angle of the through hole is an acute angle.

Abstract: A display device includes: a conductive layer on which gate electrodes are formed; a first insulation layer which is formed on the conductive layer; a semiconductor layer which is formed on the first insulation layer and is provided for forming semiconductor films which contain poly-crystalline silicon above the gate electrodes; and a second insulation layer which is formed on the semiconductor layer. Here, the semiconductor film includes a channel region which overlaps with the gate electrode as viewed in a plan view. In the channel region, a portion of the semiconductor film which is in contact with the second insulation layer exhibits higher impurity concentration than a portion of the semiconductor film which is in contact with the first insulation layer.

Abstract: Provided is a display device including a thin-film transistor and a capacitor element, the thin-film transistor includes: a first insulating film (IN1) which is formed to cover an area where a gate electrode (GT) is formed; a second insulating film (IN2) which is formed on the first insulating film, the second insulating film having an opening (OP) formed in the area in plan view; a semiconductor layer (SCLt) which is formed on the second insulating film to cross the opening, the semiconductor layer including high concentration areas (CN); a third insulating film (IN3) which is formed on the semiconductor layer to expose apart of each of the high concentration areas; and a pair of electrodes (DT, ST) each having electrical connection to the part; and the capacitor element includes a dielectric film which is formed of the same layer and the same material as the third insulating film.

Abstract: A gate driver on array of a display includes a substrate having a peripheral region, and a gate driver on array structure formed in the peripheral region. The gate driver on array structure includes a pull-down transistor, and the pull-down transistor has a gate electrode, an insulating layer, a semiconductor island, a source electrode, and a drain electrode. The semiconductor island extends out of both edges of the gate electrode, and extends out of an edge of the source electrode and an edge of the drain electrode.

Abstract: A metallic wiring film, which is not exfoliated even when exposed to plasma of hydrogen, is provided. A metallic wiring film is constituted by an adhesion layer in which Al is added to copper and a metallic low-resistance layer which is disposed on the adhesion layer and made of pure copper. When a copper alloy including Al and oxygen are included in the adhesion layer and a source electrode and a drain electrode are formed from it, copper does not precipitate at an interface between the adhesion layer and the silicon layer even when being exposed to the hydrogen plasma, which prevents the occurrence of exfoliation between the adhesion layer and the silicon layer. If the amount of Al increases, since widths of the adhesion layer and the metallic low-resistance layer largely differ after etching, the maximum addition amount for permitting the etching to be performed is the upper limit.

Abstract: In a method of manufacturing a thin film transistor substrate, a semiconductor pattern is formed on a substrate, a first etch stop layer and a second etch stop layer are sequentially formed on the semiconductor pattern, and the second etch stop layer and the first etch stop layer are sequentially patterned to form a second etch stop pattern and a first etch stop pattern. Thus, when the second etch stop layer is patterned using an etchant, the first etch stop layer covers the semiconductor pattern, thereby preventing the semiconductor pattern from being etched by the etchant.

Abstract: A microcrystalline semiconductor film with high crystallinity is manufactured. In addition, a thin film transistor with excellent electric characteristics and high reliability, and a display device including the thin film transistor are manufactured with high productivity. A deposition gas containing silicon or germanium is introduced from an electrode including a plurality of projecting portions provided in a treatment chamber of a plasma CVD apparatus, glow discharge is caused by supplying high-frequency power, and thereby crystal particles are formed over a substrate, and a microcrystalline semiconductor film is formed over the crystal particles by a plasma CVD method.

Abstract: The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor that includes a zinc oxide material including Si as a channel material of a semiconductor layer, and a method of manufacturing the same.

Abstract: In a bottom-gate-type thin film transistor used in a liquid crystal display device in which a poly-Si layer and an a-Si layer are stacked, a quantity of an ON current which flows in the thin film transistor can be increased. A poly-Si layer and an a-Si layer are stacked on a gate electrode as an active layer by way of a gate insulation film therebetween in order of the poly-Si layer and the a-Si layer. An n+Si layer and a source/drain layer are formed on the a-Si layer thus forming a thin film transistor. A forward current which flows in the thin film transistor mainly flows in the poly-Si layer.

Abstract: A manufacturing method of a semiconductor memory device includes forming a first gate electrode having a charge storage layer, a block layer, and a control gate electrode on a first region of a semiconductor substrate, forming a second gate electrode on a second region of the semiconductor substrate, forming a protective insulating film on a side surface of the block layer, exposing the first region while covering the second region on the semiconductor substrate with a photoresist, using the photoresist, the first gate electrode, and the protective insulating film as masks to implant an impurity into the first region of the semiconductor substrate, and removing the photoresist by wet etching which uses a mixed solution containing H2SO4 and H2O2. The protective insulating film having an etching selective ratio of 1:100 or above with respect to the photoresist under wet etching conditions using the mixed solution.

Abstract: Disclosed are a flexible semiconductor device and manufacturing method therefor whereby the capacitances of capacitor parts of semiconductor elements and the like can be increased while decreasing parasitic capacitances that arise between multilevel interconnections. The disclosed flexible semiconductor device is provided with an insulating film on which a semiconductor element is formed. The top and bottom surfaces of the insulating film have a top wiring pattern layer and a bottom wiring pattern layer, respectively. The semiconductor element comprises: a semiconductor layer formed on the top surface of the insulating film; a source electrode and a drain electrode formed on the top surface of the insulating film so as to contact the semiconductor layer; and a gate electrode formed on the bottom surface of the insulating film so as to be opposite the semiconductor layer.

Abstract: A semiconductor apparatus having a substrate and a laminate structure formed on the substrate, the laminate structure including an insulating film made of a metal oxide and a semiconductor thin film, both the insulating film and the semiconductor thin film being crystallized.

Abstract: A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer.

Abstract: An array substrate for a display device includes a gate electrode on a substrate; a gate insulating layer on the gate electrode and having the same plane area and the same plane shape as the gate electrode; an active layer on the gate insulating layer and exposing an edge of the gate insulating layer; an interlayer insulating layer on the active layer and including first and second active contact holes, the first and second active contact holes respectively exposing both sides of the active layers; first and second ohmic contact layers contacting the active layer through the first and second active contact holes, respectively; a source electrode on the first ohmic contact layer; a drain electrode on the second ohmic contact layer; a data line on the interlayer insulating layer and connected to the source electrode; a first passivation layer on the source electrode, the drain electrode and the data line, the first passivation layer, the interlayer insulating layer and the gate insulating layer have a first gat

Abstract: An object of the present invention is to provide a thin film transistor having a gate insulating film for suppressing a shift amount of a threshold voltage generated by use under a high temperature environment. In a thin film transistor having a channel layer made of microcrystalline silicon, a gate insulating film 140 is a film obtained by laminating a first silicon nitride film 141 having a nitrogen concentration of 6×1021 atoms/cc or less and a second silicon nitride film 142 having a nitrogen concentration higher than 6×1021 atoms/cc. Therefore, the second silicon nitride film 142 increases the blocking effect against mobile ions entering from a glass substrate 20 to make the mobile ions less likely to be stored in an interface with a channel layer 50. The first silicon nitride film 141 increases the dielectric breakdown voltage of the gate insulating film 140.

Abstract: Provided is a polysilicon thin film transistor having a bottom gate structure using copper and a method of making the same. The polysilicon thin film transistor includes: a transparent insulation substrate; a seed layer that is formed in the same pattern as that of a gate electrode on the transparent insulation substrate, and that is used to form the gate electrode; the gate electrode that is formed of copper on the seed layer; a planarization layer that is formed on the transparent insulation substrate in the same level as that of the gate electrode in the vicinity of the gate electrode; a gate insulation film formed on the upper portion of the gate electrode and the planarization layer, respectively; and a polysilicon layer in which a channel region, a source region and a drain region are formed on the upper portion of the gate insulation film.

Abstract: A thin film transistor display substrate and a method of manufacturing the same are provided. The thin film transistor substrate includes a gate electrode formed on a display substrate, an active layer formed on the gate electrode to overlap with the gate electrode and including polycrystalline silicon, a first ohmic contact layer formed on the active layer, a second ohmic contact layer formed on the first ohmic contact layer, and a source electrode and a drain electrode each formed on the second ohmic contact layer.

Abstract: An object of the present invention is to provide a technology of reducing a nickel element in the silicon film which is crystallized by using nickel. An extremely small amount of nickel is introduced into an amorphous silicon film which is formed on the glass substrate. Then this amorphous silicon film is crystallized by heating. At this time, the nickel element remains in the crystallized silicon film. Then an amorphous silicon film is formed on the surface of the silicon film crystallized with the action of nickel. Then the amorphous silicon film is further heat treated. By carrying out this heat treatment, the nickel element is dispersed from the crystallized silicon film into the amorphous silicon film with the result that the nickel density in the crystallized silicon film is lowered.