Abstract: Inorganic solar cells having a nano-patterned p-n or p-i-n junction to reduce electron and hole travel distance to the separation interface to be less than the magnitude of the drift length or diffusion length, and meanwhile to maintain adequate active material to absorb photons. Formation of the inorganic solar cells may include one or more nano-lithography steps.

Abstract: Objects are to reduce damage to a semiconductor integrated circuit by external stress and to increase the manufacturing yield of a thinned semiconductor integrated circuit. A single crystal semiconductor layer separated from a single crystal semiconductor substrate is used for a semiconductor element included in the semiconductor integrated circuit. Moreover, a substrate which is formed into a thin shape and provided with the semiconductor integrated circuit is covered with a resin layer. In a separation step, a groove for separating a semiconductor element layer is formed in the supporting substrate, and a resin layer is provided over the supporting substrate in which the groove is formed. After that, the resin layer and the supporting substrate are cut in the groove so as to be divided into a plurality of semiconductor integrated circuits.

Abstract: A photodetector array comprises a plurality of photodetectors formed by a high resistivity low doping concentration first semiconductor substrate and a low resistivity high doping concentration second semiconductor substrate. The first and second semiconductor substrates are directly bonded together with a silicon-to-silicon atomic bond at a bond interface, thereby providing a sharp transition from the first substrate to the second substrate. A method of making the photodetector array is also provided.

Abstract: Provided is a superstrate type a-Si:H thin film solar cell of which the device characteristics are improved as compared with conventional ones. The solar cell device is manufactured by a process comprising depositing phosphorus on a transparent conductive film formed on a transparent substrate and sequentially forming a p-type layer, an i-type layer, and an n-type layer which are formed of a-Si:H on the transparent conductive film by a plasma CVD method. The phosphorus is deposited, for example, by plasmatization of phosphorus-containing gas. Alternatively, the phosphorus is deposited by etching a phosphorus source provided in a margin region where a plasma excitation voltage is applied but no transparent substrate is placed, with hydrogen plasma at the start of the formation of the p-type layer by the plasma CVD method.

Abstract: According to an exemplary aspect of the present invention, at least a semiconductor mesa and a semiconductor layer covering at least the side wall of the mesa and a semiconductor mesa are formed on an n-type semiconductor substrate. The semiconductor mesa includes at least a light absorption layer and a p-type contact layer. The principal surface of the semiconductor substrate tilts at an angle ? to the (100) plane. The angle ? is 0.1 degree?|?|?10 degrees.

Abstract: A solar cell includes a first electrode disposed on a substrate, a first light absorption layer disposed on the first electrode, an interlayer disposed on the first light absorption layer, a second light absorption layer disposed on the interlayer, and a second electrode disposed on the second light absorption layer. The solar cell further includes a groove penetrating through the first light absorption layer, the interlayer, and the second light absorption layer. The groove is filled with the second electrode. The interlayer is spaced apart from the second electrode filling the groove, to define a spacer layer which electrically insulates the interlayer from the second electrode filling the groove.

Abstract: The lattice mismatching between a Ge layer and a Si layer is as large as about 4%. Thus, when the Ge layer is grown on the Si layer, penetration dislocation is introduced to cause leakage current at the p-i-n junction. Thereby, the photo-detection sensitivity is reduced, and the reliability of the element is also lowered. Further, in the connection with a Si waveguide, there are also problems of the reflection loss due to the difference in refractive index between Si and Ge, and of the absorption loss caused by a metal electrode.

Abstract: A stack including a first electrode, a first impurity semiconductor layer having one conductivity type, an intrinsic semiconductor layer, a second impurity semiconductor layer having an opposite conductivity type to the one conductivity type, and a light-transmitting second electrode is formed over an insulator. The light-transmitting second electrode and the second impurity semiconductor layer have one or more openings. The shortest distance between one portion of the wall of one opening and an opposite portion of the wall of the same opening at the level of the interface between the second impurity semiconductor layer and the intrinsic semiconductor layer is made smaller than the diffusion length of holes in the intrinsic semiconductor layer. Thus, recombination is suppressed, so that more photocarriers are generated due to the openings and taken out as current, whereby conversion efficiency is increased.

Abstract: A color unit is disclosed in which is included in an imaging device. The color unit includes; a first p-type electrode layer disposed on a light receiving side of the color unit, and including a light-absorptive organic material which selectively absorbs a wavelength other than a desired wavelength in a visible light band of the electromagnetic spectrum, a second p-type electrode layer disposed under the first p-type electrode layer and including a light-absorptive organic material which absorbs a desired wavelength and an n-type electrode layer disposed under the second p-type electrode layer and including an organic material, wherein photoelectric conversion is performed through a p-n junction between the second p-type electrode layer and the n-type electrode layer and light of the desired wavelength is converted into electrical current.

Abstract: It is possible to reduce the contact resistance so as to improve the conversion efficiency of a photoelectric conversion element structure. Provided is a photoelectric conversion element structure of the pin structure which selects an upper limit energy level of the valence band of the p-type semiconductor or the electron affinity of the n-type semiconductor layer and the work function of a metal layer which is brought into contact with the semiconductor, so as to reduce the contact resistance as compared to the case when Al or Ag is used as an electrode. The selected metal layer may be arranged between the electrode formed from Al or Ag and the semiconductor or may be substituted for the n- or p-type semiconductor.

Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Abstract: In a manufacturing method of a thin film solar cell in which a p-type layer, an i-type layer, and an n-type layer are layered, the i-type layer is an amorphous silicon layer, the n-type layer is a microcrystalline silicon layer, and in a process of forming the n-type layer, a doping concentration of an n-type dopant is increased as a distance from the i-type layer is increased.

Abstract: Sidewall photodetectors for integrated photonic devices and their method of manufacture. An embodiment includes a p-i-n film stack formed on a sidewall of a substrate semiconductor feature having sufficiently large area to accommodate the spot size of a multi-mode fiber. An embodiment includes a first sidewall photodetector coupled to a second sidewall photodetector by a waveguide, the first sidewall photodetector having an i-layer tuned to absorb a first wavelength of light incident to the first sidewall and pass a second wavelength of light to the second sidewall photodetector having an i-layer tuned to absorb the second wavelength.

Abstract: A photo-detector comprising: a p-doped semiconductor layer; an n-doped semiconductor layer juxtaposed with the p-doped semiconductor layer; one of an intrinsic amorphous silicon layer sandwiched between the p-doped semiconductor layer and the n-doped semiconductor layer and a depletion region formed between the p-doped semiconductor layer juxtaposed with the n-doped semiconductor layer; a plurality of mesoscopic sized particles within the one of the intrinsic amorphous silicon layer sandwiched between the p-doped semiconductor layer and the n-doped semiconductor layer and the depletion region formed between the p-doped semiconductor layer juxtaposed with the n-doped semiconductor layer. A source of pumping light is provided and arranged to be received at the mesoscopic sized particles thereby generating free carriers confined in the mesoscopic sized particles. Received light of a target waveband releases the carriers from confinement which is detected as a flow of current.

Abstract: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection.

Abstract: A method of manufacturing a photovoltaic module is provided. The method includes providing an electrically insulating substrate and a lower electrode, depositing a lower stack of silicon layers above the lower electrode, and depositing an upper stack of silicon layers above the lower stack. The lower and upper stacks include N-I-P junctions. The lower stack has an energy band gap of at least 1.60 eV while the upper stack has an energy band gap of at least 1.80 eV. The method also includes providing an upper electrode above the upper stack. The lower and upper stacks convert incident light into an electric potential between the upper and lower electrodes with the lower and upper stacks converting different portions of the light into the electric potential based on wavelengths of the light.

Abstract: A light sensing system comprises a first light sensor (21?), a second light sensor (21) and a first light shielding material (24) disposed over the first light sensor (21?) but not over the second light sensor (21) so as to block ambient light from being incident on the first light sensor (21). A first electrically conductive material (23a) is disposed between the first light shielding layer (24) and the first light sensor and a second electrically conductive material (23b) is disposed over the second light sensor. The second electrically conductive material (23b) is at least partially light-transmissive. Providing the first electrically conductive material (23a) between the first light shielding layer (24) and the first light sensor eliminates any parasitic capacitance that would otherwise be set up by the light shielding layer (24) (which is typically a metallic layer).

Abstract: Flexible lateral p-i-n (“PIN”) diodes, arrays of flexible PIN diodes and imaging devices incorporating arrays of PIN diodes are provided. The flexible lateral PIN diodes are fabricated from thin, flexible layers of single-crystalline semiconductor. A plurality of the PIN diodes can be patterned into a single semiconductor layer to provide a flexible photodetector array that can be formed into a three-dimensional imaging device.

Abstract: A photodetector with an improved electrostatic discharge damage threshold is disclosed, suitable for applications in telecommunication systems operating at elevated data rates. The photodetector may be a PIN or an APD fabricated in the InP compound semiconductor system. The increased ESD damage threshold is achieved by reducing the ESD induced current density in the photodetector by a suitable widening of the contact at a critical location, increasing the series resistance and promoting lateral current spreading by means of a current spreading layer.

Abstract: A light-absorbing layer is composed of a compound-semiconductor film of charcopyrite structure, a surface layer is disposed on the light-absorbing layer, the surface layer having a higher band gap energy than the compound-semiconductor film, an upper electrode layer is disposed on the surface layer, and a lower electrode layer is disposed on a backside of the light-absorbing layer in opposition to the upper electrode layer, the upper electrode layer and the lower electrode layer having a reverse bias voltage applied in between to detect electric charges produced by photoelectric conversion in the compound-semiconductor film, as electric charges due to photoelectric conversion are multiplied by impact ionization, while the multiplication by impact ionization of electric charges is induced by application of a high-intensity electric field to a semiconductor of charcopyrite structure, allowing for an improved dark-current property, and an enhanced efficiency even in detection of low illumination intensities, wit

Abstract: A solar cell device is provided, including a transparent substrate, a composite transparent conductive layer disposed over the transparent substrate, a photovoltaic element formed over the composite transparent conductive layer, and an electrode layer disposed over the photovoltaic element. In one embodiment, the composite transparent conductive layer includes a first transparent conductive layer and a second transparent conductive layer sequentially stacked over the transparent substrate, and the first transparent conductive layer is made of lithium and fluorine-codoped tin oxide and the second transparent conductive layer is made of a material selected from a group consisting of zinc oxide and titanium dioxide.

Abstract: Among photodiodes used in an optical system for applying light to the entire chip, the conventional PIN photodiode has a problem that light should be applied only to a light reception surface in order to prevent degradation of light response and that positioning of the optical system is difficult. Moreover, in the mesa type PIN photodiode not requiring positioning of an optical system, disconnection failure is often caused by the mesa step. The present invention is made to solve the aforementioned problems, and its object is to provide a PIN photodiode having an improved light response and causing less disconnection failure of metal wiring and a light reception device using the PIN photodiode. The PIN photodiode of the present invention has a structure that the light reception surface is surrounded by a groove of a predetermined depth.

Abstract: The invention relates to an avalanche photodiode having enhanced gain uniformity enabled by a tailored diffused p-n junction profile. The tailoring is achieved by a two stage doping process incorporating a solid source diffusion in combination with conventional gas source diffusion. The solid source diffusion material is selected for its solubility to the dopant compared to the solubility of the multiplication layer to dopant. The solid source has a diameter between the first and second diffusion windows. Thus, there are three distinct diffusion regions during the second diffusion. The dopant in the multiplication layer at the edge region, the dopant from the solid source material with a relatively higher dopant concentration (limited by the solubility of the dopant in the solid source material) at the intermediate region, and the central region exposed to an infinite diffusion source from the solid source material as it is continually charged with new dopant from the external gas source.

Abstract: The present invention changes layer polarities of an epitaxy structure of an avalanche photodiode into n-i-n-i-p. A transport layer is deposed above an absorption layer to prevent absorbing photon and producing electrons and holes. A major part of electric field is concentrated on a multiplication layer for producing avalanche and a minor part of the electric field is left on the absorption layer for transferring carrier without avalanche. Thus, bandwidth limit from a conflict between RC bandwidth and carrier transferring time is relieved. Meanwhile, active area is enlarged and alignment error is improved without sacrificing component velocity too much.

Abstract: A photo detector has a sensing TFT (thin film transistor) and a photodiode. The sensing TFT has a gate and a base. The photodiode has an intrinsic semiconductor region electrically connected to the gate and the base of the sensing TFT. The sensing TFT and the photodiode both have a structure comprising low temperature poly-silicon. A display panel contains the photo detector is also disclosed.

Abstract: A photodiode element includes a first layer of a first diffusion type and a second layer. The second layer defines a charge-collecting area. The charge-collecting area includes an active region of a second diffusion type and an inactive region. The active region surrounds the inactive region. The photodiode element also includes an intrinsic semiconductor layer between the first layer and the second layer.

Abstract: An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.

Abstract: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.

Abstract: The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer (12, 16) of second conductivity type is formed on a main surface of a first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) are formed at least on the second semiconductor layer to separate the device into the regions of photodiodes (PD1-PD4). A conductive layer (18) is formed on the second semiconductor layer 16 in a divided pattern that provides a segment for each photodiode and is connected to the second semiconductor layer (16) along the an outer periphery with respect to all photodiodes. An insulation layer (19, 21) is formed on the entire surface to cover conductive layer (18). An opening, which reaches the second semiconductor layer (16), is formed in the insulation layer (19, 21) in the region inside the pattern of conductive layer (18).

Abstract: A photodiode array includes a plurality of photodiodes arranged in a single semiconductor laminate including a first conductivity-type semiconductor layer and an absorption layer overlying the first conductivity-type semiconductor layer. The photodiode array also includes a functional portion among the photodiodes in a predetermined proportion. The functional portion acts as a monitor light receiving portion and/or a charge sweep portion. Each of the photodiodes and functional portion has a second conductivity-type region reaching the absorption layer from the surface of the semiconductor laminate and an electrode in ohmic contact with the second conductivity-type region.

Abstract: Wirebonds are formed to couple an opto-electronic device chip having two or more opto-electronic devices to a signal processing chip. Two or more mutually adjacent wirebond groups, each corresponding to one of the opto-electronic devices, are formed. For example, each wirebond group can include a first wirebond coupling a P-terminal of the opto-electronic device of the wirebond group to the signal processing chip, a second wirebond coupling an N-terminal of the opto-electronic device of the wirebond group to the signal processing chip, and a third wirebond coupling the opto-electronic device chip to the signal processing chip.

Abstract: The present invention provides high-speed, high-efficiency PIN diodes for use in photodetector and CMOS imagers. The PIN diodes include a layer of intrinsic semiconducting material, such as intrinsic Ge or intrinsic GeSi, disposed between two tunneling barrier layers of silicon oxide. The two tunneling barrier layers are themselves disposed between a layer of n-type silicon and a layer of p-type silicon.

Abstract: A method for reducing dislocation density between an AlGaN layer and a sapphire substrate involving the step of forming a self-organizing porous AlN layer of non-coalescing column-like islands with flat tops on the substrate.

Abstract: Intended is to provide a device structure, which makes the light receiving sensitivity and the high speediness of a photodiode compatible. Also provided is a Schottky barrier type photodiode having a conductive layer formed on the surface of a semiconductor layer. The photodiode is so constituted that a light can be incident on the back side of the semiconductor layer, and that a periodic structure, in which a light incident from the back side of the semiconductor layer causes a surface plasmon resonance, is made around the Schottky junction of the photodiode.

Abstract: Provided are a photodetector capable of suppressing variations in the output characteristics among photodiodes, and a display device provided with the photodetector. A display device in use has an active matrix substrate (20) including a transparency base substrate (2), a plurality of active elements and a photodetector. The photodetector includes a light-shielding layer (3) provided on one main surface of the base substrate (2), a photodiode (1) arranged on an upper layer of the light-shielding layer (3), and an electrode (12) arranged in the vicinity of the photodiode (1) on the upper layer of the light-shielding layer (3). The photodiode (1) includes a silicon layer (11), and the silicon layer (11) is insulated electrically from the light-shielding layer (3). The electrode (12) is insulated electrically from the light-shielding layer (3) and the silicon layer (11).

Abstract: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.

Abstract: A purpose is to provide a semiconductor optical device having good characteristics to be formed on a semi-insulating InP substrate. Firstly, a semi-insulating substrate including a Ru—InP layer on a conductive substrate is used. Secondly, a semi-insulating substrate including a Ru—InP layer on a Ru—InP substrate or an Fe—InP substrate is used and semiconductor layers of an n-type semiconductor layer, a quantum-well layer, and a p-type semiconductor layer are stacked in this order.

Abstract: A sealed semiconductor device having reduced delamination of the sealing layer in high temperature, high humidity conditions is disclosed. The semiconductor device includes a substrate and a stack of device layers on the substrate sealed with a sealing layer. The upper surface of a street area of the substrate is oxidized so that the oxidized region extends under the sealing layer. The presence of the oxidized region of the upper surface of the substrate helps reduce the delamination, because the oxidized surface does not react with water to the same extent as a non-oxidized surface. The semiconductor devices remain sealed after dicing through the street area because the oxidized surface does not delaminate.

Abstract: An image sensor includes a semiconductor substrate having a pixel region and a peripheral circuit region. An interlayer dielectric layer has metal wirings and a pad formed over the semiconductor substrate. A lower electrode is selectively formed over the metal wirings. A photo diode is formed over the interlayer dielectric layer of the pixel region. An upper electrode formed over the photo diode. Therefore, a vertical integration of the transistor and the photodiode may approach a fill factor to 100%, and provide higher sensitivity, implement more complicated circuitry without reducing sensitivity in each unit pixel, improve the reliability of the image sensor by preventing crosstalk, etc., between the pixels, and improve light sensitivity by increasing the surface area of the photo diode in the unit pixel.

Abstract: Provided are a photodetector capable of suppressing variations in the output characteristics among photodiodes, and a display device provided with the photodetector. A display device in use has an active matrix substrate (20) including a transparency base substrate (2), a plurality of active elements and a photodetector. The photodetector includes a light-shielding layer (3) provided on the base substrate (2), and a photodiode (1) arranged on an upper layer of the light-shielding layer (3). The light-shielding layer (3) is overlapped with the photodiode (1) in the thickness direction of the base substrate (2). The photodiode (1) includes a silicon layer (11) insulated electrically from the light-shielding layer (3). The silicon layer (11) includes a player (11c), an i-layer (11b) and an n-layer (11a) that are provided adjacent to each other in the planar direction. The p-layer (11c) is formed so that its area (length Lp) will be larger than the area (length Ln) of the n-layer (11a).

Abstract: A photovoltaic device having improved conversion efficiency as a result of an increase in the open-circuit voltage is provided. The photovoltaic device comprises a photovoltaic layer having a stacked p-layer, i-layer and n-layer, wherein the p-layer is a nitrogen-containing layer comprising nitrogen atoms at an atomic concentration of not less than 1% and not more than 25%, and the crystallization ratio of the p-layer is not less than 0 but less than 3. Alternatively, the n-layer may be a nitrogen-containing layer comprising nitrogen atoms at an atomic concentration of not less than 1% and not more than 20%, wherein the crystallization ratio of the n-layer is not less than 0 but less than 3. Alternatively, an interface layer may be formed at the interface between the p-layer and the i-layer, wherein the interface layer is a nitrogen-containing layer comprising nitrogen atoms at an atomic concentration of not less than 1% and not more than 30%.

Abstract: A photovoltaic device with improved cell properties having a photovoltaic layer comprising microcrystalline silicon-germanium, and a process for producing the device. A buffer layer comprising microcrystalline silicon or microcrystalline silicon-germanium, and having a specific Raman peak ratio is provided between a substrate-side impurity-doped layer and an i-layer comprising microcrystalline silicon-germanium.

Abstract: An image sensor includes a semiconductor substrate, an interconnection and an interlayer dielectric, an image sensing device, a trench, a buffer layer, a barrier pattern, a via hole, and a metal contact. The semiconductor substrate includes a readout circuitry. The interconnection and an interlayer dielectric layer are formed on and/or over the semiconductor substrate while the interconnection is connected to the readout circuitry. The image sensing device may be formed on and/or over the interlayer dielectric and a trench may be formed in the image sensing device, the trench corresponding to the interconnection. The buffer layer may be formed on a sidewall of the trench. The barrier pattern may be formed on the buffer layer with the via hole penetrating through the image sensing device and the interlayer dielectric under the barrier pattern and exposing the interconnection. The metal contact may be formed in the via hole.

Abstract: A photoelectric conversion device includes an intrinsic semiconductor layer, a first conductive type semiconductor layer disposed on a first side of the intrinsic semiconductor layer, and a second conductive type semiconductor layer disposed on a second side of the intrinsic semiconductor layer opposite the first side. The intrinsic semiconductor layer includes an amorphous semiconductor layer and a crystalline semiconductor layer including a plurality of crystals. A diameter of a crystal of the plurality of crystals is equal to or less than approximately 100 angstroms.

Abstract: An embodiment relates to a device comprising a nanowire photodiode comprising a nanowire and at least on vertical photogate operably coupled to the nanowire photodiode.

Abstract: A semiconductor photo detecting element includes a PIN-type photo detecting element and window semiconductor layer. The PIN-type photo detecting element has a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer is provided on the semiconductor substrate, is lattice-matched to the semiconductor substrate, includes a first conductivity type dopant, and has first band gap energy. The second semiconductor layer is provided on the first semiconductor layer, has the first band gap energy, and has a concentration of the first conductivity type dopant lower than that of the first semiconductor layer or is substantially undoped. The third semiconductor layer is provided on the second semiconductor layer. The window semiconductor layer has second band gap energy larger than the first band gap energy at a light-incoming side with respect to the second semiconductor layer and has a thickness of 5 nm to 50 nm.

Abstract: A photodetector is formed in a semiconductor body. A hard mask grating is photolithographically formed on a surface of the semiconductor body. The semiconductor body is etched using the hard mask grating as a mask. The etching is performed down to a predetermined depth. An implantation is performed such that an anode or cathode of the photodetector that has been interrupted during the etching is re-formed.

Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.

Abstract: A method for manufacturing a thin film type solar cell is disclosed, which is capable of reducing degradation of solar cell by decreasing the number of dangling bonding sites or SiH2 bonding sites existing in amorphous silicon owing to an optimal content ratio of ingredient gases, an optimal chamber pressure, or an optimal substrate temperature during a process for depositing an I-type semiconductor layer of amorphous silicon by a plasma CVD method, the method comprising forming a front electrode layer on a substrate; sequentially depositing P-type, I-type, and N-type semiconductor layers on the front electrode layer; and forming a rear electrode layer on the N-type semiconductor layer, wherein the process for forming the I-type semiconductor layer comprises forming an amorphous silicon layer by the plasma CVD method under such circumstances that at least one of the aforementioned conditions is satisfied, for example, a content ratio of silicon-containing gas to hydrogen-containing gas is within a range betwe