And Shaping, E.g., Cutting Or Bending, Etc. Patents (Class 29/835)
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Patent number: 7134198Abstract: A method for manufacturing an electric element built-in module including flip-chip mounting at least one electric element such as a semiconductor chip or a surface acoustic wave device on a wiring pattern, sealing the electric element with a thermosetting resin composition, and grinding or abrading the thermosetting resin composition and electric element from a side of the electric element opposite that of the wiring pattern. The method provides upper surfaces of the electric element and the thermosetting resin composition that are substantially flush with each other. The method provides an electric element built-in module suitable for high-density packaging with a reduced thickness without damaging the electric element and while maintaining mechanical strength.Type: GrantFiled: September 3, 2003Date of Patent: November 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Seiichi Nakatani, Yoshihiro Bessho, Yasuhiro Sugaya, Keiji Onishi
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Patent number: 7127802Abstract: A method for fabricating a composite plate for a magnetic resonance imaging magnet. The method including cutting a starting plate having oppositely-directed major surfaces into a plurality of strips. Each of the strips having a width of approximately greater than 9 inches and faces which originally constituted parts of the major surfaces of the starting plate. The strips may be positioned to form the composite plate such that the width of each of the strips is equal to a thickness of the composite plate and the faces of the strips confront one another.Type: GrantFiled: September 16, 2004Date of Patent: October 31, 2006Assignee: Fonar CorporationInventors: Jevan Damadian, John Linardos, Gordon T. Danby, Raymond V. Damadian
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Patent number: 7127805Abstract: A system and apparatus are described for a flexible tape constructed of a material suitable to convey electronic devices through an entire manufacturing process without removing the electronic packages from the tape. According to one embodiment, part receiving areas are located within the tape. Each part receiving area is suitable to hold an electronic device. A retention channel encompasses each part receiving area. The retention channel extends substantially an entire length along each edge of each part receiving area. The retention channel comprises an upper tab and a lower tab wherein the upper tab is flush with an upper surface of the flexible tape and extends into the part receiving area and the lower tab extends below a lower surface of the flexible tape and into the part receiving area.Type: GrantFiled: November 20, 2002Date of Patent: October 31, 2006Assignee: Intel CorporationInventor: Jeffrey Watson
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Patent number: 7126825Abstract: A combined chip/heat-dissipating metal plate includes a chip and a heat-dissipating metal plate bonded to a side of the chip, wherein the heat-dissipating metal plate is in a stretched state. The heat-dissipating metal plate is stretched before bonding the chip. Preferably, the stretched heat-dissipating metal plate has a thickness smaller than that of the heat-dissipating metal plate before stretching by not more than 20%. The chip has good compression strength in the radial direction and the heat-dissipating metal plate has higher tensile strength after being stretched and taking shape, providing a more stable structure and avoiding damage to the chip due to radially outward tension. The combined chip/heat-dissipating metal plate thus obtained is more stable and thus benefits the subsequent cutting by a laser cutting apparatus.Type: GrantFiled: December 7, 2004Date of Patent: October 24, 2006Assignee: Cleavage Enterprise Co., Ltd.Inventor: Chih-Ming Hsu
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Patent number: 7103965Abstract: The invention relates to a method of making a chip resistor using a material substrate for which are set a plurality of first cutting lines extending in a first direction and a plurality of second cutting lines extending in a second direction perpendicular to the first direction. The method includes an upper electrode forming step A for forming a thick upper conductor layer on the upper surface of the substrate by printing and baking a metal organic paste, a lower electrode forming step B for forming a thick lower conductor layer on the lower surface of the substrate by printing and baking metal organic paste, and a resistor element forming step C for forming a thin resistor layer by depositing a resistor material on the upper surface of the substrate. Preferably, the upper and the lower surfaces of the material substrate are flat.Type: GrantFiled: January 15, 2003Date of Patent: September 12, 2006Assignee: Rohm Co., Ltd.Inventor: Masanori Tanimura
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Patent number: 7093357Abstract: A method for manufacturing an electronic component including the steps of preparing a pair of substantially round conductive wires, bending one end portion of each of the pair of conductive wires outward at an angle of about 90 degrees, forming a flat portion on each of the pair of substantially round conductive wires by press extending at least the portion on the tip side from the bending point so as to be extended substantially parallel to a lead portion of the lead terminal, such that a thickness of the flat portion is less than a diameter of each of the pair of substantially round conductive wires, forming a cup-shaped holder portion by bending the flat portion inwards, holding both end portions of a piezoelectric element in a pair of the cup-shaped holder portions, and electrically and mechanically connecting the cup-shaped holder portions and the electrodes formed in both end portions of the piezoelectric element by using a conductive joining material.Type: GrantFiled: February 17, 2004Date of Patent: August 22, 2006Assignee: Murata Manufacturing Co., Ltd.Inventors: Masanobu Sugimori, Kenichi Nakamura
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Patent number: 7082681Abstract: A vertically mountable semiconductor device including a plurality of stub contacts extending perpendicularly from a bottom edge thereof. The stub contacts may be formed by trimming the leads of an existing vertical surface mount package. A complementary alignment device includes a receptacle for receiving the vertically mountable semiconductor device. The alignment device is attachable to a carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, a contact element applies a downward force to the vertically mountable semiconductor device to establish and maintain an electrical connection between the vertically mountable semiconductor device and the carrier substrate.Type: GrantFiled: May 1, 2003Date of Patent: August 1, 2006Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Walter L. Moden, Warren M. Farnworth
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Patent number: 7076873Abstract: A cavity plate of an ink-jet head is formed by stacking a clad plate on a manifold plate. The clad plate is formed by unitarily bonding a first layer and a second layer, which are made of different materials. Pressure chambers and communicating holes to the pressure chambers are formed in the first and second layers, respectively. Each of the first and second layers is etched using an etching agent that is able to only one of the layers to form therein the pressure chambers or the communicating holes. Thus, the pressure chambers and the communicating holes are formed with high precision in depth. In addition, the cavity plate including the clad plate with a predetermined thickness is easy to handle when manufactured into an ink-jet head.Type: GrantFiled: September 9, 2004Date of Patent: July 18, 2006Assignee: Brother Kogyo Kabushiki KaishaInventors: Hiroto Sugahara, Masaaki Deguchi, Atsushi Ito
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Patent number: 7059044Abstract: For the purpose of achieving enhanced reliability with respect to interlayer connections of printed wiring boards, a manufacturing method of printed wiring boards of the present invention includes any one of the steps of A) restricting the resin flowing in hot press processing, B) joining fiber reinforcements together by fusion or adhesion, C) having the thickness of a board material reduced after a filling process and D) forming a low fluidity layer via a filler mixed in a board material. Such properties as allowing the resin flowing in hot press processing to be controlled are provided to a material for manufacturing printed wiring boards of the present invention or to a volatile ingredient contained therein to allow the thickness of a board material to be reduced efficiently after a filling process.Type: GrantFiled: July 17, 2002Date of Patent: June 13, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toshihiro Nishii
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Patent number: 7005584Abstract: One embodiment of the invention provides a compact navigation device assembly that is rugged, compact and does not require independent connector components to interconnect multiple circuit boards. According to one implementation of the compact navigation device assembly, an electrical or electromechanical circuit may be laid-out among a plurality of circuit boards that are electrically joined along their edges in a three-dimensional structure without the use of discrete connectors or components. Each circuit board may have one or more crenelated, serrated, and/or notched edge to electrically join the circuit board to other circuit boards. Such crenelated edges may be plated for electrical conductivity and may be joined to corresponding crenelated edges with solder or other electrically conductive materials.Type: GrantFiled: February 13, 2004Date of Patent: February 28, 2006Assignee: Honeywell International Inc.Inventors: Robert W. Levi, Ron Fang
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Patent number: 6996882Abstract: A surface acoustic wave element includes a laminated substrate where a first substrate made of a piezoelectric material is laminated over a second substrate made of a material different from that of the first substrate, and at least one pair of comb-shaped electrodes formed on one main plane of the first substrate. A step or a notch is formed on the periphery of the laminated substrate on the side of the first substrate.Type: GrantFiled: June 10, 2002Date of Patent: February 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Keiji Onishi, Hiroki Sato, Yoshihiro Tomita
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Patent number: 6990733Abstract: A land grid array connector is formed by attaching a reinforcing member to a frame and coating the reinforcing member with an elastomeric compound to form a reinforced, flexible body portion of the connector. Conductive wires are inserted in pairs in an array in the fabric extent. Free ends of the wires extend past the elastomeric compound to provide contacts of the connector. The pairs of wires provide redundancy for the contacts to ensure a reliable connection.Type: GrantFiled: February 20, 2004Date of Patent: January 31, 2006Assignee: Molex IncorporatedInventors: John E. Lopata, James L. McGrath, Arindum Dutta, Marvin Menzin, Daniel Fisher, Jr.
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Patent number: 6971148Abstract: Multiple layer elements for a transducer array are provided. Each element comprises two or more layers of transducer material. Various of the elements are manufactured by one or more of: (1) stacking to form a multiple-layer, multiple-dimensional array where the layers are polymericly bonded and electrically connected through asperity contact, (2) using air or gas to separate at least two elements, (3) stacking an even number of layers where each layer is electrically connected through asperity contact, (4) using multiple-layers where each layer comprises transducer material and electrodes in a substantially same configuration, and (5) electrically isolating electrodes on layers by kerfing or cutting after bonding the layers together.Type: GrantFiled: June 28, 2002Date of Patent: December 6, 2005Assignee: Acuson CorporationInventors: John P. Mohr, III, Worth B. Walters, Sevig Ayter
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Patent number: 6962829Abstract: A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first surface. The first metallizations, IC chip including bonding pads and first substrate surface are then encapsulated. Interconnection balls or pads are formed at substrate bonding locations on a substrate second surface, the interconnection pads or balls being electrically connected to corresponding first metallizations. The substrate and encapsulant are then cut along the periphery of each section to form the plurality of IC chip packages.Type: GrantFiled: May 17, 2002Date of Patent: November 8, 2005Assignee: Amkor Technology, Inc.Inventors: Thomas P. Glenn, Roy D. Hollaway, Anthony E. Panczak
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Patent number: 6938331Abstract: A method for fabricating a filament-affixed trace within an electronic device, such as a circuit board or microelectronic device. Conductive traces are affixed to the surface of a composite substrate containing filaments in a matrix bonded to an underlying solid material. The matrix is then removed, leaving the conductive traces suspended or supported by filaments. The signal intensity attenuation for filament-suspended or filament-supported signal lines is much lower than signal lines embedded in solid dielectric materials, allowing for transmission of significantly higher frequency signals within filament-suspended and filament-supported signal lines.Type: GrantFiled: November 6, 2003Date of Patent: September 6, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: James J. deBlanc, David Dickey, Andrew Michael Cherniski
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Patent number: 6936502Abstract: A method for implementing a circuit component on a surface of a multilayer circuit board is provided. The circuit component includes a plurality of pins and the circuit board includes a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The method comprises the step of forming at least one pin of the plurality of pins of the circuit component to have a length compatible with a depth of a corresponding via of the circuit board.Type: GrantFiled: May 14, 2003Date of Patent: August 30, 2005Assignee: Nortel Networks LimitedInventors: Aneta Wyrzykowska, Herman Kwong, Luigi Difilippo
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Patent number: 6928718Abstract: An assembly and method for array processing of hermetically sealed Surface Acoustic Wave (SAW) Devices employs a non-conductive material having an array of spaced cavities extending into the material for receiving a SAW die face down, in a flip-chip arrangement. Each cavity has a peripheral recess dimensioned to receive a lid for hermetically sealing the die within the cavity. Conductive paths are provided from the interior of the cavity to the surface of the array for providing an electrical contact with the SAW die. Individual SAW devices are then provided by cutting along separation lines between adjacent cavities after a plurality of die have been hermetically sealed within its cavity.Type: GrantFiled: May 24, 2001Date of Patent: August 16, 2005Assignee: Sawtekk, Inc.Inventor: Charles Carpenter
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Patent number: 6915567Abstract: An housing of a meter unit is inserted from above into a meter unit support hole which is provided in the rear handle cover. Engagement claws of the housing are engaged with claw receiving portions of the rear handle cover, thereby prevent the housing from coming out. Male connector is provided beforehand in the rear handle cover, and inserting the housing of the meter unit into the meter unit support hole causes the female connector of the housing to be automatically connected to the male connector, thus completing the wiring work of the meter unit. The wiring work on the meter unit supported on the rear handle cover of the motorcycle can therefore be performed easily and reliably.Type: GrantFiled: October 29, 2001Date of Patent: July 12, 2005Assignee: Toyo Denso Co., Ltd.Inventors: Kazuhiko Nakao, Yukihiro Hayasaka, Hiroshi Sakamoto
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Patent number: 6898848Abstract: A chip is fixed via an insulating film on a tape carrier on one main surface of which plural inner leads are laid and each electrode pad of the chip is bonded to each inner lead. The inner lead is bonded to the electrode pad when the chip is supplied in a fixed position for a bonding tool using a sprocket hole of the ape carrier. Next, the respective positions of the inner lead and the electrode pad are recognized and the center line of the inner lead is recognized. The inner lead is touched to the chip by the bonding tool and after the inner lead is pushed in the direction of the base and bent in the form of a letter S. the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.Type: GrantFiled: December 13, 2002Date of Patent: May 31, 2005Assignee: Renesas Technology Corp.Inventors: Tatsuyuki Ohkubo, Keisuke Nadamoto, Yoshifumi Katayama
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Patent number: 6898845Abstract: A method for manufacturing a plurality of hybrid electronic circuits for active implantable medical devices and circuits made by the process.Type: GrantFiled: January 17, 2002Date of Patent: May 31, 2005Assignee: ELA Medical S.A.Inventors: Yves Van Campenhout, Dominique Gilet, Thierry Legay
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Patent number: 6892449Abstract: A method of manufacturing a plurality of electro-optical sub-assemblies in parallel is provided. A plurality of printed circuit boards (PCBs) are preferably formed in a panel of flex material. Rigid substrates can be arranged along regions of the PCBs. A plurality of electrical components, including electro-optical semiconductor devices, are preferably located on the rigid substrates. Lens arrays are preferably aligned over the electro-optical semiconductor devices, such as through an alignment mechanism. The PCBs can then be singulated into individual electro-optical sub-assemblies. The rigid substrates can be a plurality of leadframes formed on a matrix leadframe. The matrix leadframe is preferably attached to the panel of flex material such that the leadframes are arranged in proximity to leadframe cutout regions of the PCBs. Electrical interconnections are then preferably formed between the electrical components on the leadframe and the PCBs.Type: GrantFiled: October 9, 2002Date of Patent: May 17, 2005Assignee: Cypress Semiconductor Corp.Inventors: Brenor Brophy, Marc Hartranft, Syed Tariq Shafaat, Jeff Hall
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Patent number: 6886247Abstract: Methods to singulate circuit forming regions of a circuit board substrate assembly includes providing a plurality of circuit forming regions including at least one pair of adjacent circuit forming regions separated by at least one opening defined in substrate material between each pair of adjacent circuit forming regions. At least a portion of interconnection regions along singulation axes are removed to singulate the circuit forming regions.Type: GrantFiled: December 2, 2003Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventors: Zane Drussel, Derek Hinkle
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Patent number: 6883227Abstract: Methods of manufacturing an antenna are presented. The antenna is capable of being mounted on a printed circuit board. In accordance with the method, the design dimension of a unitary piece of material are selected according to an operating wavelength. The unitary piece of material is stamped out from a larger section of material according to the design dimensions to form an antenna. The unitary piece of material includes a circular area and a stem area. The circular area has a center and an outer region. The stem area has a first end and a second end. The first end is joined with the outer region. The unitary piece is bendable at the first end and the outer region.Type: GrantFiled: July 24, 2001Date of Patent: April 26, 2005Assignee: Atheros Communications, Inc.Inventors: Jovan E. Lebaric, Andy Dao
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Patent number: 6874222Abstract: Methods of manufacturing an antenna are presented. The antenna is capable of being mounted on a printed circuit board. In accordance with the method, the design dimension of a unitary piece of material are selected according to an operating wavelength. The unitary piece of material is stamped out from a larger section of material according to the design dimensions to form an antenna. The unitary piece of material includes a circular area and a stem area. The circular area has a center and an outer region. The stem area has a first end and a second end. The first end is joined with the center. The unitary piece is bendable at the first end and the center.Type: GrantFiled: February 13, 2003Date of Patent: April 5, 2005Assignee: Atheros, Inc.Inventors: Jovan E. Lebaric, Andy Dao
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Patent number: 6848170Abstract: A magnet for magnetic resonance imaging has an interior working space within the magnet frame sufficient to accommodate a physician and a patient. Because the physician is positioned inside the magnet frame, the physician has unimpeded access to the patient. Elements of the magnet frame desirably encompass a room, and the magnet frame may be concealed from view of a patient within the room. Preferred embodiments facilitate MRI imaged guided surgery and other procedures performed while the patient is being imaged, and minimize claustrophobia experienced by the patient. Also provided is a magnet having field coils disposed about the of pole portions of the magnet. A diagnostic facility for high volume MRI use is also disclosed.Type: GrantFiled: May 10, 2001Date of Patent: February 1, 2005Assignee: Fonar CorporationInventors: Jevan Damadian, John Linardos, Gordon T. Danby, Raymond V. Damadian
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Patent number: 6848155Abstract: A method of manufacturing an edge reflection type surface acoustic wave device using a Shear Horizontal type surface acoustic wave includes the steps of making a first half cut defining a first end surface portions having a smooth surface, that is, opposing two end surfaces which function as reflection end surfaces, from the upper surface of a piezoelectric substrate after at least one of a plurality of IDTs has been formed on the upper surface of the piezoelectric substrate, making a second half cut for forming second end surface portions having a rough surface after making the first cut, and making a full cut for cutting the piezoelectric substrate so as to reach the lower surface of the piezoelectric substrate outside of the second end surface portions in the surface acoustic wave propagation direction.Type: GrantFiled: May 11, 2004Date of Patent: February 1, 2005Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasuhiro Kuratani, Takao Mukai, Tomoyasu Miyata, Hideharu Yoshikawa
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Patent number: 6845554Abstract: The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, the functional circuit units (101d) are picked up by means of a handling device (101) and are placed down on a second film (102b) by means of the handling device (103), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units (101d).Type: GrantFiled: November 18, 2002Date of Patent: January 25, 2005Assignee: Infineon Technologies AGInventors: Gerd Frankowsky, Harry Hedler, Roland Irsigler, Thorsten Meyer, Barbara Vasquez
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Patent number: 6834419Abstract: The invention relates to an electromechanical drive or a sensor element composed of piezoelectric elements arranged in the form of a stack. The drive or the sensor element is intended for measurement instruments and operates even at very high temperatures. The new drive or the new sensor element (10) for this purpose comprises a number of piezoelectric ceramic layers (12a-f), with electrode layers (16a-e) in each case being arranged between two mutually facing surfaces of directly adjacent piezoelectric ceramic layers. Connectors (18a,b) in the form of wires run in grooves (14a-d) in the electrode layers (16a-e) in order to make electrical contact with the electrode layers (16a-e), and are passed out of the electrode layers (16a-e).Type: GrantFiled: November 7, 2003Date of Patent: December 28, 2004Assignee: Endress + Hauser GmbH + Co.Inventors: Sergej Lopatin, Igor Getman, Anatoliy Panitch, Yuriy Wusewker
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Publication number: 20040244193Abstract: Apparatus and method for electrically connecting an electric conductor to an electronic component including the steps of providing a textile material, in which at least, one flexible, wire-like and/or thread-like electric conductor is arranged, severing the electric conductor at a point to be connected, arranging a contact-making device of the component on at least one surface side of the textile material at the point on the conductor to be connected, and connecting the conductor electrically to the contact-making device.Type: ApplicationFiled: June 4, 2004Publication date: December 9, 2004Applicant: Infineon Technologies AGInventors: Stefan Jung, Christl Lauterbach
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Patent number: 6826822Abstract: One embodiment is directed to a method for trimming a rubber plate which is configured to be placed on a platform of an ion implanter, wherein the platform of the ion implanter includes a plurality of primary holes and a plurality of primary notches. The method comprises providing a template including a plurality of secondary holes corresponding to the plurality of primary holes of the platform of the ion implanter and a plurality of secondary notches corresponding to the plurality of primary notches of the platform of the ion implanter; and trimming the rubber plate using the template as a guide to form a plurality of tertiary holes in the rubber plate corresponding to the plurality of secondary holes of the template and to form a plurality of tertiary notches in the rubber plate corresponding to the plurality of secondary notches of the template.Type: GrantFiled: February 11, 2002Date of Patent: December 7, 2004Assignee: Mosel Vitelic, Inc.Inventors: Cheng-Min Pan, Hua-Jen Tseng, Chun-Chieh Lee, Sheng-Feng Hung
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Patent number: 6782616Abstract: The present disclosure relates to connection arrangements for electrical devices. In the connection arrangements, an electrical device having at least one ledge that includes a plurality of contact terminals provided thereon is electrically connected to an electrical component having a plurality of contacts formed thereon.Type: GrantFiled: January 12, 2001Date of Patent: August 31, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventor: Kenneth J. Eldredge
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Publication number: 20040154162Abstract: A method for fabricating a multi-layer printed circuit board can include forming an etching resist layer on a first metal layer having plating grooves that selectively expose the first metal layer, forming a plated layer at the surface of the first metal layer exposed by the plating groove through a plating process to form connection protrusion, removing the etching resist layer, forming an insulation layer at the first metal layer and positioning a second metal layer at the surface of the insulation layer coupled to an end portion of the connection protrusion. By forming the connection protrusion through the plating process, a loss of material can be reduced and a strength of the connection protrusion can be increased. Further, a complexity of the fabrication process is reduced to reduce costs and increase productivity.Type: ApplicationFiled: February 3, 2004Publication date: August 12, 2004Applicant: LG Electronics Inc.Inventors: Sung-Gue Lee, Jung-Ho Hwang, Joon-Wook Han, Sang-Min Lee, Tae-Sik Eo, Yu-Seock Yang
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Publication number: 20040154166Abstract: A hole plugging method for a printed circuit board, a hole plugging device in accordance therewith and a manufacturing method in accordance therewith where a mask for selectively exposing a via hole, a through hole and a surface pattern of the printed circuit board is positioned on the board having the via hole and the through hole to electrically connect circuit patterns formed on the surface of the board and in the board and an insulating material is plugged in the via hole by abutting and pushing the material on the surface of the board. Therefore, the insulating material can be plugged smoothly without a void, the processing is simplified by plugging the insulating material just to the height of the circuit pattern in a space between the circuit patterns and accordingly, damage to the circuit pattern can be prevented.Type: ApplicationFiled: February 9, 2004Publication date: August 12, 2004Applicant: LG ELECTRONICS INC.Inventors: Sung Gue Lee, Sung Sik Cho, Yong Il Kim, Yong Soon Jang, Ho Sung Choi, Sang Jin Kong, Young Hwan Kim
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Publication number: 20040148765Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.Type: ApplicationFiled: February 4, 2003Publication date: August 5, 2004Applicant: International Business Machines CorporationInventors: Jon A. Casey, James G. Balz, Michael Berger, Jerome Cohen, Charles Hendricks, Richard Indyk, Mark LaPlante, David C. Long, Lori A. Maiorino, Arthur G. Merryman, Glenn A. Pomerantz, Robert A. Rita, Krystyna W. Semkow, Patrick E. Spencer, Brian R. Sundlof, Richard P. Surprenant, Donald R. Wall, Thomas A. Wassick, Kathleen M. Wiley
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Patent number: 6769166Abstract: A method of making an electrical current sensor having an electrical conducting portion (6; 6a, 6b) of rectangular cross-section being surrounded, on three of its lateral faces, by a magnetic circuit portion (7) which has end portions (7′, 7″) having planar surfaces situated substantially in a plane of a fourth lateral face of the conductor portion (6), a magnetic field detector (3; 24; 26) being arranged opposite the fourth lateral face. The conductor portion (6) is made by photo-lithography and etching in a layer of electrically conducting material applied on a first surface of a flat support member (1; 1′; 1″) or on intermediate layers (8, 9, 10, 11) deposited on the support member. The magnetic circuit portion (7) is made by photo-lithography and etching in a layer of magnetically permeable material applied on the conductor portion (6) on the first surface of the support member (1; 1′, 1″) or of an intermediate layer (8).Type: GrantFiled: February 14, 2000Date of Patent: August 3, 2004Assignee: Liaisons Electroniques-Mecaniques LEM SAInventor: Hubert Blanchard
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Publication number: 20040111881Abstract: A transformer balun is obtained that is symmetrical in structure, provides high current, or high voltage, amplification and has high coupling coefficients while maintaining minimal overall size. The balun structure includes primary and secondary metal windings at separate layer interfaces. The primary and secondary metal windings are symmetrical and can have any number of turns, which is only limited by integrated circuit area and capacitance. Accordingly, the primary and secondary windings may be on as many layers as needed. Further, the primary and/or secondary may include a center tap ground, which enables the winding to be used as a differential port.Type: ApplicationFiled: December 4, 2003Publication date: June 17, 2004Inventors: Hung Yu Yang, Jesse A. Castaneda, Reza Rofougaran
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Patent number: 6739042Abstract: A method of mounting a mechatronics control module (14) includes an electronic control unit (16) having a flex foil circuit (34) with a multiple of mounted electronic components including sensors (24) which sense the hydraulic state of the transmission clutch or other frictional engagement elements within the transmission system. The sensor is mounted to a base plate (82) which is mounted to a fixture (88) which folds the flap (84.) When the base plate (82) and mounted sensor are removed from the fixture (88), the flap (84) unfolds so that the circuit traces of the flex foil (34) are adjacent the contacts (94.) In a final step, the circuit traces (81) are electrically connected to the contacts (94.Type: GrantFiled: August 23, 2001Date of Patent: May 25, 2004Assignee: Siemens VDO Automotive CorporationInventor: Michael D. Thorum
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Patent number: 6718619Abstract: Methods of manufacturing an antenna are presented. The antenna is capable of being mounted on a printed circuit board. In accordance with the method, the design dimension of a unitary piece of material are selected according to an operating wavelength. The unitary piece of material is stamped out from a larger section of material according to the design dimensions to form an antenna. The unitary piece of material includes a circular area and a stem area. The circular area has a center and an outer region. The stem area has a first end and a second end. The first end is joined with the center. The unitary piece is bendable at the first end and the center.Type: GrantFiled: July 24, 2001Date of Patent: April 13, 2004Assignee: Atheros Communications, Inc.Inventors: Jovan E. Lebaric, Andy Dao
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Patent number: 6715192Abstract: A fabricating method of a piezoelectric/electrostrictive device including a driving portion having thin plates facing each other and a film-like piezoelectric/electrostrictive element formed on the surface of at least one thin plate of the thin plates, and a fixing portion and a movable portion in rectangular solid form. The thin plates are spanned so that the side faces of the movable portion and the fixing portion are continuous. The fabricating method includes steps of preparing a laminated body of green sheets comprising at least one green sheet to constitute the thin plate, and at least one green sheet with at least one hole formed thereon, sintering a green-sheet laminated body, and forming a piezoelectric/electrostrictive element on an outer surface of the thin plates of the sintered body obtained.Type: GrantFiled: October 3, 2001Date of Patent: April 6, 2004Assignee: NGK Insulators, Ltd.Inventors: Yukihisa Takeuchi, Tsutomu Nanataki, Toshikazu Hirota, Koji Kimura
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Patent number: 6708400Abstract: Reflow soldering of a variety of circuit boards (9, 11, 15) in a variety of sizes and shapes to assigned locations on the base or carrier (13) of the electronic module housing (3) is simplified by eliminating custom made metal blocks previously used to clamp the circuit boards against the carrier metal. Instead, the solder-backed circuit boards are placed in assigned positions in the module housing and the inside volume of that housing is filled (22) with particulate, such as small beads (17), covering the circuit boards, but leaving the edges of the upstanding metal shields (5 and 7) visible. A plate (21) backed foam sheet (19) is placed over the module housing (24) and clamped down (26), pressing against the beads. The clamped assembly is then heated (28) to reflow the solder, soldering the circuit boards in place.Type: GrantFiled: October 15, 2001Date of Patent: March 23, 2004Assignee: Northrop Grumman CorporationInventors: Mark Kintis, Charles G. Turner
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Patent number: 6694609Abstract: A land grid array connector is formed by attaching a reinforcing member to a frame and coating the reinforcing member with an elastomeric compound to form a reinforced, flexible body portion of the connector. Conductive wires are inserted in pairs in an array in the fabric extent. Free ends of the wires extend past the elastomeric compound to provide contacts of the connector. The pairs of wires provide redundancy for the contacts to ensure a reliable connection.Type: GrantFiled: March 22, 2001Date of Patent: February 24, 2004Assignee: Molex IncorporatedInventors: John E. Lopata, James L. McGrath, Arindum Dutta, Marvin Menzin, Daniel Fisher, Jr.
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Publication number: 20040026108Abstract: Disclosed is an improved composite substrate for use in a magnetic recording-and-reproducing device. It comprises an “L”-shaped main plate and a separate sub-plate. The “L”-shaped main plate has a major section of relatively large area and a minor section of relatively small area, integrally connected to one side of the major section. The sub-plate has a square or rectangular piece cut and separated from the minor section of the main plate. When being inversely arranged and jointed together two composite substrates can define a square or rectangular shape.Type: ApplicationFiled: July 2, 2003Publication date: February 12, 2004Inventor: Michiharu Maeda
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Patent number: 6681482Abstract: A method of connecting a heatspreader to an integrated circuit device that is connected to a substrate in a flip-chip configuration includes forming a heatspreader from a single flat sheet of metal. The heatspreader has a heatspreader plate and a plurality of legs. The legs are flat plate portions substantially parallel to the heatspreader plate. A first thermal interface material is used to connect the heatspreader plate to a non-active side of the integrated circuit device. A second thermal interface material is used to connect each of the plurality of legs to the substrate.Type: GrantFiled: February 2, 2000Date of Patent: January 27, 2004Assignee: Agere Systems, Inc.Inventors: David Lischner, Raymond J. Nika, James Robert Ronemus
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Patent number: 6678952Abstract: A microelectronic element is formed from a structure including metal layers on top and bottom sides of a dielectric. Apertures are formed in the top metal layer, and vias are formed in the dielectric in alignment with the apertures. Top and bottom conductive features are formed in proximity to the vias, as by selectively depositing a metal on the metal layers or selectively etching the metal layers. The top and bottom conductive features are connected to one another by depositing a conductive material into the vias, most preferably without seeding the vias as, for example, by depositing solder in the vias.Type: GrantFiled: July 27, 2001Date of Patent: January 20, 2004Assignee: Tessera, Inc.Inventor: Owais Jamil
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Patent number: 6678927Abstract: Surface mount capacitors are made having ultra-small dimensions of length, width and height. For example, capacitors of 0402 size and smaller may be produced having lower height than has been achieved in the prior art. The components have L-shaped terminations on respective ends thereof, providing bottom lands for mounting to a circuit board. At most, the component will have top lands of negligible size to provide a large gap width between the terminations across the top surface of the component. In some embodiments, the top surface may also include orientation indicia located thereon. The invention also provides improved methodology for terminating a capacitor or other surface mount component.Type: GrantFiled: September 29, 2000Date of Patent: January 20, 2004Assignee: AVX CorporationInventor: Gennady Retseptor
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Patent number: 6658728Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad/via.Type: GrantFiled: July 27, 2001Date of Patent: December 9, 2003Assignee: Xerox CorporationInventors: David Kirtland Fork, Jackson Ho, Rachel King-ha Lau, JengPing Lu
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Patent number: 6647620Abstract: A center bond flip chip device carrier and a method for making and using it are described. The method includes forming a seat with a cut out portion in at least one trace on a substrate and providing an elastomeric material over the substrate. The seat is sized and configured to receive a conductive connecting structure. The elastomeric material has a gap at the seat to allow electrical connection of the conductive connecting structure with a semiconductor die.Type: GrantFiled: October 6, 2000Date of Patent: November 18, 2003Assignee: Micron Technology, Inc.Inventors: Tongbi Jiang, Alan G. Wood
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Patent number: 6640418Abstract: In processing a head unit in which a head relative height Y is Y′ with a grinding amount &Dgr;GD of &Dgr;GD′, the relationship between distances Bo between a vertex of a curved surface as a front face of a head chip and a head gap before and after grinding the front face of the head chip and a gap depth dimension GD, is predetermined with respect to a head unit in which the head relative height is substantially equal to Y′, through which Bo1 as the value of Bo before grinding corresponding to a target value of the value of Bo after grinding is determined and used as Bo1 of the head unit in which the head relative height Y is Y′. Thus, grinding of the front face of the head chip is conducted after Bo1 corresponding to the target value is determined. Hence, a head unit with the value of Bo after grinding falling within the range of standard values can be manufactured efficiently, and accordingly the yield can be improved.Type: GrantFiled: July 31, 2001Date of Patent: November 4, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuya Okana, Mitsuhisa Fujiki, Satoshi Yamabayashi, Shinya Ogasawara
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Patent number: 6637087Abstract: A method of manufacturing an edge reflection type surface acoustic wave device includes the step of preparing a surface acoustic wave mother substrate having a plurality of interdigital transducers formed on one main surface thereof. A cut groove is formed in the substrate by cutting the surface acoustic wave mother substrate beginning from the one main surface side thereof. This step of forming a cut groove is repeated so as to produce a plurality of cut grooves so that the first reflection edge of the respective surface acoustic wave devices are sequentially formed. Next, similarly, cut grooves are sequentially formed on the surface acoustic wave mother substrate from the one main-face side thereof so as not to reach the other main surface thereof, whereby the second reflection edges of the respective surface acoustic wave devices are sequentially formed.Type: GrantFiled: March 17, 2000Date of Patent: October 28, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Hideya Horiuchi, Michio Kadota, Junya Ago, Seigo Hayashi, Yasunori Takakuwa
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Patent number: 6634098Abstract: A vertically mountable semiconductor device including a plurality of stub contacts extending perpendicularly from a bottom edge thereof. A complementary alignment device includes a receptacle for receiving the vertically mountable semiconductor device. The alignment device is attachable to a carrier substrate. Upon attachment of the alignment device to a carrier substrate and insertion of a vertically mountable semiconductor device into the receptacle, a contact element applies a downward force to the vertically mountable semiconductor device to establish and maintain an electrical connection between the vertically mountable semiconductor device and the carrier substrate.Type: GrantFiled: July 20, 1999Date of Patent: October 21, 2003Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Walter L. Moden, Warren M. Farnworth