Abstract: The present invention includes: a first current source, through which a first current is made to flow; a second current source, through which a second current set at a certain ratio to the first current is made to flow; a first current path, which includes a second resistor, a first resistor, and a first bipolar transistor that are connected to the first current source in a sequential manner, and through which the first current is made to flow; a second current path, which includes a third resistor and a 0th bipolar transistor that are connected to the second current source in a sequential manner, and through which the second current is made to flow; an operational amplifier, which controls current amounts of the first current and the second current by an output from an output end, and of which a positive input end is connected to a connection point between the second resistor and the first resistor, and of which a negative input end is connected to a connection point between the third resistor and the 0th bi

Abstract: A booster circuit includes a boost converter configured to boost an input voltage and performs feedback control such that an output voltage becomes a set value on the basis of a voltage applied to a feedback terminal and an internal feedback reference voltage, a power supply unit configured to generate a reference voltage with a smaller error than the feedback reference voltage, and a control unit configured to compare a voltage corresponding to the output voltage of the boost converter with the reference voltage, and configured to output a control signal indicating a comparison result to the feedback terminal of the boost converter.

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal imposes the drain-source current of the first transistor.

Abstract: A reference generator system can include a PTAT circuit coupled to a signal supply node and configured to provide a voltage reference signal or a current reference signal that is based on a physical characteristic of one or more components of the PTAT circuit and a correction signal. The system can include a CTAT circuit coupled to the PTAT circuit and configured to provide the correction signal to the PTAT circuit. In an example, the reference generator system can be implemented at least in part using NMOS devices that comprise a portion of an indium gallium zinc oxide (IGZO) substrate.

Abstract: A reference current/voltage generator includes a current mirror unit and a current-mode temperature compensation unit. The current mirror unit generates a first current, a first sum current and a second sum current flowing through first to third terminals thereof, and the first current, the first sum current and the second sum current are in a multiple relationship. The current-mode temperature compensation unit is electrically connected to the second and third terminals of the current mirror unit, and when a voltage on the second terminal is equal to a voltage on the third terminal, the first sum current is a sum of a current proportional to absolute temperature (PTAT) and a current complementary to absolute temperature (CTAT). The first terminal of the current mirror unit is an output terminal of the reference current/voltage generator and configured to output the first current as a reference current.

Abstract: An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.

Abstract: An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

Abstract: Provided is a reference voltage circuit configured to supply a reference voltage in which a variation in voltage with respect to a variation in power supply voltage is suppressed. The reference voltage circuit includes a reference voltage generation circuit which includes an output line for supplying a generated reference voltage to an output terminal; and an output control circuit which includes an output transistor and a stabilization transistor, and is configured to control the supply of the reference voltage to the output terminal, the output transistor containing a gate to which a control voltage is to be provided, the stabilization transistor containing a gate to be connected to a source of the output transistor, and a source to be connected to a drain of the output transistor, and having a gate-source voltage that is equal to or more than a dram-source voltage in a saturation region of the output transistor.

Abstract: An apparatus comprises a first circuit, a second circuit, a first transistor, a second transistor, a third transistor, a first programmable resistance, and a second programmable resistance. The first circuit may be configured to generate a reference signal and a bias signal in response to a supply voltage and a first input signal. The first circuit generally provides supply noise rejection to variations in the supply voltage. The second circuit may be connected to the first circuit and a ring oscillator. The first transistor may be connected to the first circuit and configured to set a first reference current of the first circuit based on the first input signal and the first programmable resistance. The second transistor may be connected in parallel with the first transistor. The second transistor is generally diode-connected.

Abstract: A voltage generation circuit may include: a first transistor coupled to an internal supply voltage terminal, and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to a first reference voltage generated based on an external supply voltage. The voltage generation circuit may limit a variation in level of a second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.

Abstract: A voltage reference circuit includes a first circuit block configured to generate a proportional to absolute temperature current, the first circuit block comprising a current mirror amplifier, a second circuit block coupled to the first circuit block and configured to generated a complimentary to absolute temperature current, and a third circuit block coupled to both the first circuit block and the second circuit block. The second circuit block includes a multi-stage common-source amplifier. The third circuit block is configured to combine the proportional to absolute temperature current and the complimentary to absolute temperature current to generate a reference voltage at an output of the voltage reference circuit.

Abstract: An electronic system comprising a voltage-to-current converter and a proportional-to-absolute-temperature (PTAT) circuit is disclosed. The voltage-to-current converter is configured to receive one of a control voltage, a supply voltage, a scaled-down version of the control voltage, and a scaled-down version of the supply voltage, and generate a set of currents. The PTAT circuit is coupled with the voltage-to-current converter such that each current of the set of currents is one of sourced to the PTAT circuit and sank from the PTAT circuit. Further, the PTAT circuit is configured to receive at least one of the supply voltage and the control voltage, and generate a set of reference voltages. The control voltage is generated based on the set of reference voltages and the supply voltage.

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

Abstract: A low power comparator circuit is provided. The circuit includes a comparator core including a first stage. The first stage has an output configured to provide a digital value. A capacitor includes a first terminal coupled at an input of the first stage and a second terminal selectively coupled to a first input and a second input of the comparator core. A voltage generator is coupled to the first stage. The voltage generator is configured and arranged to generate a first voltage based on a predetermined input current and to limit a maximum current of the first stage based on the predetermined input current.

Abstract: A noise component of a reference voltage is reduced in a circuit that generates a constant reference voltage that does not depend on a power supply voltage or a temperature. A reference voltage generation circuit includes a transistor, a first resistor, a diode, a second resistor, and a control unit. One of both ends of the transistor is connected to an output signal line. The first resistor is connected to another end of the transistor. Both ends of the second resistor are connected to one end of the diode and the output signal line. The control unit controls a potential of the another end of the transistor and a potential of the one end of the diode to the same potential.

Abstract: An ultra-low-power voltage reference generator in an integrated CMOS circuit includes a regular MOS transistor reference current source connected to a line voltage and a regular MOS transistor resistor between the regular MOS transistor reference current source and ground. A constant with temperature reference voltage VREF is generated from a terminal inter-connecting the regular MOS transistor reference current source and the regular MOS transistor resistor. An ultra-low-power current reference generator receives a reference voltage and generated ultra-low level current from the reference voltage with a temperature compensated gate-leakage array.

Abstract: Power consumption of a signal processing circuit is reduced. Further, power consumption of a semiconductor device including the signal processing circuit is reduced. The signal processing circuit includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, and first and second holding circuits. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier. Reference voltage from the reference voltage generation circuit and reference voltage from the voltage divider circuit can be held in the first and second holding circuits, respectively, so that the reference voltage generation circuit can stop operating. Thus, power consumption of the reference voltage generation circuit can be reduced.

Abstract: The present application discloses a circuit for providing a temperature-dependent common electrode voltage. The circuit includes a sensing sub-circuit coupled between a power-supply terminal and a ground terminal and configured to generate a first voltage for controlling a switching sub-circuit to connect the power-supply terminal to a first node. The circuit further includes a compensation sub-circuit coupled between the first node and the ground terminal and be enabled, when the first voltage decreases below a threshold as temperature increases above a threshold temperature, to output a temperature-dependent second voltage proportional to the temperature to a second node.

Abstract: Embodiments of the disclosure provide a bandgap reference circuit, including: first and second vertically stacked structures, the first and second vertically stacked structures each including: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET; and a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region.

Abstract: Voltage reference with temperature compensation. At least one example embodiment is a method of producing a compensate voltage reference, the method comprising: driving a reference current through a reference current path of a current mirror, and driving a mirror current through a mirror current path of the current mirror; driving the reference current through a first reference transistor having a control input, and driving the mirror current though a second reference transistor having a control input; equalizing the reference current flow through the first reference transistor to the mirror current flow through the second reference transistor by adjusting a control voltage on the control inputs of the first and second reference transistors; producing a reference voltage proportional to the control voltage; and compensating the reference voltage for temperature effects by adjusting a mirror ratio of the current mirror.

Abstract: A power converter includes: an inverter that includes an upper arm element and a lower arm element, and converts electric power supplied from a DC power source via a power wiring so as to supply the electric power to a load; a driver that receives electric power supplied from the DC power source via a control wiring, and applies gate voltage to the upper arm element and the lower arm element; and a controller that includes a drive controller controlling operation of the upper arm element and the lower arm element in accordance with a current command value.

Abstract: A voltage reference includes a flipped gate transistor configured to receive a first current. The voltage reference further includes a first transistor configured to receive a second current, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current, wherein the first leakage current is substantially equal to the second leakage current.

Abstract: A voltage reference circuit including a resistive track having a first force contact and a second force contact. The first and second force contacts configured to pass a current through the resistive track. A first sense contact, a second sense contact and a third sense contact are arranged at different positions along the resistive track between the first and second force contacts and the sense contacts are arranged to define a first resistor and a second resistor. A first component arrangement includes a P-N junction which has a temperature dependent voltage bias; a second component arrangement. One or both of the first component arrangement and the second component arrangement provide for a counter-bias voltage. The counter bias voltage counters the temperature dependent voltage bias of the P-N junction such that the voltage reference circuit provides a constant output reference voltage.

Abstract: A simulation method, simulation device and a readable storage medium are disclosed, in which a correction circuit is added to an equivalent circuit model for a three-terminal circuit employed in a SPICE simulation system. The correction circuit enables simulating behavior of the resistor module, enabling the SPICE simulation system to take in account the body effect. Therefore, simulation results obtained from the simulation model and simulation parameters for the resistor module can better reflect resistor behavior with body effect in an actual circuit, resulting in effectively improved simulation accuracy of the SPICE simulation system and allowing the system to provide more accurate circuit simulation results. Fitting tests can be performed to obtain first-order, second-order and resistor-width-dependent correction coefficients for a body voltage of the resistor module.

Abstract: A reference voltage generating circuit includes: an operational amplifier including a first input terminal connected to a first node and a second input terminal connected to a second node; a first transistor connected between a ground terminal and the first node, wherein a first current flows in the first transistor; a second transistor connected to the ground terminal; and a first variable resistor connected between the second transistor and the second node, wherein the first variable resistor has a first resistance value for adjusting the first current, based on a change in a current characteristic of the first transistor caused by a variation in a process of forming the first transistor. The reference voltage generating circuit provides a reference voltage, based on a voltage of the first node and a voltage across the first variable resistor.

Abstract: A level shifter circuitry is provided. The level shifter circuitry includes a first sub-circuit connected to a first power supply voltage, a second sub-circuit connected to a second power supply voltage and a shifting circuit which is connected to the first and second sub-circuits and outputs the first power supply voltage or the second power supply voltage to an output terminal or an inverted output terminal in response to a signal applied to an input node in accordance with an enable signal.

Abstract: An electronic circuit includes first to third transistors. The first transistor has a first channel width and a first channel length and generates a first potential difference by passing an operating current based on a first operating voltage. The second transistor has a second channel width and a second channel length and generates a second potential difference based on the operating current. The third transistor generates a third potential difference based on a second operating voltage and the operating current. A sum of a level of the first operating voltage and a level of the first potential difference corresponds to a sum of a level of the second operating voltage, a level of the second potential difference, and a level of the third potential difference. The first channel width is greater than the second channel width, or the first channel length is longer than the second channel length.

Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

Abstract: A correction current output circuit comprises a first voltage dividing circuit for generating a voltage in which an output voltage from a bandgap reference voltage circuit is divided in multiple stages, first and second correction circuits connected between a power supply and a ground, and a second voltage dividing circuit for dividing the above voltage in multiple stages in a path in which a positive temperature characteristic voltage is generated with the band gap reference voltage circuit. Current output terminals of a the second transistor of the first correction circuit and a first transistor of the second correction circuit are connected to a common connection point, and a current for correcting the temperature characteristic of a reference voltage generation circuit is output from the common connection point.

Abstract: A semiconductor circuit according to embodiments includes a circuit that includes the current source and generates the output voltage, and a voltage filter constituted by a depression-type NMOS transistor, the depression-type NMOS transistor having a source connected to a power supply side of the circuit, a gate that is grounded, and a drain to which a power supply voltage is applied. Thereby, a voltage on the power supply side of the circuit that has the current source and generates an output voltage is fixed regardless of an influence of a power supply fluctuation and suppresses a change in circuit characteristics.

Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.

Abstract: A manufacturing method of a semiconductor module including a trimming resistance element and a plurality of transistor chips connected mutually in parallel, in which gate electrodes are connected to one end of the trimming resistance element, including: measuring elapsed time and a gate-source voltage value when a predetermined gate current is injected into the gate electrodes and a predetermined drain current flow; calculating a gate-source capacity on the basis of the gate-source voltage value; determining a compensation gate resistance value on the basis of the gate-source voltage value and the gate-source capacity; and changing a resistance value of the trimming resistance element such that the resistance value of the trimming resistance element is conformed to the compensation gate resistance value.

Abstract: A frequency converter having a shunt resistor for emitter shunt current measurement includes a drivable switch, which is interconnected and driven in such a way that it prevents an undesired current flow via a bootstrap capacitor and the shunt resistor.

Abstract: Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.

Abstract: A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.

Abstract: A regulator circuit and its manufacturing method are presented, relating to semiconductor technology. The regulator circuit comprises a mirror current source comprising two current output nodes; a depletion MOS transistor comprising a drain connected to one current output node of the mirror current source, a gate connected to the ground, and a source; an enhancement MOS transistor comprising a drain connected to the other current output node of the mirror current source, and a source connected to the ground; a first resistance device comprising a first node connected to the drain of the depletion MOS transistor, and a second node connected to a gate of the enhancement MOS transistor; and a second resistance device comprising a first node connected to the first resistance device, and a second node connected to the ground. This regulator circuit consumes less power than its conventional counterparts.

Abstract: A voltage reference circuit serves to furnish a reference voltage for an application-specific integrated circuit. The voltage reference circuit includes a voltage input for applying an operating voltage; a ground terminal; a voltage output for furnishing a reference voltage; and a signal output for furnishing a power-on reset signal. The voltage reference circuit includes an IPTAT circuit, connected between the voltage input and ground terminal, for generating a current proportional to the absolute temperature, the voltage reference circuit being embodied to furnish the power-on reset signal only if the reference voltage has reached a target value and if additionally a current is flowing in the IPTAT circuit with a quantity of current that reaches or exceeds a minimum current intensity determined by a voltage value of the operating voltage and by a pull-down resistance value.

Abstract: A reference voltage generation circuit includes a supply voltage terminal, a node, a current source, an output terminal, a common voltage terminal, a bandgap reference circuit and a feedback circuit. The supply voltage terminal is used to provide a supply voltage. The current source is coupled between the supply voltage terminal and the node, and used to receive the supply voltage and generate a current according to a feedback signal, and output the current to establish at the node a first voltage substantially insensitive to the supply voltage. The common voltage terminal is used to provide a common voltage. The bandgap reference circuit is coupled between the node and the common voltage terminal, and used to establish a temperature-invariant bandgap voltage at the output terminal. The feedback circuit is coupled to the node and the current source, and used to generate the feedback signal according to the first voltage.

Abstract: An electrical device includes a power supply circuit configured to provide a first voltage and a second voltage, and a first verification circuit configured to derive a first and a second internal voltage from the first voltage, to compare the first and second internal voltages, and to generate a first output signal based on the comparison. The electrical device includes a second verification circuit including a first input terminal for the first voltage and a second input terminal for the second voltage, and configured to compare the first and second voltages and to generate a second output signal based on the comparison. Furthermore, the electrical device includes a combination circuit configured to generate a third output signal if the first output signal or the second output signal is indicative of the first voltage or the second voltage being outside a tolerance range.

Abstract: A reference voltage generation circuit of the invention includes: PMOS transistors P1 and P2 configured to provide current sources with same current to a first current path and a second current path; a bipolar transistor Q1 connected to the PMOS transistors P1 on the first current path; a bipolar transistor Q2 connected to the PMOS transistors P2 on the second current path; a differential amplifier AMP controlling the gates of the PMOS transistors P1 and P2, such that a voltage of a node VN and a voltage of a node VP are equal; an output node BGR outputting a reference voltage Vref; and a reference voltage guarantee portion 130 outputting a detecting signal BGRDET when a differences between the voltage of the node VN and the voltage of the node VP is maintained below a determined value.

Abstract: The present disclosure provides bandgap reference circuits having multi-level chopping actions to current mirror circuits for the purpose of reducing the flicker noise of the output reference voltage. A bandgap reference circuit includes a first current mirror including a pair of a first MOSFET and a second MOSFET, a second current mirror comprising a third MOSFET electrically connected to the first current mirror, and configured to provide a reference voltage at a drain, a first bipolar junction transistor electrically connected to the first current mirror, a second bipolar junction transistor connected to the first current mirror via a first resistor, a third bipolar junction transistor connected to the third MOSFET via a second resistor. The bandgap reference circuit further includes an operational amplifier to control the MOSFETs and a plurality of chopping switches configured to perform chopping actions on outputs of the first current mirror and the second current mirror.

Abstract: An apparatus includes a first switching device and a second switching device connected in series between a first node and a second node, a first voltage blocking device and a second voltage blocking device connected in series between the first node and a third node, a flying capacitor connected between a common node of the first switching device and the second switching device, and a common node of the first voltage blocking device and the second voltage blocking device, and a controller configured to adjust power losses in the first switching device and the second switching device through controlling charge and discharge processes of the flying capacitor.

Abstract: An integrated circuit is provided with a bandgap voltage reference circuit having a bandgap reference voltage output. A bandgap failure detection circuit is coupled to the bandgap reference voltage output. The bandgap failure detection forms a model value of the reference voltage from a first time, compares a present value of the reference voltage at a second time to the model value; and asserts a bandgap fail signal to indicate when the present value is less than the model value by a threshold value. The integrated circuit is reset by the bandgap fail signal. The detection circuit may be operated from a failsafe voltage domain that also allows a critical circuit to complete a pending operation during a reset.

Abstract: A bandgap reference circuit and a method for providing a reference voltage are disclosed. In an embodiment a bandgap reference circuit includes a voltage generator including a first branch and a second branch and being configured to produce a reference voltage with a temperature coefficient lower than a given threshold, a supply circuit configured to provide a first current to the first branch and a second current to the second branch, and a control loop including a transconductance amplifier configured to provide an output signal representative of a difference between a first voltage of the first branch and a second voltage of the second branch and a filter coupled to an output of the transconductance amplifier, the filter configured to provide an output signal for controlling the first current and second current of the supply circuit.

Abstract: A bandgap reference circuit is applied to the wide range supply voltage. When a power supply voltage is changed, the change amount of the bandgap voltage generated by the bandgap reference circuit is very low. The bandgap reference circuit includes a mirroring circuit, an input circuit and an operation amplifier. The mirroring circuit generates a first current, a second current and a third current to a first node, a second node and an output voltage of the bandgap reference circuit. The input circuit is connected with the first node to receive the first current and connected with the second node to receive the second current. A positive input terminal of the operation amplifier is connected with the first node. A negative input terminal of the operation amplifier is connected with the second node. An output terminal of the operation amplifier is connected with the mirroring circuit.

Abstract: An electronic device comprises a regulator, and an oscillator and a resistor coupled to the regulator. The electronic device further comprises a feedback controller that includes a differential amplifier coupled between the oscillator, the resistor, and the regulator. The feedback controller is configured to apply a control voltage to the regulator in response to a resistor voltage upon the resistor and an oscillator voltage upon the oscillator. The feedback controller can be coupled to control a substantially equal voltage upon the resistor and the oscillator.

Abstract: Methods, systems, and apparatus to facilitate current sensing for valley current-controlled power converters are disclosed. An example apparatus includes a comparator including a first terminal, a second terminal, and an output. The apparatus further includes a first transistor including a first drain coupled to the first terminal of the comparator. The apparatus further includes a second transistor including a second drain coupled to the first terminal of the comparator. The apparatus further includes a third transistor including a third drain coupled to the second terminal of the comparator.

Abstract: A low voltage bandgap reference circuit (200) is provided which includes a first current generator (202) having first and second circuit branches which include, respectively, first and second bipolar transistors having different sizing reference values for generating a first current at a first resistor that varies proportionally as a function of temperature; a second current generator (204, 205) having a third circuit branch which includes one or more field effect transistors and no bipolar transistors for generating a second current that varies inversely as a function of temperature; and a third circuit (206) connected to generate a bandgap reference current in response to the first current and the second current.

Abstract: The present disclosure discloses a bandgap reference power generation circuit and an integrated circuit. The bandgap reference power generation circuit includes a bias circuit and a bandgap reference core circuit. The bias circuit is configured to provide starting current according to a bias voltage. The bandgap reference core circuit is connected to the bias circuit to receive the starting current and goes into a stable operating state according to the starting current to output a preset voltage or preset current. The integrated circuit includes the bandgap reference power generation circuit. By the aforementioned method, the present disclosure can simplify a circuit design and reduce power consumption.

Abstract: A system for coupling a modulated voltage signal onto a current loop between a host device and a field device, in various embodiments, can include a circuit and an impedance bridge. The circuit is configured to flow current from the field device between two terminals of an input circuit in the host device, wherein the two terminals are included in the current loop. The impedance bridge is positioned between the two terminals and configured to modulate impedance to convert the current in a field loop produced by the field device into terminal voltage modulation, without introducing a DC voltage burden to the current.