Abstract: This document discusses, among other things, apparatus and methods for an edge rate driver for a power converter switch. In an example, the driver can include an input node configured to receive a pulse width modulated signal, a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state, a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state, and a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch.

Abstract: An apparatus and a method for recognizing an error in a power bridge circuit containing a load, a high-side branch and a low-side branch. Accordingly, a first switched current source is connected to the load and to a diagnosis connection for a high-potential of a diagnosis voltage, a second switched current source is connected to the load and to a diagnosis connection for a low-potential of the diagnosis voltage, and a control device for controlling the first switched current source and the second switched current source. The control device switches on one of the switched current sources when the high-side power switch and the low-side power switch are open, while the other switched current source is switched off. A testing device tests a voltage at the load when one of the switched current sources is switched on and the other of the switched current sources is switched off.

Abstract: A DC-DC converter converts an input voltage input from an input terminal to a predetermined voltage and outputs the converted voltage from an output terminal, the DC-DC converter including an output control transistor and an operation control circuit that has an error amplifying circuit, whereby the error amplifying circuit includes an output circuit configured to output an error voltage and include an output transistor of a source follower connection, a series circuit configured to include a resistor for phase compensation and a capacitor for phase compensation and be connected between a control electrode of the output circuit and a grounding voltage terminal, and an amplifying circuit configured to be positioned on a side more distant from a side outputting the error voltage relative to the output circuit in the error amplifying circuit, and include a voltage generating element as a load of the amplifying circuit.

Abstract: A current mirror circuit having formed in a semiconductor: a pair of transistors arranged to produce an output current through an output one of the transistors proportional to a reference current fed to an input one of the pair of transistors; a resistor comprising a pair of spaced electrodes in ohmic contact with the semiconductor, one of such pair of electrodes of the resistor being coupled to the input one of the pair of transistors; and circuitry for producing a voltage across the pair of electrodes of the resistor, such circuitry placing the resistor into saturation producing current through a region in the semiconductor between the pair of spaced ohmic contacts, such produced current being fed to the input one of the transistors as the reference current for the current mirror.

Abstract: A system including a first transistor, a second transistor, and a comparator. The first transistor is configured to supply a first current to a first load connected to a first terminal of the first transistor. The second transistor is configured to supply a second current to a second load connected to a first terminal of the second transistor, wherein the first current and the second current have a predetermined ratio. The comparator is configured to compare a voltage at the first terminal of the first transistor or a voltage at the first terminal of the second transistor to a reference voltage, and to adjust, based on the comparison, biasing of the first transistor and the second transistor to maintain the predetermined ratio between the first current and the second current.

Abstract: A signal level detector and detecting method are provided. In one implementation a method includes receiving a differential input signal; incorporating two configurable rectifiers of the same circuit topology; configuring a first one of the two configurable rectifiers as a inverting rectifier to generate an inverting end of an output signal in response to an absolute value of the differential input signal; and configuring a second one of the two configurable rectifiers as a non-inverting rectifier to generate a non-inverting end of the output signal.

Abstract: A current mirror circuit includes an input portion configured to conduct a bias current, and a first current source circuit coupled to the input portion and configured to generate the bias current, and vary the bias current over a range of currents based on a first group of weightings associated therewith. The current mirror circuit also includes an output portion configured to conduct an operational current, wherein the output portion is coupled to the input portion, and a second current source circuit coupled to the output portion and configured to generate the operational current, and vary the operational current over a range of currents based on a second group of weightings associated therewith. The first group of weightings and the second group of weightings are different.

Abstract: A reference current source circuit includes a reference voltage generating module, a voltage buffer, an equivalent resistance, a filter capacitor, a current mirror module and a reference current outputting terminal. The voltage buffer includes an operational amplifier and a first FET. The current mirror module includes a second FET and a third FET. The equivalent resistor includes an oscillator, a fourth FET, a fifth FET and a capacitor connected to the fourth FET and the fifth FET. The oscillator is for generating a clock signal whose frequency is related to a charging and discharging capacitor in the oscillator to control charging and discharging of the capacitor in the equivalent resistance. The reference current outputting terminal is for outputting a reference current only related to a capacitance ratio of the capacitor to the charging and discharging capacitor. A reference current source system is further disclosed.

Abstract: A method for generating a reference voltage includes generating a proportional-to-absolute temperature (PTAT) voltage across a first pseudo resistor. The first pseudo resistor includes a transistor. The method also includes converting the PTAT voltage to a current based on a resistance of the first pseudo resistor. The method also includes mirroring the current using a current mirror circuit and converting the mirrored current to a converted PTAT voltage using a second pseudo resistor. The second pseudo resistor includes a transistor. The first pseudo resistor and the second pseudo resistor include equal transistor types. The method also includes generating a complementary-to-absolute temperature (CTAT) voltage, and summing the converted PTAT voltage and the CTAT voltage to produce the reference voltage. The resulting reference voltage is temperature independent.

Abstract: A fixed voltage generating circuit includes a current mirror, a differential pair, and a resistor coupled to the current mirror. A node of the resistor is coupled to a voltage source. The differential pair includes two resistors coupled to the voltage source to enable the differential pair outputting a stable output voltage.

Abstract: In one embodiment, a method includes generating a drive current. Generation of the drive current results in a first leakage current, and the drive current and first leakage current each flow into a first node. The method also includes generating a second leakage current and amplifying the second leakage current to generate a leakage-compensation current. The leakage-compensation current flows away from the first node.

Abstract: The present invention provides a current balancing circuit and method for balancing the respective currents in a plurality of parallel circuit branches in a target circuit. The current balancing circuit including: a plurality of balancing transistors, each having a collector, an emitter, and a base, the collector and emitter of each balancing transistor connected in series with a respective circuit branch; and a selection circuit for selectively connecting the circuit branch having the smallest current amongst the circuit branches to the bases of each balancing transistor.

Abstract: Current circuits, circuits configured to provide a bias voltage, and methods for providing a bias voltage are described, including a current circuit configured to receive a reference current and having an output at which an output current is provided. One such current circuit includes a first current mirror configured to receive a first portion of the reference current and further configured to mirror the first portion of the reference current to provide a first current. The current circuit further includes a second current mirror configured to receive a second portion of the reference current and receive the first current. The second current mirror is further configured to provide a portion of the first current to the output of the current circuit as the output current and to receive another portion of the first current and mirror the same as the second portion of the reference current.

Abstract: A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage. The noise cancelling circuit includes an auxiliary current path which branches from the load current path. The length-to-width ratios of transistors of the circuit are selected to provide the desired noise cancellation while maintaining device stability.

Abstract: Various apparatuses and methods for supplying an electrical current are disclosed herein. For example, some embodiments provide an apparatus including a current regulation switch connected in a current path between a power input and a current output. A current regulator is connected to the current regulation switch. The current regulator includes a current set terminal, and the current through the current regulation switch is proportional to the current through current set terminal. An impedance monitor is connected to the current set terminal.

Abstract: A transistor includes a source region, a drain region, a channel region, a gate electrode and a layer of a stress-creating material. The stress-creating material provides a stress that is variable in response to a signal acting on the stress-creating material. The layer of stress-creating material is arranged to provide a stress in at least the channel region. The stress provided in at least the channel region is variable in response to the signal acting on the stress-creating material. Layers of stress-creating material providing a stress that is variable in response to a signal acting on the stress-creating material may also be used in circuit elements other than transistors, for example, resistors.

Abstract: A circuit for controlling a switch in a power converter in which peak current is regulated to achieve a specified average current through a load. The circuit can include a first input to receive a voltage corresponding to a pre-specified target average current through the load, and a second input to receive a voltage corresponding to a voltage across a sensing resistor immediately after the switch turns ON. The circuit generates a threshold value that is approximately equal to twice the voltage corresponding to the pre-specified target average current through the load, minus the voltage corresponding to a non-zero voltage across the sensing resistor just after the switch turns ON. Control logic is operable to monitor a voltage across the sensing resistor such that when the voltage across the sensing resistor reaches or exceeds the threshold value, the control logic generates a signal that causes the switch to be turned OFF.

Abstract: An output setting device of a constant current circuit includes a reference current generation circuit and first to fourth current mirror circuit groups. The reference current generation circuit feeds a reference current. Each current mirror circuit group includes at least one current mirror circuit that feeds a current proportional to the reference current. One current mirror circuit group or two or more current mirror circuit groups connected in parallel to each other among the plurality of current mirror circuit groups are connected to a load to set a current to be supplied to the load.

Abstract: A reference quantity generator for generating a reference quantity includes a reference source configured to provide a reference source signal, a digitally controlled signal source and a digital controller. The digitally controlled signal source is configured to provide a digitally controlled quantity. The reference quantity is determined based on the digitally controlled quantity. The digital controller is configured to provide a digital control signal to control the digitally controlled signal source to adapt the digitally controlled quantity based on the reference source signal using a feedback.

Abstract: The voltage reference circuit includes: a first MOS transistor; a second MOS transistor including a gate terminal connected to a gate terminal of the first MOS transistor and having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value and a K value of the first MOS transistor; a current mirror circuit flowing a current based on a difference between the absolute values of the threshold values of the first MOS transistor and the second MOS transistor; a third MOS transistor flowing the current; and a fourth MOS transistor having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value of the third MOS transistor and flowing the current.

Abstract: A linear voltage regulator includes a Miller frequency compensation having a movable zero, which tracks the frequency of the load pole as the load condition changes. The compensated voltage regulator maintains stability under variable load conditions. Because of the Miller effect, DC open-loop gain and bandwidth are not sacrificed for stability. The compensated voltage regulator can therefore maintain high power supply rejection ratio (PSRR).

Abstract: A voltage regulator includes a master circuit, first and second filters, and a slave circuit. The master circuit provides a second reference voltage based on a first reference voltage and a supply voltage. The first filter provides a filtered second reference voltage based on the second reference voltage. The second filter provides a filtered supply voltage based on the supply voltage. The slave circuit provides a third reference voltage based on the filtered second reference voltage and the filtered supply voltage. The second filter includes an NMOS transistor and a capacitor. The gate and the drain of the NMOS transistor receive the supply voltage. A first terminal of the capacitor is electrically coupled to a source of the NMOS transistor. A second terminal of the capacitor is electrically coupled to ground. The source of the NMOS transistor provides the filtered supply voltage.

Abstract: A reference voltage generation circuit includes: a bandgap reference circuit, generating a plurality of initial currents with different temperature coefficients; a base voltage generation circuit, combining the initial current into a combined current, and converting the combined current into one or more base voltages; a bias current source circuit, generating one or more bias currents based on at least one of the initial currents; and one or more regulating output circuit, each converting a respective one of the one or more bias currents into an increment voltage and adding the increment voltage to the base voltage to generate a respective output voltage. Each output voltage may have its respective temperature coefficient.

Abstract: A distribution current is split into a first control current, a second control current, and a third control current, in an apportionment according to a distribution command. A first control voltage is generated in response to the third control current. A second control voltage is generated as indication of the first control current, and a third control voltage is generated as indication of the second control current. Optionally, de-emphasis contribution of a first driver, a second driver and a third driver to an output is controlled based, at least in part, on the first control voltage, the second control voltage and the third control voltage, respectively.

Abstract: One embodiment provides a reference current generation circuit. The circuit has first and second reference current generation circuits for generating first and second reference currents respectively, and a current output circuit for outputting a third reference current by adding the first and second reference currents. The first reference current generation circuit includes first and second current-voltage conversion circuits and a first current supply circuit. The first current supply circuit provides substantially equal amounts of current to the first and second current-voltage conversion circuits respectively. The second reference current generation circuit includes third to fifth current-voltage conversion circuits and a second current supply circuit.

Abstract: A current mirror circuit having formed in a semiconductor: a pair of transistors arranged to produce an output current through an output one of the transistors proportional to a reference current fed to an input one of the pair of transistors; a resistor comprising a pair of spaced electrodes in ohmic contact with the semiconductor, one of such pair of electrodes of the resistor being coupled to the input one of the pair of transistors; and circuitry for producing a voltage across the pair of electrodes of the resistor, such circuitry placing the resistor into saturation producing current through a region in the semiconductor between the pair of spaced ohmic contacts, such produced current being fed to the input one of the transistors as the reference current for the current mirror.

Abstract: A circuit arrangement for measuring a load current provided to a load via a first load terminal of a load transistor is disclosed. In accordance with one example of the invention, the circuit arrangement includes a sense transistor coupled to the load transistor to provide a sense current representing the load current at a first load terminal of the sense transistor. The first load terminals of the load and the sense transistors are at respective floating electric potentials. A floating sense circuit coupled between the load terminals of sense transistor and load transistor, at least in one mode of operation the sense circuit receives the sense current and provides a floating signal representing the sense current. A non-floating measurement circuit is coupled to the sense circuit via a DC decoupling capacitor for transferring the floating signal representing the sense current to the non-floating measurement circuit.

Abstract: A current generating circuit may include a first current source configured to generate a first current having positive temperature characteristics; a second current source configured to generate a second current; a compensation transistor configured as an NPN bipolar transistor, and arranged such that the second current flows through from its collector and its emitter; and a first current mirror circuit configured to multiply a base current of the compensation transistor by a first coefficient so as to generate a third current. The current generating circuit may be configured to output a fourth current that is proportional to the difference between the first current and the third current.

Abstract: A low noise current buffer circuit includes a first transistor, for receiving an input current, a second transistor, for draining a first current from a drain of the second transistor according to the input current received by the first transistor, a third transistor, for outputting first current, a fourth transistor, for outputting a second current to an output resistor, to generate an output voltage, and a feedback capacitor, for eliminating impacts of noise of a system voltage on the output voltage.

Abstract: A constant current generating circuit and constant current generating method applied to a chip are provided, where the chip includes a first current generating circuit and a second current generating circuit, the second current generating circuit includes a transistor and an adjustable resistor. The constant current generating method includes: connecting an external resistor to the first current generating circuit to make the first current generating circuit use the external resistor to generate a first current; utilizing the second current generating circuit to generate a second current; adjusting the adjustable resistor in accordance with the first current and the second current to make the second current substantially equal to the first current, where the second current serves as a constant current of the chip.

Abstract: A circuit exhibiting rectification and amplification characteristics. In particular, a full-wave rectifier, wherein the rectifier has the ability to simultaneously amplify and rectify an input voltage. The circuit comprises transconductor circuit, rectifying circuit and amplifying circuit. The transconductor circuit is adapted for receiving an input voltage from at least one voltage source. The input voltage is then converted into intermediate currents by the transconductor circuit. Thereafter, the rectifying circuit rectifies the intermediate currents current to produce a rectified current. Lastly, the amplification circuit amplifies the input voltage to produce the amplified voltage.

Abstract: Systems and methods for managing process and temperature variations for on-chip sense resistors are disclosed. The system includes a circuit that can leverage a linear gm circuit in order to provide linear gains (positive gains and/or negative gains). The linearity of the circuit enables compensation for temperature and process variations across an entire range of current (positive to negative). A control signal is generated by using a linear gm amplifier and a replica resistor, which is substantially similar to the on chip resistor. The control signal is used to control the gain of a disparate linear gm amplifier within a compensation circuit, which provides an offset voltage to compensate for the variation in resistance of the on chip resistor.

Abstract: A current source includes a first MOS transistor of a first channel type including a drain connected to an output terminal, and a source directly connected to a first power supply, a second MOS transistor of the first channel type including a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first transistor, and a source directly connected to the first power supply, a third MOS transistor of a second channel type opposite the first channel type including a drain connected to the drain of the second MOS transistor, a fourth MOS transistor of the second channel type including a drain connected to the source of the third MOS transistor, a gate connected to a first bias voltage, and a source directly connected to second power supply voltage, and a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor.

Abstract: Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a voltage distribution line. Examples of counter coupling capacitances which may be coupled to the gate nodes of sense amplifier transistors are also described.

Abstract: Interface circuitry of a storage device or other type of processing device comprises at least one data path, and an adaptive power supply configured to provide a variable supply voltage to the data path. The adaptive power supply comprises a reference voltage circuit having a plurality of field effect transistors collectively configured to provide a variable reference voltage, with different ones of the field effect transistors being biased into different operating regions. For example, a first subset of the field effect transistors may each be biased into a linear region such that the variable reference voltage tracks variations in on-resistance of one or more corresponding field effect transistors of the data path, and a second subset of the field effect transistors may each be biased into a saturation region such that the variable reference voltage tracks variations in threshold voltage of the corresponding field effect transistors of the data path.

Abstract: A constant-voltage power supply circuit includes a first transistor connected between a power supply terminal and an output terminal. The constant-voltage power supply circuit includes a voltage divider circuit including a first resistor having a first end connected to the output terminal and a second resistor having a first end connected to a second end of the first resistor and a second end connected to ground. The constant-voltage power supply circuit includes an output voltage control amplifier that compares the divided voltage and a reference voltage and controls a voltage of a control terminal of the first transistor. The constant-voltage power supply circuit includes a current-limiting characteristic control circuit that controls the voltage of the control terminal of the first transistor according to the divided voltage and an output current.

Abstract: A semiconductor integrated circuit includes a current mirror having a predetermined input-output ratio and including a first transistor configured to receive an input current and a second transistor configured to output an output current, and an output transistor configured to generate a reference voltage according to the output current of the current mirror. The value of the output current is greater than the value of the input current, and the total area of one or more collector regions of the first transistor is substantially the same as the total area of one or more collector regions of the second transistor.

Abstract: A reference circuit for an oscillator module is provided. The reference circuit includes a reference voltage generation unit and a reference current generation unit. The reference voltage generation unit includes an electric element having a voltage proportional to absolute temperature (PTAT voltage) and provides a reference voltage based on the PTAT voltage. The reference current generation unit is coupled to the reference voltage generation unit and provides a reference current to the oscillator circuit to serve as an input current based on the PTAT voltage. The oscillator circuit generates a clock signal based on the reference voltage and the input current. The reference voltage and the input current are proportional to absolute temperature and have the same change trend relative to absolute temperature, such that the clock signal is a temperature insensitive signal. An oscillator module including an oscillator circuit and the foregoing reference circuit is also provided.

Abstract: A small power semiconductor device current detector circuit and detection method with low loss by detecting current using the sensing function of a power semiconductor device is disclosed. An already known current is caused to flow through a main region of the power semiconductor device. The current is detected by a current detector unit connected to a sense terminal of the power semiconductor device. A deviation in characteristics between the main region and a sensing region is detected by a variable voltage source circuit based on the detected current. An offset amount and gain amount in an output regulator are regulated in such a way that the characteristics of the two coincide. The offset amount and gain amount to be regulated may be supplied to the output regulator, serially or in parallel, from a CPU provided externally.

Abstract: A multi-hysteresis voltage controlled current source system having a variety of multi-hysteresis characteristics is provided. In the multi-hysteresis voltage controlled current source system, single-hysteresis voltage controlled current source circuits 21, 22, . . . 2N as fundamental components are connected in parallel, and a differential input voltage vid is applied to the single-hysteresis voltage controlled current source circuits 21, 22, . . . 2N, so that a plurality of discrete values of current can be output based on the single-hysteresis voltage controlled current source circuits 21, 22, . . . 2N.

Abstract: A constant current source circuit is constituted of a control voltage generation section which detects the output voltage at the output terminal so as to generate a control voltage, a reference current adjustment section which adjust a reference current based on the control voltage, and a current mirror section which outputs the output current responsive to the adjusted reference current at the output terminal. This reduces variations of the output current due to variations of the output voltage; hence, the constant current source circuit can precisely operate in a low-voltage region.

Abstract: A regulator for providing a low dropout voltage at an output node of the regulator is provided. An amplifier has a non-inverting input terminal for receiving an input voltage, an inverting input terminal and an output terminal. A first resistor is coupled between a ground and the inverting input terminal of the amplifier. A second resistor is coupled to the inverting input terminal of the amplifier. A first transistor is coupled between a voltage source and the second resistor. A current source coupled between the voltage source and a gate of the first transistor provides a bias current. A second transistor coupled between the first transistor and a current mirror has a gate coupled to the output terminal of the amplifier. The first and second transistors are different type MOS transistors. The replica unit generates the low dropout voltage according to a voltage of the output terminal of the amplifier.

Abstract: A circuit for sensing load current of a voltage regulator. The circuit includes a power transistor and a mirror transistor. A first transistor sizing circuit is coupled to the power transistor and is operable to control size of the power transistor based on a bias voltage of the power transistor, thereby regulating a first voltage for varying load conditions. The circuit also includes a feedback amplifier coupled to the power transistor and the mirror transistor. A transistor is coupled to the feedback amplifier and the mirror transistor. An analog to digital converter (ADC) is coupled to the transistor. A second transistor sizing circuit is coupled to the mirror transistor, the transistor, and the ADC. The second transistor sizing circuit is responsive to an output voltage to control size of the mirror transistor, thereby ensuring that accuracy of output voltage sensed by ADC is not limited by ADC's resolution.

Abstract: A differential current source includes two source transistors, sources of which are respectively connected to a power source, and a mixer circuit having a first terminal, a second terminal, a third terminal and a fourth terminal, the first terminal and the second terminal being respectively connected to drains of the two source transistors, and the third terminal and the fourth terminal being respectively output terminals, wherein the mixer circuit changes a connection state in accordance with a local signal between a first connection state where the first terminal and the third terminal are connected and also the second terminal and the fourth terminal are connected, and a second connection state where the first terminal and the fourth terminal are connected and also the second terminal and the third terminal are connected.

Abstract: A regulator control circuit includes a high side driver that is configured to receive a supply voltage. A capacitor is configured to store charges. A first transistor is coupled between the capacitor at a first node and a gate of a high side driver at a second node. The first node is capable of being boosted to a voltage to operate the first transistor at a saturation mode for a charge sharing between the first node and the second node so as to substantially turn on the high side driver.

Abstract: A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.

Abstract: A host electronic device may be coupled to an accessory electronic device. During normal operation, the host device may supply the accessory device with power over a power supply line. Back-powering events in which the accessory device delivers power to the host device may be prevented by interposing a protection transistor in the power supply line. A current mirror may be formed using the protection transistor and an additional transistor that produces a sense current proportional to the amount of current that is flowing through the power supply line. A current-to-voltage amplifier may produce a sense voltage that is proportional to the sense current. A bias circuit may be used to bias the sense current through the current mirror. A control circuit may compare the sense voltage to one or more reference voltages and turn off the protection transistor when appropriate to prevent back-powering of the host device.

Abstract: A system and a method are disclosed for using driving capacitors to dynamically bias an amplifier in a stage of a pipeline analog-to-digital converter (ADC). The drain of the amplifier is connected to a sink transistor, and the driving capacitors are used to raise or lower the voltage at the gate of the sink transistor. The driving capacitors can be used in this manner to rapidly power the amplifier on and off to save power and/or to selectively boost the drain current of the amplifier to improve the response time of the pipeline ADC stage.

Abstract: The high-side switch circuit includes a first output MOS transistor that is connected, at a first end thereof, to a power supply terminal. The high-side switch circuit includes a second output MOS transistor that is connected to a second end of the first output MOS transistor at a first end thereof and to a voltage output terminal at a second end thereof. The high-side switch circuit includes a current detecting circuit that detects a current flowing through the first output MOS transistor and outputs a detection signal. The high-side switch circuit includes a first gate driver that applies a first control voltage to a gate of the first output MOS transistor. The high-side switch circuit includes a second gate driver that applies a second control voltage to a gate of the second output MOS transistor.

Abstract: A system and method for calibrating bias in a data transmission system including a calibrated bias having impedance calibration for accommodating parameter variations in the data transmission system. A current mirror receives and balances bias currents between the calibrated bias and an output driver from the data transmission system. A digital compensation logic circuit is connected to the calibrated bias to adjust the calibrated bias for variations in parameters causing a current tail effect. A calibration logic circuit adjusts calibration due to variations in operational parameters, such that the tail current variations are minimized.