Abstract: A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.

Abstract: The present invention provides a method and a fault isolation system for detecting errors in an integrated circuit. One feature of the present invention is using a movable second probe to scan and acquire an output signal through the vias or metal line structure of a diagnostic area along a detecting line, so as to find the fault location precisely, and another feature of the present invention is using a cutter in conjunction with the above method to narrow down the fault range. The cutter is used to electrically isolate the portion of diagnostic area step by step for approaching the fault location. This method can help to save a lot of analysis time and also makes the minor fault localization possible.

Abstract: A probe head and methods of testing a device using a probe head are provided. The probe head includes a first end connected to a first substrate. The first substrate is configured to be connected to a test head. The probe head also includes second end having a first inner recess surrounded by a first protrusion and a first plurality of probe needles connected to the first protrusion.

Abstract: Terminals (2, 502) of a device under test (DUT) are connected to corresponding contact pads or leads by a series of electrically conductive contacts. Each terminal testing connects with both a “force” contact and a “sense” contact. In one embodiment, the sense contact (770) partially or completely laterally surrounds the force contact (700). In order to increase the contact surface, the force contact, in a spring pin (700) configuration contacts the device under test terminal at that portion of the lead which is curved or angled, rather than orthogonal to the pin.

Abstract: A contact device for an electric contact for electrically testing an electric test object, comprising a contact head and at least one printed circuit board. The contact head has a plurality of guide bores in which elongated contact elements that buckle elastically in a lateral direction upon contacting the test object are mounted in a longitudinally movable manner. One end of the contact element is used to contact the test object and the other end is in contact with first contact surfaces which are arranged in a specified pattern and which are located on a face of the printed circuit board in a first, central region of the printed circuit board face. Second contact surfaces are arranged in a further specified pattern, are electrically connected to the first contact surfaces through the printed circuit board, and lie on the other face of the printed circuit board in a second, central region of the printed circuit board face.

Abstract: An integrated circuit includes a first power unit, a second power unit, and a selection switch. The first power unit generates a first output voltage and is coupled to a first load pin. The first load pin is coupled to a first load. The second power unit generates a second output voltage and is coupled to a second load pin. The second load pin is coupled to a second load. The selection switch outputs either the first output voltage or the second output voltage to a voltage pin according to a selection signal.

Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips, which includes forming routing structure(s) that facilitate process limiting yield (PLY) testing of test devices. A routing structure includes an array of link-up regions and a set of metal pads surrounding that array. Each link-up region includes two sections, each having two nodes electrically connected to the terminals of a corresponding two-terminal test device. During PLY testing with a probe card, electrical connections between the test devices and the metal pads through the link-up regions allow each test device to be tested individually. Optionally, additional routing structures with the same footprint are formed down the line and stacked one above the other. These additional routing structures are used for PLY testing with the same probe card. Optionally, dummy pads are formed between stacked routing structures to improve robustness. Also disclosed is a semiconductor structure formed according to this method.

Abstract: A probe card which is capable of transmitting high-frequency signals provided by a DUT, and the DUT includes an output pin group and an input pin group for sending and receiving the high-frequency signals respectively. The probe card includes a first signal pin group, a second signal pin group, and a band circuit. The first signal pin group is made of a conductive material, and is used to contact the output pin group; the second signal pin group is made of a conductive material too, and is used to contact the input pin group; the band circuit is electrically connected to the first signal pin group and the second signal pin group to allow signals within a first bandwidth and a second bandwidth to pass therethrough.

Abstract: An example test system includes: multiple channels, where each of the multiple channels is configured to force voltage and to source current; and circuitry to combine current sourced by the multiple channels to produce a combined current for output on a single channel to a device under test (DUT), where each of the multiple channels includes a load sharing resistor to control a contribution of the channel to the combined current.

Abstract: Coupling an electrical connector to a printed circuit board (PCB) involves disposing forms of conductive bonding agent on the PCB, pressing spring-loaded power pins of an electrical connector towards a surface of the PCB, heating the forms of conductive bonding agent, thereby at least partially melting the forms, pressing the spring-loaded power pins into the melted forms of conductive bonding agent, and holding the power pins in the forms until the forms have cooled enough to form a bond that holds the power pins, thereby forming an electrical connection between the one or more pins and the PCB. The spring-loaded power pins are configured to automatically lift away from the surface of the PCB when the bond is weakened.

Abstract: Systems and methods for magnetic coupling. One system includes an external computing device and a connector having a conductive end. The system also includes a printed circuit board. The printed circuit board includes a connector side opposite a back side. The connector side has a contact pad with an aperture. The printed circuit board also includes a magnet positioned on the back side of the printed circuit board. The magnet provides a magnetic field configured to provide magnetic attraction forces to a connector contacting the contact pad. The printed circuit board also includes a communication terminal. The system also includes a circuit in communication with the printed circuit board through the connector and contact pad.

Abstract: A probe assembly can be connected and disconnected from its electrical harness within a vacuum chamber so that the probe assembly with the work piece mounted can be rotated and tilted without interference from a cable, and can then be reconnected without opening the vacuum chamber. Also described is a means of grounding a sample and probes when the probe assembly is disconnected from its electrical harness and a means of preventing damage to the probe mechanism and the probe itself by ensuring that the probes are not sticking up too far during operations.

Abstract: A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (tf) of 100 ns or less and a pulse amplitude (If) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (ts) of 100 ns or less and a pulse amplitude (Is) equal to or larger than the forming current pulse amplitude (If).

Abstract: To test a probe card with an examination apparatus that tests a device under test, provided is a test system that tests a device under test and includes a test section that includes a plurality of test units that input or output a signal; a probe card that includes a plurality of probe terminals connected to a terminal of the device under test, and transmits signals between the device under test and the test section; and a wafer for testing that is connected to the probe card, instead of the device under test, when testing the probe card, and includes a connection wire that electrically connects two of the probe terminals to each other. The test section measures output of at least one of two test units connected to the two probe terminals, and judges pass/fail of the two probe terminals.

Abstract: A structure and a method for obtaining capacitance in an array substrate are disclosed. The structure comprises a first conductive region, arranged in a same layer as a first conductive layer of said array substrate; a second conductive region, arranged in a same layer as a second conductive layer of said array substrate, wherein said second conductive region overlaps with said first conductive region partly or totally; a first measurement region, connected with said first conductive region; and a second measurement region, connected with said second conductive region. The capacitance of the corresponding capacitor of the sub pixel can be detected by the structure, thereby providing data basis for judging the performance and quality of the sub pixel and the liquid crystal display panel.

Abstract: This disclosure relates generally to a chip package assembly arranged to be electrically coupled to a circuit board including a plurality of circuit board contacts. The chip package assembly may include a chip package including a first side and a second side, the second side including a first plurality of contacts arranged to be electrically coupled to the plurality of circuit board contacts and a second plurality of contacts arranged to be electrically coupled to a remote device via a connector assembly.

Abstract: A pogo pin may include a housing, a resilient connecting member and a switching unit. The housing may be arranged between a printed circuit board (PCB) and a probing head. The resilient connecting member may be arranged in the housing to electrically connect the PCB with the probing head. The switching unit may be provided in the housing to selectively cut off an electrical connection between the PCB and the probing head. Thus, because the PCB may not require additional switching substrates, the PCB may have a small size so that the probe card may also have a small size. A semiconductor device may be manufactured using the probe card.

Abstract: A system and method for evaluating wafer test probe cards under real-world wafer test cell condition integrates wafer test cell components into the probe card inspection and analysis process. Disclosed embodiments may utilize existing and/or modified wafer test cell components such as, a head plate, a test head, a signal delivery system, and a manipulator to emulate wafer test cell dynamics during the probe card inspection and analysis process.

Abstract: Disclosed is a method for mounting a wafer on a probe card. In the wafer mounting method, an extendable tubular member is placed to surround the probe card, the wafer is placed on a chuck top, the chuck top is supported by a movable stage, and the stage is moved toward the probe card together with the wafer and the chuck top to bring the chuck top into contact with the tubular member. After the chuck top is in contact with the tubular member, the stage is moved toward the probe card together with the wafer and the chuck top to bring the wafer into contact with the probe card and maintain a positional relationship of the stage, the wafer, and the chuck top. After the wafer is in contact with the probe card, a space surrounded by the chuck top, the tubular member, and the probe card is evacuated.

Abstract: A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; at least two metal layers, formed above the substrate, each metal layer forming a specific circuit, wherein two adjacent metal layers are separated by an inter-metal dielectric layer; and a passivation layer, formed on a top side of the chip. By changing the I/O pad from the top of the chip to the peripheries, the extra thickness of the packaged chip caused by wire bonding in the prior arts can be reduced.

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Abstract: A smart output protector device includes a data positive input, a data positive output, a data negative input, a data negative output, a first resistor, and a first normally closed relay. The first resister blocks direct short circuits. The first normally closed relay separates the smart output protector device when opened.

Abstract: A test interface board includes a substrate including a power plane electrically connected to at least one power terminal of a semiconductor device under test, and a ground plane electrically connected to at least one ground terminal of the semiconductor device under test, and a voltage regulator arranged on the substrate and configured to supply, via the power plane and the ground plane, to the semiconductor device under test, a driving voltage.

Abstract: A probe card includes a wiring substrate including an opening portion and a connection pad arranged on an upper face of the wiring substrate located on the periphery of the opening portion, a resin portion formed in the opening portion of the wiring substrate, and the resin portion formed of a material having elasticity, a contact terminal arranged to protrude from the lower face of the resin portion, and wire buried in the resin portion and connecting the contact terminal and the connection pad, wherein the contact terminal is formed of an end part of the wire, and is formed integrally with the wire.

Abstract: A probe card includes a wiring substrate including an opening portion, a first connection pad, and a second connection pad arranged in an opposite area to the first connection pad, a resin portion formed in the opening portion, a first wire buried in the resin portion, in which one end is connected to the first connection pad and other end constitutes a first contact terminal, and a second wire buried in the resin portion, in which one end is connected to the second connection pad and other end constitutes a second contact terminal, wherein the first and second wires extend on one line, and the first and second contact terminals are arranged on the one line, and the first and second contact terminals are gathered to be separated such that the first and second contact terminals touch one electrode pad of a text object with a pair.

Abstract: At least two needles (11, 12) are inserted from the surface of an outer covering film (200) such that the needles reach metal foils (252, 262) in the outer covering film (200), and the electrical connection state with an object inside of a structure covered with the outer covering film (200) is inspected. The electrical connection state is more reliably inspected.

Abstract: A probe card, which is between a tester and a device under test (DUT), includes two first electrical lines, two second electrical lines, two inductive elements, and a capacitor. The first electrical lines are electrically connected to the probes respectively. The second electrical lines are electrically connected to the first electrical lines respectively. The inductive elements are electrically connected to the first electrical lines and the tester respectively; and the capacitor has opposite ends connected to the second electrical lines respectively.

Abstract: The contacts of a probing apparatus are elastically supported on a replaceable coupon and electrically interconnected with conductors on a membrane or a space transformer.

Abstract: A test pin array (21) array with electrostatic discharge protection comprises at least one modified test pin (22) with a static dissipative element (24) incorporated at its plunger tip (23). The use of the modified test among the test pin array provides an extremely low-cost alternative solution to the large scale testing of microchips without the use of any air ionizer.

Abstract: A method for testing an Integrated Circuit (IC) with Near Field Communication (NFC) technology according to a first embodiment of the present invention includes: utilizing a BB modem of the IC to generate a known data pattern; modulating the known data pattern to generate a modulated data pattern; sending the modulated data pattern on the transmitting path to an NFC antenna of the IC and utilizing the NFC antenna to loop the modulated data pattern back to the receiving path; demodulating the modulated data pattern; and determining if the data pattern on the transmitting path is the same as the data pattern on the receiving path. When the data pattern on the transmitting path is not the same as the data pattern on the receiving path, it is determined that the IC fails.

Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.

Abstract: A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.

Abstract: Apparatuses and methods for a self-biased delay looked loop with delay linearization are provided. One example delay locked loop (DLL) circuit (100, 200) can include a digital-to-analog converter (DAC) (104, 204, 304) and a bias generator (108, 208) communicatively coupled to an output of the DAC (106, 206, 306). The bias generator (108, 208) is configured to provide a clock signal and a bias signal. A delay control circuit (DCC) (109, 209) is communicatively coupled to the bias generator (108, 208). The DCC (109, 209) is configured to provide a delayed clock signal based on the clock signal and the bias signal. A DAC bias circuit (122, 222, 422) is communicatively coupled to the DAC (106, 206, 306) and configured to provide a feedback signal to the DAC (104, 204, 304) based on the bias signal.

Abstract: A test probe card structure includes a probe card and a connection circuit common plate. The probe card includes a probe substrate, A test circuit board is disposed between the probe substrate and the connection circuit common plate, The test circuit board has a lest circuit connection section attached to and electrically connected with a common circuit adaptation section of the connection circuit common plate. A circuit extension section is formed around the connection circuit common plate, which is all-channel electrically connectable between a tester and the teat circuit connection section. The connection circuit common plate serves to provide an all-channel test circuit convergence connection ability for the test circuit board so as to greatly minify the size of the test circuit board and lower the manufacturing cost of the probe card.

Abstract: Conductive electronic device structures such as a conductive housing member that forms part of an antenna may be tested during manufacturing. A test system may be provided that has a capacitive coupling probe. The probe may have electrodes. The electrodes may be formed from patterned metal structures in a dielectric substrate. A test unit may provide radio-frequency test signals in a range of frequencies. The radio-frequency test signals may be applied to the conductive housing member or other conductive structures under test using the electrodes. Complex impedance data, forward transfer coefficient data, or other data may be used to determine whether the structures are faulty. A fixture may be used to hold the capacitive coupling probe in place against the conductive electronic device structures during testing.

Abstract: An embodiment, in a single structure, combines a pad including a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside of the chip itself and at least one capacitor. By combining a connection pad and a capacitor in a single structure, it may be possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the capacitor itself. In this way, the costs and size of the chip can be reduced.

Abstract: A test system can include a probe suitable to be coupled between a test measurement device and a device under test (DUT). The probe can include a signal input to receive an active signal from the DUT and a signal output to provide the active signal to the test measurement device. The probe can also include an input ground to connect to the DUT ground and an output ground to connect to the test measurement device ground. A probe ground connection checking device can automatically determine whether the probe ground connections to the DUT ground and test measurement device ground are solid.

Abstract: A probe apparatus is provided, comprising a card clamp mechanism configured to detachably clamp a probe card equipped with a plurality of probes; a wafer chuck configured to mount a semiconductor wafer thereon and configured to provide contact between electrodes formed in the semiconductor wafer with the probes of the probe card clamped by the card clamp mechanism with an operation of a drive mechanism; and a card movement mechanism configured to move the card clamp mechanism and the probe card clamped by the card clamp mechanism to at least two positions spaced at a predetermined distance.

Abstract: A probe card interface for interfacing a probe head with a first circuit. The probe card interface includes an impedance control element to interface a first set of pins of the probe head with the first circuit. The impedance control element is further configured to control the impedance of the first set of pins. The probe card interface includes a conductive plane to interface a second set of pins of the probe head with the first circuit. The conductive plane is further coupled to provide at least one of power or ground to the second set of pins.

Abstract: A semiconductor inspection apparatus has a test-program execution part, a signal-condition detection part, a test-time calculation part to calculate an optimum test time having a duration from a period of the unstable region to a certain period at a leading portion of the stable region subsequent to the unstable region based on the unstable and stable regions detected by the signal-condition detection part, a test-program modification part to reflect the optimum test time in the test program, and a signal waveform importing part to import a signal at the signal output pin of the device to be tested based on a test time written in the test program in which the optimum test time is reflected. The test-program execution part executes the test program again after the optimum test time is reflected in the test program by the test-program modification part.

Abstract: An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Abstract: A test apparatus for testing a semiconductor device includes a circuit board having a contact pattern on one side and an opening therethrough, and a probe card supporting a probe needle array. The probe needle array is insertable into the opening of the circuit board and is configured to probe a device under test. The probe needle array is in electrical contact with the contact pattern of the circuit board, to allow signals through the probe card and circuit board to a test equipment. A holder supports the probe card and other probe cards. The holder has multiple sides, each of which is supportable of a probe card having a probe needle array. The holder is rotatable to manipulate and position the probe needle arrays of the probe cards relative to a device under test. The holder allows disconnection and replacement of the probe needle arrays from the holder.

Abstract: A test system is provided. A printed circuit board (PCB) includes a plurality of traces and at least one test point. A central processing unit (CPU) socket including a plurality of first pins and a memory module slot including a plurality of second pins are disposed on the PCB. Each of the second pins is coupled to the corresponding first pin of the CPU socket via the corresponding trace. A CPU interposer board is inserted into the CPU socket, and a memory interposer board is inserted into the memory module slot. The traces form a test loop via the CPU interposer board and the memory interposer board. When an automatic test equipment (ATE) provides a test signal to the test loop via the test point, the ATE determines whether the test loop is normal according to a reflectometry result of the test signal.

Abstract: A probe apparatus has probe wires with a contact pattern on one side. The contact pattern is for contacting a respective contact pattern on another test equipment or component, such as a circuit board. The probe wires have tips that probe a device desired for testing. Signals are transmitted through the probe wires from the probe card, for example, through a circuit board to other diagnostic equipment. The contact of the probe card with the circuit board allows signals to be transferred through the probe wires to the other diagnostic equipment. On another side of the probe card is a connector structure. The connector structure includes a retainer that can allow the probe card to be replaced from a test system, such as allowing it to be connected and disconnected from a holder.

Abstract: A first switch is arranged such that a first terminal thereof is connected to an AC test unit and a second terminal thereof is connected to an I/O terminal and a DC test unit. A first switch is configured so as to be capable of switching states between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A bypass capacitor is arranged between the first terminal and the second terminal, and is configured to bypass the frequency component which is cut off by the first switch.

Abstract: A test apparatus includes a foreign matter removal unit having a first slope provided with an abrasive coating or an adhesive sheet and a second slope provided with an abrasive coating or an adhesive sheet, the second slope facing the first slope in such a manner that an upper end of the second slope is spaced from an upper end of the first slope a greater distance than a lower end of the second slope is spaced from a lower end of the first slope, a test unit for testing electrical characteristics of a semiconductor chip, and a transfer unit for holding and releasing the semiconductor chip at a position above the first and second slopes and transferring the semiconductor chip to the test unit.

Abstract: A pogo pin may include a housing, a resilient connecting member and a switching unit. The housing may be arranged between a printed circuit board (PCB) and a probing head. The resilient connecting member may be arranged in the housing to electrically connect the PCB with the probing head. The switching unit may be provided in the housing to selectively cut off an electrical connection between the PCB and the probing head. Thus, because the PCB may not require additional switching substrates, the PCB may have a small size so that the probe card may also have a small size. A semiconductor device may be manufactured using the probe card.

Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

Abstract: A probe module for testing an electronic device comprises at least two contacts, each contact including a first end portion extending in a first direction along a first line, a second end portion extending linearly in a second direction opposite from the first direction and along a second line, and a third curved portion extending between the first end portion and the second end portion. The first line is spaced apart from and in parallel with the second line, and the at least two contacts are spaced apart from each other in a direction perpendicular to the first line and the second line. Methods for making such a probe module are also taught.

Abstract: A wiring board for transmission of test signals between test point locations on a circuit board under test and an external analyzer having compliant contacts making electrical contact with a pad positioned on a conductive surface circuit layer having a trace extending to a second pad having a hole for receipt of an interface pin having a swaged head electrically connected to the external analyzer.