Abstract: A test system for testing a large number of dice on a semiconductor wafer without repositioning test probes is disclosed. The test system includes a set of dice under test (DUT) connected together by a plurality of signal buses formed on a semiconductor wafer, at least one test die designed for carrying out tests of the dice under test, the test die having a set of pads to be connected to one or more probes of an external test apparatus, and a probe card with at least one multiplexer implemented in the probe card, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes.

Abstract: A stiffener assembly for use with testing devices is provided herein. In some embodiments, a stiffener assembly for use with testing devices can be part of a probe card assembly that can include a stiffener assembly comprising an upper stiffener coupled to a plurality of lower stiffeners; and a substrate constrained between the upper stiffener and the plurality of lower stiffeners, the stiffener assembly restricting non-planar flex of the substrate while facilitating radial movement of the substrate with respect to the stiffener assembly.

Abstract: A test apparatus is described that can be useful as test equipment in various applications, including for example testing a semiconductor device. The test apparatus has a circuit board, a probe card, and a card holder. The circuit board includes a contact layout that electrically connects with a probe card at one portion and electrically connects with a probe card holder at another portion. The probe card has probes for electrically contacting a device to be tested, and has a contact configuration that electrically connects with the circuit board. The apparatus allows for electrical signals to be sent to and from the probe card, through the probe card holder and circuit board, in testing a device such as for example a semiconductor device. The circuit board and probe card holder have an attachment structure, configured for example as a notch and catch finger attachment arrangement.

Abstract: The present invention is a method for evaluating a silicon wafer by measuring, after fabricating a MOS capacitor by forming an insulator film and one or more electrodes sequentially on a silicon wafer, a dielectric breakdown characteristic of the insulator film by applying an electric field from the electrodes thus formed to the insulator film, the method in which the silicon wafer is evaluated at least by setting an area occupied by all the electrodes thus formed to 5% or more of an area of a front surface of the silicon wafer when the one or more electrodes are formed. This provides an evaluation method that can detect a defect by a simple method such as the TDDB method with the same high degree of precision as that of the DSOD method.

Abstract: An electronic apparatus includes a first power contact, a second power contact, and a control unit. The first power contact is electrically connected with an anode of a power supply source, and the second power contact is electrically connected with a cathode of the power supply source. The control unit electrically connects the first power contact and the second power contact for forming a signal transmission path and receiving the power generated by the power supply source. When the control unit is operated in a testing mode, the control unit operates in a working mode or a sleeping mode according to an instruction of a default instruction set for changing a current waveform signal transmitted over the signal transmission path, so as to achieve the purpose of providing a convenient and high-efficiency testing.

Abstract: Apparatus for terminating a test signal applied to multiple semiconductor loads under test is described—for example apparatus for interfacing a test signal between a tester and a semiconductor device under test (DUT). In some examples, a probe card assembly may include at least one probe substrate each having test probes configured to contact test features of a DUT; a wiring substrate, coupled to the at least one probe substrate, having a connector configured for coupling with a source termination of a tester; a signal path formed on and/or in the wiring substrate and the at least one probe substrate, the signal path having a trace and trace stubs fanning out from the trace, an input of the trace being coupled to the connector and outputs of the trace stubs being coupled to the test probes; and a resistive termination coupled between the trace and at least one potential.

Abstract: A loading card includes a printed circuit board, first and second connection portions. The first connection portion includes first and second voltage pins, and a first ground pin. The second connection portion includes third and fourth voltage pins, and a second ground pin. The loading card also includes a first voltage signal test point connected to the first and third voltage pins, a second voltage signal test point connected to the second and fourth voltage pins, a first ground signal test point connected to the first and second ground signal test points, and a second ground signal test point connected to the first and second ground signal test points.

Abstract: A testing card for peripheral component interconnection (PCI) interface includes a body, a plurality of PCI pins, a PCI interface chip, and a plurality of PCI testing pins. The PCI pins are mounted to the body. The PCI interface chip is mounted to the body and connected to the PCI pins. The PCI testing pins are mounted to the body and electrically connected to the pins of the PCI interface chip. When the PCI pins are connected to a PCI slot of a motherboard, the PCI interface chip is configured to communicate with the motherboard.

Abstract: A first switch is arranged such that a first terminal thereof is connected to an AC test unit and a second terminal thereof is connected to an I/O terminal and a DC test unit. A first switch is configured so as to be capable of switching states between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A bypass capacitor is arranged between the first terminal and the second terminal, and is configured to bypass the frequency component which is cut off by the first switch.

Abstract: A contact for an electrical test comprises a first area to be bonded to a board, a second area extending in the right-left direction from the lower end portion of the first area, a third area projecting downward from the tip end portion of the second area, and a low light reflective film having lower light reflectance than that of the first area. The third area has a probe tip to be contacted an electrode of an electronic device. The low light reflective film is formed on a surface of at least the bonding part of the first area to the board and its proximity.

Abstract: Methods and apparatus for testing devices using serially controlled intelligent switches have been described. In some embodiments, a probe card assembly can be provided that includes a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line.

Abstract: A wafer test equipment system includes a performance board connected to a tester head of a tester. A universal block printed circuit board is positioned on the performance board, directly connecting a plurality of normal signal lines to a probe card and dividing each of a plurality of power signal lines into multiple paths and connecting them to the probe card. A cable assembly transfers the normal signal lines and the power signal lines between the universal block printed circuit board and the tester head. The cable assembly is soldered directly to the universal block printed circuit board in a perpendicular direction through a center portion of the performance board. A probe card is removably secured to the performance board including the universal block printed circuit board.

Abstract: A probe core includes a frame, a wire guide connected to the frame, a probe tile, and a plurality of probe wires supported by the wire guide and probe tile. Each probe wire includes an end configured to probe a device, such as a semiconductor wafer. Each probe wire includes a signal transmitting portion and a guard portion. The probe core further includes a lock mechanism supported by the frame. The lock mechanism is configured to allow the probe core to be connected and disconnected to another test equipment or component, such as a circuit board. As one example, the probe core is configured to connect and disconnect from the test equipment or component in a rotatable lock and unlock operation or twist lock/unlock operation, where the frame is rotated relative to remainder of the core to lock/unlock the probe core.

Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.

Abstract: A power supply with and input and output includes an amplifier configured to set an output voltage of the power supply output equal to a fixed input voltage for the power supply. The power supply has a first output stage coupled to the amplifier and configured to source and sink current at the output of the power supply between a first voltage rail and a third voltage rail. The power supply has a second output stage coupled to the amplifier and configured to source and sink current to the output of the power supply between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.

Abstract: A planarizer for a probe card assembly. A planarizer includes a first control member extending from a substrate in a probe card assembly. The first control member extends through at least one substrate in the probe card assembly and is accessible from an exposed side of an exterior substrate in the probe card assembly. Actuating the first control member causes a deflection of the substrate connected to the first control member.

Abstract: An exemplary aspect of an embodiment of the present invention is a semiconductor device including a plurality of test elements formed in an array on a semiconductor substrate, an address signal generating portion that generates an address signal corresponding to each of the test elements, and a digital-to-analog converter that converts the address signal into an analog signal and outputs the converted analog signal. The present invention enables to recognize which DUT is being measured.

Abstract: An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.

Abstract: Methods and apparatus for testing devices using serially controlled intelligent switches have been described. In some embodiments, a probe card assembly can be provided that includes a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line.

Abstract: Embodiments of methods and apparatus for aligning a probe card assembly in a test system are provided herein. In some embodiments, an apparatus for testing devices may include a probe card assembly having a plurality of probes, each probe having a tip for contacting a device to be tested, and having an identified set of one or more features that are preselected in accordance with selected criteria for aligning the probe card assembly within a prober after installation therein. In some embodiments, the identity of the identified set of one or more features may be communicated to the prober to facilitate a global alignment of the probe card assembly that minimizes an aggregate misalignment of all of the tips in the probe card assembly.

Abstract: Provided is a test apparatus including a test head main body 130 that communicates a signal with the device under test 200, a prober 110 on which the device under test 200 is mounted, and a probe card 300 positioned between the test head main body 130 and the prober 110, where the probe card 300 includes: a plurality of probe pins 320 provided on a surface thereof facing the prober 110 and electrically connected to a terminal of the device under test 200; a plurality of test head pads 330 provided on a surface thereof facing the test head main body 130 and electrically connected to spring pins 129 on the test head main body 130 and to the probe pins 320; and prober pads 340 provided on a surface thereof facing the prober 110 and electrically connected to the plurality of probe pins 320.

Abstract: Systems and methods for providing a stack with a guard plane embedded in the stack are disclosed. An electrical apparatus can be made by forming a stack comprising an electrically conductive signal structure, an electrical guard structure, and an electrically insulating structure disposed between the signal structure and the guard structure. The signal structure, insulating structure, and guard structure can be aligned one with another in the stack.

Abstract: A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.

Abstract: A contacting component has a probe contact formed by plating and adapted to be contacted with a target portion. The contacting component includes an insulating substrate, a conductive circuit formed on one surface of the insulating substrate, and the probe contact is made of a conductive material and formed on the other surface of the insulating substrate. The conductive circuit and the probe contact are electrically connected in a through hole penetrating the insulating substrate. The probe contact includes a bump contact of a convex shape, the bump contact is formed by plating and having a surface which has a shape of a semispherical protrusion to be contacted with the target portion. The bump contact is made of a material containing a metal and carbon, the content of carbon falling within a range between 0.2 at % and 1.2 at %, both inclusive.

Abstract: The present invention discloses a three-dimensional microprobe array assembly structure, wherein spacers are used in assembling edge-type microprobe arrays to form a three-dimensional structure, and the spacers reveal conductive pads of the edge-type microprobe arrays to benefit wire bonding. The present invention detects depths and angles and thus increases detection reliability. Besides, in the present invention, the related IC is integrated with the spacer to achieve circuit integration and reduce cost.

Abstract: Methods and apparatus for providing a tester integrated circuit (IC) for testing a semiconductor device under test (DUT) are described. Examples of the invention can relate to an apparatus for testing a semiconductor device under test (DUT). In some examples, the apparatus can include an integrated circuit (IC) coupled to test probes configured to contact pads on the DUT, the IC including a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits.

Abstract: Devices and methods for providing, making, and/or using an electronic apparatus having a wall structure adjacent a resilient contact structure on a substrate. The electronic apparatus can include a substrate and a plurality of electrically conductive resilient contact structures, which can extend from the substrate. A first of the contact structures can be part of an electrical path through the electronic apparatus. A first electrically conductive wall structure can also extend from the substrate, and the first wall structure can be disposed adjacent one of the contact structures. The first wall structure can be electrically connected to a return current path within the electronic apparatus for an alternating current signal or power on the first contact structure.

Abstract: Methods, devices, and systems for probing electrical circuits without loading the circuits are described herein. One embodiment of an electrical probe includes a coaxial cable having an inner conductor and an outer conductor, an extension portion of the inner conductor extending beyond the outer conductor at a probe end of the cable. The electrical probe includes a conductive whisker having a first portion separated from and extending a distance along the extension portion such that the first portion and the extension portion form a first capacitor and a second portion having a probe tip for receiving an input test signal from a circuit node under test.

Abstract: The present invention provides a contactor assembly (100,200,300) for testing of semiconductor devices (DUT). The contactor assembly (100,200,300) includes a plurality of probes (20,22,24), a contactor holder (150,350) and a cover (180,280) shaped and dimensioned to fit on the contactor holder (150,350). The contactor holder (150,350) is a stack of laminates. A top laminate (156,256) of the contactor holder (150,350) has apertures (158,258). A contact probe (22) is seen through one aperture (158,258). On a rear face of the cover (180,280), there is at least one conductive pad (186) in register with an aperture (158,258). Each aperture (158,258) is operable to house a surface-mount electric component (160), such as a resistor, capacitor or inductor, and a conductive compressive element (162). In another embodiment, a front side of a cover (280) has a connector (285) in electrical communication with a conductive pad (186).

Abstract: A differential test probe for a printed wiring board test system includes a probe body having a proximal end and a distal end. Each of a plurality of coaxial cables extending from the proximal end to the distal end. The plurality of coaxial cables each includes a center conductor having an axial aperture at the distal end. The differential test probe also includes a plurality of signal pins that are each mounted in the axial aperture of the center conductor of one of the plurality of coaxial cables to electrically couple the signal pin to the center conductor. A plurality of ground pins are coupled to the probe body and selectively arranged relative to the plurality of signal pins to provide multiple signal to ground paths between the plurality signal pins and the plurality ground pins.

Abstract: A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.

Abstract: A wafer-scale probe card for temporary electrical contact to a sample wafer or other device, for burn-in and test. The card includes a plurality of directly metallized single-walled or multi-walled nanotubes contacting a pre-arranged electrical contact pattern on the probe card substrate. The nanotubes are arranged into bundles for forming electrical contacts between areas of the device under test and the probe card. The bundles are compressible along their length to allow a compressive force to be used for contacting the probe card substrate to the device under test. A strengthening material may be disposed around and/or infiltrate the bundles. The nanotubes forming the bundles may be patterned to provide a pre-determined bundle profile. Tips of the bundles may be metallized with a conductive material to form a conformal coating on the bundles; or metallized with a conductive material to form a continuous, single contact surface.

Abstract: An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. In addition, the base die includes a first probe pad configured to couple test input, a second probe pad configured to couple test output and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die so as to implement a scan chain for testing of the integrated circuit device.

Abstract: An integrated circuit probing structure (40) is provided for evaluating functional circuitry (42), such as a slow slew-rate square wave signal from a low power circuit, where the probing structure includes two or more probe pads (48, 49) for testing the functional circuitry which are formed to be electrically separate from one another, and a probe test circuit (46) connected to the functional circuitry (42) for conveying a signal from the functional circuitry to a probe needle (47) only when the probe needle (47) electrically connects the two or more probe pads (48, 49).

Abstract: Embodiments of probe cards and methods for fabricating and using same are provided herein. In some embodiments, an apparatus for testing a device (DUT) may include a probe card configured for testing a DUT; a thermal management apparatus disposed on the probe card to heat and/or cool the probe card; a sensor disposed on the probe card and coupled to the thermal management apparatus to provide data to the thermal management apparatus corresponding to a temperature of a location of the probe card; a first connector disposed on the probe card and coupled to the thermal management apparatus for connecting to a first power source internal to a tester; and a second connector, different than the first connector, disposed on the probe card and coupled to the thermal management apparatus for connecting to a second power source external to the tester.

Abstract: A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer.

Abstract: A probe system for connecting a measurement apparatus to a DUT includes an AC probe having an AC shield conductor and an AC probe conductor shielded by the AC shield; a first DC probe having a first DC probe conductor and a first guard conductor for guarding the first DC probe conductor when a virtual version of a voltage on the first DC probe conductor is applied to the first guard conductor; a second DC probe having a second DC probe conductor and a second guard conductor for guarding the second DC probe conductor when a virtual version of a voltage on the second DC probe conductor is applied to the second guard conductor; a first capacitive connection between the AC shield conductor and the first guard conductor; a second capacitive connection between the AC shield conductor and the second guard conductor; a third capacitive connection between the first guard conductor and the first DC probe conductor; and a fourth capacitive connection between the second guard conductor and the second DC probe conductor,

Abstract: An electronic device for use with a probe head in automated test equipment includes first and second pluralities of semiconductor devices. The first plurality of semiconductor devices is arranged to form at least one driver arranged to couple to a device under test. The at least one driver is configured to transmit a signal to the at least one device under test. The second plurality of semiconductor devices is arranged to form at least one receiver arranged to couple to the device under test. The at least one receiver is configured to receive a signal from the at least one device under test. Each of the second plurality of semiconductor devices has a thickness less than about 300 ?m exclusive of any electrical interconnects. The at least one receiver is adapted to mount directly to the probe head.