Abstract: The present invention discloses a semiconductor chip probe for measuring conducted electromagnetic emission (EME) of a bare die and a conducted EME measurement apparatus with the semiconductor chip probe. The semiconductor chip probe comprises a substrate, a dielectric layer, an impedance unit, a measuring unit and a connection unit. The measurement apparatus comprises a semiconductor chip probe, a high frequency probe, a signal cable and a test receiver. The integrated passive component network designed and embedded inside the semiconductor chip probe forms the 1? or 150? impedance network. And the semiconductor chip probe is able to directly couple the EME conducted current or voltage from the test pin of the flipped chip under test to the test receiver for measurement.

Abstract: A device tester is provided. The device tester includes a probe card and a substrate coupled to the probe card. The substrate has a plurality of layers for routing a signal. An integrated circuit is coupled to the substrate. The integrated circuit is operable to transmit an input signal received from a testing apparatus to a device under test through the substrate to a signal probe. The signal probe is further operable to receive a test signal from the device under test in response to the input signal, wherein the integrated circuit is operable to amplify the test signal, and transmit the amplified test signal to the testing apparatus.

Abstract: A probe module, which supports loopback test and is provided between a PCB and a DUT, includes a substrate, a probe base, two probes, two signal path switchers, and a capacitor. The substrate has two first connecting circuits and two second connecting circuits, wherein an end of each first connecting circuit is connected to the PCB. The probe base is provided between the substrate and the DUT with the probes provided thereon, wherein an end of each probe is exposed and electrically connected to one second connecting circuit, while another end thereof is also exposed to contact the DUT. Each signal path switcher is provided on the probe base, and respectively electrically connected to another end of one first and one second connecting circuits. The capacitor is provided on the probe base with two ends electrically connected to the two signal path switchers.

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Abstract: Apparatus and methods for identifying a signal on a printed circuit board (‘PCB’) under test, including an integrated circuit mounted on the PCB, the integrated circuit having a test signal generator that transmits a test signal to an output pin of the integrated circuit, with the output pin connected to a test point on the PCB; the integrated circuit also having signal identification logic that inserts into the test signal, an identifier of the signal; a test probe in contact with the test point; and a signal-identifying controller that receives the test signal and the identifier from the test probe and displays, in dependence upon the identifier, the identity of the signal.

Abstract: A semiconductor wafer includes semiconductor chips divided by a dicing line, one of the semiconductor chips including terminals of an identical potential; a wiring located on the dicing line, and electrically connecting the terminals to each other; and a pad electrically connected through the wiring to the terminals, wherein the pad is located entirely on the semiconductor chip and is not present on the dicing line.

Abstract: A test apparatus that tests a plurality of devices under test formed on a wafer under test includes a test substrate that faces the wafer under test and is electrically connected to the devices under test, a programmable device that is provided on the test substrate and changes a logic relationship of output logic data with respect to input logic data, according to program data supplied thereto, a plurality of input/output circuits that are provided on the test substrate to correspond to the devices under test and that each supply the corresponding device under test with a test signal corresponding to the output logic data of the programmable device, and a judging section that judges pass/fail of each device under test, based on operation results of each device under test according to the test signal.

Abstract: The present disclosure provide a probe card for wafer level testing. The probe card includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; and a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board.

Abstract: Methods and apparatus for testing devices using serially controlled intelligent switches have been described. In some embodiments, a probe card assembly can be provided that includes a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line.

Abstract: A method of testing semiconductor devices is provided includes: exposing one end of the device contact on the surface of the semiconductor; using a scanning probe microscopy apparatus to scan a diagnostic area on the semiconductor; applying a direct current bias between the conductive probe and a substrate of the semiconductor; directing a testing radiation at the diagnostic area to increase amount of free carriers in the device contacts and in the semiconductor layer under the device contacts; and detecting the current flowing through the conductive probe and the substrate, wherein a defect current signal is measured when the probe is in contact with a defective device contact and a normal current signal is measured when the probe is in contact with a normal device contact, wherein the testing radiation increases the current measured to increase the difference between the defect signal and the normal signal.

Abstract: A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern.

Abstract: A test prod for high-frequency measurement having a contact-side end for electrically contacting planar structures and a cable-side end, for connecting to a cable, wherein between the contact-side end and the cable-side end a coplanar conductor structure having at least two conductors is arranged, wherein on the coplanar conductor structure a dielectric is arranged over a predetermined section between the cable-side end and the contact-side end, wherein the test prod is between the dielectric and the contact-side end such that the conductors of the coplanar conductor structure are arranged freely in space and relative to the dielectric in a suspending manner, wherein on one side of the test prod facing towards the planar structure a shielding element is arranged extending into the area of the coplanar conductor structure.

Abstract: The present disclosure provides a probe card for wafer level testing. The probe card includes a space transformer having first power/ground lines and first signal lines embedded therein, wherein the first power/ground and signal lines are configured to have a first wiring pitch on a first surface and a second wiring pitch on a second surface, the second wiring pitch being substantially less than the first wiring pitch; a printed circuit board bonded to the first surface of the space transformer, wherein the printed circuit board includes second power/ground lines and second signal lines embedded in the printed circuit board and coupled to the first power/ground and signal lines; and conductive lines configured to a surface of the printed circuit board remote to the first surface of the space transformer, wherein each of the conductive lines includes a first end coupled to one of the second signal lines and a second end coupled to a different location of the printed circuit board.

Abstract: A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.

Abstract: A test apparatus that test a device under test, comprising a test head that is arranged facing the device under test and that includes a test module for testing the device under test, and a probe assembly that transmits a signal and that is arranged between the test head and the device under test. The probe assembly includes a plurality of low voltage pins arranged at prescribed intervals from each other, and a plurality of high voltage pins that are arranged such that distance between each high voltage pin and each low voltage pin is greater than the prescribed interval, and that transmit a signal with a higher voltage than a signal transmitted by the low voltage pins. All of the high voltage pins are arranged in only one of two regions formed by dividing a surface of the probe assembly in half.

Abstract: Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal.

Abstract: An integrated circuit probing structure (40) is provided for evaluating functional circuitry (42), such as a slow slew-rate square wave signal from a low power circuit, where the probing structure includes two or more probe pads (48, 49) for testing the functional circuitry which are formed to be electrically separate from one another, and a probe test circuit (46) connected to the functional circuitry (42) for conveying a signal from the functional circuitry to a probe needle (47) only when the probe needle (47) electrically connects the two or more probe pads (48, 49).

Abstract: Circuits and methods for testing wafers are disclosed herein. An embodiment of a method includes electrically contacting a first probe and a second probe to a wafer. A gas is blown in the areas proximate the first probe and the second probe. An electric potential is then applied between the first probe and the second probe while the gas is being blown.

Abstract: A probe card 10 includes a first probe 11 configured to come into electric contact with an emitter electrode of a power device D; a block-shaped first connecting terminal 12 to which the first probe 11 is connected; a second probe 13 configured to come into electric contact with a gate electrode of the power device D; a block-shaped second connecting terminal 14 to which the second probe 13 is connected; a contact plate 15 configured to come into electric contact with a collector electrode of the power device D; and a block-shaped third connecting terminal 16 fixed to the contact plate 15. Further, the first connecting terminal 12, the second connecting terminal 14 and the third connecting terminal 16 electrically come into direct contact with corresponding connection terminals of a tester, respectively.

Abstract: A first device and a second device can include at least one alignment feature and at least one corresponding constraint. The alignment feature and the constraint can be configured to align the first device and the second device when the alignment feature is inserted into the constraint. The alignment feature and the constraint can be further configured to direct relative movement between the first device and the second device due to relative thermal expansion or contraction between the first device and the second device. The directed relative movement can keep the first device and the second device aligned over a predetermined temperature range.

Abstract: A probe card comes in touch with a test object to perform an inspection. The probe card contains: a probe substrate provided with a plurality of probes on the first surface and a plurality of anchor receiving portions on the second surface; and a supporting body disposed to support the periphery of the probe substrate, with at least a plurality of anchor receiving portions located within a probe existence region being arranged regularly and at an equal distance from each other on the second surface of the probe substrate.

Abstract: A test card includes a power interface, a controller, a test interface, and a test point. The test interface includes a power pin, a start pin, and a data signal pin. The power interface is connected to the controller and the power pin, and also connected to an external power to receive a work voltage. The controller transmits a turn-on signal to the start pin. The test point is connected to the data signal pin. When an interface of a motherboard is connected to the test interface, the power pin, the start pin, and the data signal pin are connected to corresponding pins of the interface of the motherboard. The motherboard outputs a data signal to the test point through the motherboard interface and the test interface after the controller receives the turn-on signal.

Abstract: A test apparatus is described that can be useful as test equipment in various applications, including for example testing a semiconductor device. The test apparatus has a circuit board, a probe card, and a card holder. The circuit board includes a contact layout that electrically connects with a probe card at one portion and electrically connects with a probe card holder at another portion. The probe card has probes for electrically contacting a device to be tested, and has a contact configuration that electrically connects with the circuit board. The apparatus allows for electrical signals to be sent to and from the probe card, through the probe card holder and circuit board, in testing a device such as for example a semiconductor device. The circuit board and probe card holder have an attachment structure, configured for example as a notch and catch finger attachment arrangement.

Abstract: A probe core includes a frame, a wire guide connected to the frame, a probe tile, and a plurality of probe wires supported by the wire guide and probe tile. Each probe wire includes an end configured to probe a device, such as a semiconductor wafer. Each probe wire includes a signal transmitting portion and a guard portion. The probe core further includes a lock mechanism supported by the frame. The lock mechanism is configured to allow the probe core to be connected and disconnected to another test equipment or component, such as a circuit board. As one example, the probe core is configured to connect and disconnect from the test equipment or component in a rotatable lock and unlock operation or twist lock/unlock operation, where the frame is rotated relative to remainder of the core to lock/unlock the probe core.

Abstract: An apparatus and method for protecting probes used in automated testing is disclosed. The apparatus comprises a probe operable to provide power to a device under test (DUT) from a device power source (DPS), wherein the probe is coupled to a contact point on the DUT and a probe protector circuit connected to the probe in series between the DPS and the DUT. The probe protector circuit further comprises a current sense module operable to monitor a flow of current from the DPS to the DUT to determine if the current flow is below a predetermined threshold current level and a switch for controlling the connection from the DPS to the DUT. The switch is coupled to the current sense module and is operable to be used in conjunction with the current sense module to limit the current flow if it exceeds the predetermined threshold current level.

Abstract: An apparatus and method for conducting electrical testing of probes is disclosed. Probes may also be tested for deflection and loading hysteresis.

Abstract: Provided is a test apparatus for testing a plurality of devices under test formed on a semiconductor wafer, including: a probe card to be connected to respective contacts of the plurality of the devices under test on a connection surface to be overlapped on the semiconductor wafer, the probe card being provided with a plurality of corresponding contacts on a rear surface of the connection surface; and a test head that tests the plurality of devices under test on the semiconductor wafer by sequentially connecting to each part of the plurality of contacts of the probe card.

Abstract: A deflection measurement probe includes a body portion having a cavity defined by the body portion, a first positional measurement sensor disposed in the cavity of the body portion, the first positional measurement sensor including a sensor tip extending from the body portion operative to contact a measurement surface, and a second positional measurement sensor disposed in the cavity of the body portion, the first positional measurement sensor including a sensor tip extending from the body portion operative to contact a measurement surface.

Abstract: An embodiment of an electrical connecting apparatus enables reliable identification of a mark and enables accurate and easy determination of a coordinate position of the mark. The electrical connecting apparatus comprises a supporting body having a lower surface, a plurality of contacts arranged on the lower surface of the supporting body, a mark that is provided on a lower side of the supporting body and whose light passing feature differs from that of an area adjacent to the mark, and a light source provided to the supporting body to irradiate light to the mark from an upper side of the mark.

Abstract: A wafer-scale probe card for temporary electrical contact to a sample wafer or other device, for burn-in and test. The card includes a plurality of directly metallized single-walled or multi-walled nanotubes contacting a pre-arranged electrical contact pattern on the probe card substrate. The nanotubes are arranged into bundles for forming electrical contacts between areas of the device under test and the probe card. The bundles are compressible along their length to allow a compressive force to be used for contacting the probe card substrate to the device under test. A strengthening material may be disposed around and/or infiltrate the bundles. The nanotubes forming the bundles may be patterned to provide a pre-determined bundle profile. Tips of the bundles may be metallized with a conductive material to form a conformal coating on the bundles; or metallized with a conductive material to form a continuous, single contact surface.

Abstract: In one embodiment a circuit for testing delays is provided. A test signal generator circuit toggles a plurality of output signals 1 through N in sequential order, separating the toggles by a delay period. Each output signal is coupled to an input of a respective one of a plurality of delay circuits. A phase detector circuit is coupled to the delay circuits and is configured to determine the order in which signals output from delay circuits X?1, X, and X+1 are toggled for each delay circuit X. In response to the output signals being toggled in the order X?1 followed by X followed by X+1, the phase comparator circuit is configured to output a first signal indicating correct operation. Otherwise, the phase comparator circuit is configured to output a second signal indicating incorrect operation.

Abstract: An automated electronics circuit test cassette assembly is provided for mating with a test platform. The platform comprises a platform common signal interface and a vacuum manifold having a combined registration and vacuum port coupler. The cassette assembly includes a cassette common signal interface providing electrical communication with the platform common signal interface and an alignment bushing providing combined registration and vacuum communication with the vacuum port coupler. A pattern of test probes mimic a test pattern on a printed circuit assembly (PCA), extending upwards from a probe support substrate and optionally downward from a clamshell probe substrate. The PCA is supported by a PCA support substrate floating above the test probe support substrate. The clamshell test substrate provides a vacuum seal above the PCA support substrate.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: A tester may include a test head with a movable coupler, a probe card with a connector unit that is coupled with the coupler, and a needle block disposed on the probe card. In one example, the tester may test respective subsets of semiconductor devices on a wafer via a one-touch operation by moving a coupler on the test head, while the wafer remains in continuous and uninterrupted electrical contact with the tester during testing.

Abstract: An embodiment of a probe card adapted for testing at least one integrated circuit integrated on a corresponding at least one die of a semiconductor material wafer, the probe card including a board adapted for the coupling to a tester apparatus, and a plurality of probes coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units, each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test, the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

Abstract: A DDR signal testing assistant device includes a body. The body is detachably locked to a motherboard integrated with a DDR connector. The DDR connector defines a plurality of pins. The body defines a plurality of testing holes corresponding and mating with the pins. Each testing hole of the body is marked with characters. The characters indicate the denomination or property of each corresponding pin of the DDR connector.

Abstract: A probe card and a test apparatus including the probe card for improving test reliability. The probe card may include a first input terminal Microelectromechanical Systems (MEMS) switch that connects a first input terminal and a first input probe pin, wherein the first input terminal MEMS switch comprises a control portion that receives an operation signal and a connection portion that connects the first input terminal and the first input probe pin. The probe card may further include a first output terminal MEMS switch that connects a first output terminal and a first output probe pin, wherein the first output terminal MEMS switch comprises a control portion that receives the operation signal and a connection portion that connects the first output terminal and the first output probe pin.

Abstract: Based upon a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads, a probe chip contactor is established, having a unit standard cell on the probe side of the probe chip to correspond to each of the arranged integrated circuits. The unit standard cell is stepped and repeated for the probe side of the probe chip contactor, to establish a wafer scale standard cell layout. The opposite contact side of the probe chip contactor is connectable to a central structure, e.g. a Z-block or PC board, typically comprising a fixed array of vias with fixed X, Y, and Z locations. The routing of contact side of the probe chip contactor is preferably routed automatically, such as implemented on one or more computers, to provide electrical connections between the substrate through vias and the Z-block through vias.

Abstract: Identifying a signal on a printed circuit board (‘PCB’) under test, including a test probe with a radio transmitter and transmitter antenna, the test probe positioned with the transmitter antenna at a test point on the PCB, the test probe transmitting a radio signal; at least two radio receivers, each receiver having a receiver antenna, each receiver antenna positioned at predetermined, separate physical locations with respect to the PCB, the receivers coupled to at least one signal strength meter, each receiver receiving the transmitted radio signal; and a signal-identifying controller connected to the signal strength meter, the signal-identifying controller reading, from the signal strength meter, signal strengths of the transmitted radio signal as received at the radio receivers; determining, in dependence upon the read signal strengths, a test signal identifier; and displaying the test signal identifier.

Abstract: The present invention provides a ST board 2 that is formed with an lower surface electrode 22; a unit attachment plate 3 that is fastened on the ST board 2 and formed with an opening part 31 exposing the lower surface electrode 22; a probe unit 5 that includes a probe substrate 50 formed with a contact probe 51 and a probe electrode 52 and is fastened on the unit attachment plate 3; and an electrically conductive wire 54 that connects the lower surface electrode 22 and the probe electrode 52 to each other through the opening part 31. The probe unit 5 can be fastened on the ST board 2 with the unit attachment plate 3 intervening, and through the opening part 31 of the unit attachment plate 3, the probe electrode 51 and the lower surface electrode 22 can be electrically connected to each other.

Abstract: A DUT is connected to an I/O terminal. An AC test unit performs an AC test operation for the DUT. A DC test unit performs a DC test operation for the DUT. An optical semiconductor switch is arranged such that a first terminal thereof is connected to the AC test unit and a second terminal thereof is connected to the I/O terminal. The optical semiconductor switch 10 is configured to be capable of switching states, according to control signals input to control terminals, between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A first impedance circuit is arranged on a signal line for the control signal to be input to the positive-electrode control terminal. Furthermore, a second impedance circuit is arranged on a signal line for the control signal to be input to the negative-electrode control terminal.

Abstract: In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive portion exposed on an insulating film, a photomask whose opening area has an outline having two sides along two straight lines approaching to each other as the two straight lines extend from a center portion of the opening area in an extending direction of a wiring path is used.

Abstract: A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer.

Abstract: An electrical signal connector which may be used for testing narrow-pitched chips or multi-chips, and causes no faulty connections between probes and pads or between probes and a circuit board even in a high temperature environment such as in a burn-in test is provided. The electrical signal connector has a probe unit in which a plurality of resin-made film probes, corresponding to one or more pads on a semiconductor chip to be tested, are supported in parallel on a plurality of support plates; a first probe holder of grid structure provided with a plurality of openings; and a second probe holder of the same configuration as that of the first probe holder, the second probe holder having projections at intersection points in the grid structure. The first and second probe holders are fastened to the circuit board with the projections of the second probe holder inserted in corresponding holes of the circuit board and the first probe holder being fastened to the circuit board with screws.

Abstract: A probe card transmitting electrical test signals between a tester and a semiconductor device includes a main circuit board configured to receive and transmit electrical signals from the tester, an interface unit electrically connected to the main circuit board, the interface unit including a signal line and a signal connection terminal, and at least one probe unit connected to the interface unit, the probe unit being detachable and including a plurality of probe needles arranged in a pattern corresponding to a pattern of electrode pads of the semiconductor device.

Abstract: Provided is a probe card including a plurality of unit plates including pad areas and contact probe areas, a plurality of electrode pads formed in the pad areas, a plurality of contact probes formed in the contact probe areas, and a plurality of interconnecting layers electrically connecting the electrode pads and the contact probes. The plurality of unit plates has different sizes and are arranged and laminated so as to expose all the pad areas of each unit plate.

Abstract: A method of estimating the output light flux of a light emitting diode, comprises applying a drive current waveform to the LED over a period of time comprising a testing period. The forward voltage across the LED is monitored during the testing period, and the output light flux is estimated as a function of changes in the forward voltage.

Abstract: A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon.

Abstract: A manufacturing method of manufacturing a wafer unit for testing includes forming a plurality of test circuits on a circuit wafer, forming a plurality of circuit pads on a predetermined surface of a connecting wafer, forming a plurality of wafer pads on a rear surface of the connection wafer opposing the predetermined surface, forming a plurality of long via holes to electrically connect the plurality of circuit pads and the plurality of wafer pads, and forming the wafer unit for testing, by overlapping the circuit wafer and the connection wafer to electrically connect the plurality of test circuits and the plurality of circuit pads.

Abstract: A MEMS probe adapted to contact a corresponding terminal of an integrated circuit, integrated on at least one chip of a semiconductor material wafer during a test phase of the wafer is provided. The probe includes a support structure comprising a first access terminal and a second access terminal; the support structure defines a conductive path between said first access terminal and said second access terminal. The probes further-includes a probe region connected to the support structure adapted to contact the corresponding terminal of the integrated circuit during the test phase for providing at least one test signal received from the first access terminal and the second access terminal to the integrated circuit through at least one portion of the conductive path, and/or providing at least one test signal generated by the integrated circuit to at least one between the first access terminal and the second access terminal trough at least one portion of the conductive path.