Abstract: There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units.

Abstract: An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad.

Abstract: A loading card includes a printed circuit board, first and second connection portions. The first connection portion includes first and second voltage pins, and a first ground pin. The second connection portion includes third and fourth voltage pins, and a second ground pin. The loading card also includes a first voltage signal test point connected to the first and third voltage pins, a second voltage signal test point connected to the second and fourth voltage pins, a first ground signal test point connected to the first and second ground signal test points, and a second ground signal test point connected to the first and second ground signal test points.

Abstract: A system for making high frequency measurements on a DUT includes a high frequency measurement instrument; a plurality of DUT probes; a first coaxial cable having a center conductor and a coaxial conductor for connection between the instrument and a first DUT probe; and a second coaxial cable having a center conductor and a coaxial conductor for connection between the instrument and a second DUT probe, at least one of the first and second cables being selectively shortable between the respective center conductor and coaxial conductor at a location near the respective DUT probe.

Abstract: A test card includes a power interface, a controller, a test interface, and a test point. The test interface includes a power pin, a start pin, and a data signal pin. The power interface is connected to the controller and the power pin, and also connected to an external power to receive a work voltage. The controller transmits a turn-on signal to the start pin. The test point is connected to the data signal pin. When an interface of a motherboard is connected to the test interface, the power pin, the start pin, and the data signal pin are connected to corresponding pins of the interface of the motherboard. The motherboard outputs a data signal to the test point through the motherboard interface and the test interface after the controller receives the turn-on signal.

Abstract: A probe card assembly can include a plurality of probes disposed on a substrate and arranged to contact terminals of a semiconductor wafer. Switches can be disposed on the probe card assembly and provide for selective connection and disconnection of the probes from electrical interconnections on the probe card assembly.

Abstract: A wiring substrate that allows wiring at a fine pitch and has a coefficient of thermal expansion close to the coefficient of thermal expansion of silicone, and a probe card that includes the wiring substrate are provided. To this end, there are provided a wiring substrate that includes a ceramic substrate having a coefficient of thermal expansion of 3×10?6 to 5×10?6/° C. and one or more thin-film wiring sheets stacked on one surface of the ceramic substrate, and a probe head on which a plurality of conductive proves are arranged in accordance with wiring on the thin-film wiring sheet, which holds individual probes while preventing the probes from coming off and allowing both ends of each probe to be exposed, and which is stacked on the wiring substrate while one end of each probe is brought into contact with the thin-film wiring sheet.

Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

Abstract: A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals.

Abstract: Provided is a test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit including: a test wafer having a shape corresponding to a shape of the semiconductor wafer; and a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips. The test wafer unit may include a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, where each of the plurality of connection terminals is connected to a corresponding one of the test terminals.

Abstract: A substrate is provided for a probe card assembly. The substrate includes an interconnection layer including a first surface having a first electrode set and a second surface having a second electrode set electrically connected to the first electrode set. The substrate further includes a base layer including a first surface having a third electrode set electrically connected to the second electrode set and a second surface having a plurality of contact terminals electrically connected to the third electrode set. And the substrate further includes a resin layer including a plurality of sublayers made of different materials. The resin layer is attached to the first surface of the base layer and the second surface of the interconnection layer.

Abstract: Automated test equipment for high-speed testing of devices under test (DUTs) includes a tester channel circuit generating a high-speed electrical test signal applied to the signal input terminal of each DUT, and a contacter board in physical and electrical contact with the DUTs. The contacter board has a high-speed signal transmission channel including (1) an electrical contact at which the high-speed electrical test signal is received, (2) conductive etch extending from the electrical contact to isolation areas each adjacent to the signal input terminal of a respective DUT, and (3) an embedded series isolation resistor formed on an inner layer of the contacter board at a respective isolation area forming a connection between the conductive etch and the adjacent signal input terminal of the respective DUT.

Abstract: A test apparatus includes: test modules that communicate with the device under test to test the device under test; additional modules connected between the device under test and the test modules, each additional module performing a communication with the device under test, the communication being at least one of a communication performed at a higher speed and a communication performed with a lower latency, in comparison with a communication performed by the test modules; a test head having a plurality of connectors that connect the test modules and the additional modules, respectively, the test modules and the additional modules are mounted on the test head; a performance board placed on the test head that connects between at least a part of terminals of the plurality of connectors and the device under test. The test modules are connected to the additional modules without through the performance board.

Abstract: A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern.

Abstract: A non-invasive Time Domain Reflectometry transmission line system and method for measuring one or more parameters of an electromagnetic Radio Frequency pulse transmitted, and reflected, along a transmission line, the parameters including at least one of; amplitude, propagation velocity and/or propagation time between defined predetermined instances. The system includes a transmission line structure including three or more elongated transmission elements each having two distal ends. Each element is capable of being selectively activated in at least two distinct pairs having distinct geometric configurations relative to each other to generate at least two distinct electric field potentials without physical displacement of the transmission line.

Abstract: Test structures, methods of manufacturing thereof, and testing methods for semiconductors are disclosed. In one embodiment, a test structure for semiconductor devices includes a printed circuit board (PCB), a probe region, and a compliance mechanism disposed between the PCB and the probe region. A plurality of wires is coupled between the PCB and the probe region. End portions of the plurality of wires proximate the probe region are an integral part of the probe region.

Abstract: A system, probe interface, and method to test an integrated circuit with an electrostatic discharge signal. The probe interface includes a pulse generation circuit, ground plane, and a relay matrix, while the integrated circuit includes a plurality of contact points. The probe interface is configured proximate to the integrated circuit and the relay matrix is configured to electrically connect at least one of an operative signal, the pulse generation circuit, or the ground plane to a contact point of the integrated circuit. The probe interface is thus configured to provide a shortened path for at least one of the electrostatic discharge signal from the probe interface to the integrated circuit, or to the ground plane from the integrated circuit. The probe interface may selectively electrically connect to up to about thirty-two contact points of the integrated circuit, while the system may include up to about four probe interfaces.

Abstract: Some of the embodiments of the present disclosure provide an integrated circuit (IC) chip comprising a die, a system on chip (SOC) coupled to the die, and an internal test engine included in the SOC and configured to test the die, wherein one or more components within the IC chip may be configured to be tested by an external test engine coupled to the IC chip. Other embodiments are also described and claimed.

Abstract: An improved system for capacitive testing electrical connections in a low signal environment. The system includes features that increase sensitivity of a capacitive probe. One feature is a spacer positioned to allow the probe to be partially inserted into the component without contacting the pins. The spacer may be a collar on the probe that contacts the housing of the component, contacts the substrate of the circuit assembly, or both. In some other embodiments, the spacer may be a riser extending beyond the surface of the sense plate that contacts the component, a riser portion of the component, or a combination of both. The spacer improves sensitivity by establishing a small gap between a sense plate of the probe and pins under test without risk of damage to the pins. A second feature is a guard plate of the probe with reduced capacitance to a sense plate of the probe. Reducing capacitance also increases the sensitivity of the probe.

Abstract: A plurality of inserts are anchored in holes or recesses in a probe head. Shafts are coupled to the inserts, and adjustable multi-part fasteners are attached to the shafts and to a stiffener. The multi-part fasteners are operated to move the shafts and couple the probe head, the stiffener, and other components of a microelectronic contactor assembly. In some embodiments, the inserts may be anchored in the probe head using an adhesive. In some embodiments, the probe head may comprise more than one major substrate, and the inserts may be anchored in either of the substrates.

Abstract: An embodiment of a probe card comprising: a probe base plate including a ceramic base plate and a plurality of conductive paths; and a plurality of contacts disposed on one face of the probe base plate and electrically connected to the conductive paths. The ceramic base plate may be provided with: a plurality of first layers having a heating element which generates heat by electric power and disposed at intervals in the thickness direction of the ceramic base plate; second layers each interposed between adjoining first layers; and a power supply path for supplying electric power for heating to the heating element.

Abstract: A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested.

Abstract: Provision of a probe device, a processing device and a probe test capable of performing an efficient wafer probe test. A probe device, comprising a plurality of measuring stages to which a plurality of probe cards for inspecting semiconductor wafers are connected, respectively; a first conveying portion for conveying a semiconductor wafer to a first measuring stage to which a first probe card is connected; a first inspection control portion for controlling the inspection of the semiconductor wafer by the first probe card; a receiving portion for receiving stage information including information showing nonuse of the first measuring stage from a processing device; a second conveying portion for conveying the semiconductor wafer to a second measuring stage, to which a second probe card different from the first probe card is connected, according to the received stage information; and a second inspection control portion for controlling the inspection of the semiconductor wafer by the second probe card.

Abstract: A microelectronic contactor assembly can include a probe head having microelectronic contactors for contacting terminals of semiconductor devices to test the semiconductor devices. A stiffener assembly can provide mechanical support to microelectronic contactors and for connecting a probe card assembly to a prober machine. A stiffener assembly may include first and second stiffener bodies that are connected together at their central portions with adjustment mechanisms such as three differential screw mechanisms. A probe head may be attached to a first stiffener body at locations outside its central portion, while a prober machine may be attached to a second stiffener body at locations outside its central portion. The first and second stiffener bodies may have different coefficients of thermal expansion.

Abstract: In an oscilloscope probe with a transistor amplifier constructed on a semiconductor substrate using integrated circuit technology, at least one part of the input-voltage divider is also constructed together with the amplifier using integrated-circuit technology on the semiconductor substrate.

Abstract: Embodiments of the present invention can relate to probe card assemblies, multilayer support substrates for use therein, and methods of designing multilayer support substrates for use in probe card assemblies. In some embodiments, a probe card assembly may include a multilayer support substrate engineered to substantially match thermal expansion of a reference material over a desired temperature range; and a probe substrate coupled to the multilayer support substrate. In some embodiments, the reference material may be silicon.

Abstract: An electronic device for use with a probe head in automated test equipment includes first and second pluralities of semiconductor devices. The first plurality of semiconductor devices is arranged to form at least one driver arranged to couple to a device under test. The at least one driver is configured to transmit a signal to the at least one device under test. The second plurality of semiconductor devices is arranged to form at least one receiver arranged to couple to the device under test. The at least one receiver is configured to receive a signal from the at least one device under test. Each of the second plurality of semiconductor devices has a thickness less than about 300 ?m exclusive of any electrical interconnects. The at least one receiver is adapted to mount directly to the probe head.

Abstract: A probe card of a semiconductor test apparatus having a plurality of space transformers supporting probe units of the probe card is provided. A probe card of the present invention includes a plurality of probe units, each comprising a guide member and at least one probe secured by the guide member and contacting a chip pad to be tested; a plurality of space transformers arranged below the respective probe units, each space transformer having wires electrically connected to lower terminals of the probes; a frame having a plurality of guide holes for fixedly positioning the respective probe units; an interposer array arranged below the space transformers for supporting the space transformers, interposer array comprising electrical connection means for supplying test signals to the wires of the space transformers; and a printed circuit board arranged below the interposer array for supporting the interposer array and electrically connected to the electrical connection means for supplying the test signals.

Abstract: Enhanced microfabricated spring contact structures and associated methods, e.g. such as for electrical contactors and interposers, comprise improvements to spring structures that extend from the substrate surface, and/or improvements to structures on or within the support substrate. Improved spring structures and processes comprise embodiments having selectively formed and etched, coated and/or plated regions, which are optionally further processed through planarization and/or annealment. Enhanced solder connections and associated processes provide a gap between substrates for componentry, and or improved manufacturing techniques using distributed spacers. Enhanced probe card assembly structures and processes provide improved planarization adjustment and thermal stability.

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Abstract: A universal system for testing different semiconductor devices provides a probe head with a probe pattern that may be used to test different test patterns formed on different semiconductor devices. Each of a plurality of bumps or pads of the test pattern contacts a corresponding probe of the probe head to enable the semiconductor device to be tested. The universal probe head may additionally or alternatively include a substrate design on the probe head that provides a pattern on the substrate of the probe head that may be used in conjunction with different patterns formed on a plurality of different printed circuit boards for testing different semiconductor devices.

Abstract: The present invention relates to a method for determining a status and/or condition of an LED/OLED device 10, comprising the steps of: applying at least one time varying signal 22 to the LED/OLED device, acquiring the response 24 to said at least one time varying signal, correlating said response with predetermined values 30, and determining the status/condition 32 on the basis of the correlation result. Further, the present invention relates to a device adapted to carry out the inventive method.

Abstract: A contactor includes conductive parts for electrical connection with input/output terminals of an IC device; beam parts with the conductive part provided on their main surfaces; and a base part supporting the beam parts in a cantilever manner, the base part has a support region supporting the beam parts and mark formation regions at which first positioning marks are provided, and weakened parts relatively weaker in strength than other parts of the base part are provided between the support region and mark formation regions.

Abstract: The present disclosure provides a probe card for wafer level testing. The probe card includes a space transformer having first power/ground lines and first signal lines embedded therein, wherein the first power/ground and signal lines are configured to have a first wiring pitch on a first surface and a second wiring pitch on a second surface, the second wiring pitch being substantially less than the first wiring pitch; a printed circuit board bonded to the first surface of the space transformer, wherein the printed circuit board includes second power/ground lines and second signal lines embedded in the printed circuit board and coupled to the first power/ground and signal lines; and conductive lines configured to a surface of the printed circuit board remote to the first surface of the space transformer, wherein each of the conductive lines includes a first end coupled to one of the second signal lines and a second end coupled to a different location of the printed circuit board.

Abstract: The invention discloses a testing system and a testing method, suitable for testing a DUT with double-sided signal pins. The testing system includes a testing platform and a pick-and-place device. The testing platform includes an electromagnetic shielding chamber and a test-bench module. The electromagnetic shielding chamber has an opening. The test-bench module is disposed in-between the electromagnetic shielding chamber. The pick-and-place device is movably disposed above the testing platform. The pick-and-place device includes an electromagnetic shielding cap and a signal transmission structure. When the pick-and-place device places the DUT on the test-bench module, the electromagnetic shielding cap cooperates with the electromagnetic shielding chamber of the testing platform to form an isolated space for isolating the DUT, and furthermore, the signal pin disposed on an upper surface of the DUT can be electrically connected to the test-bench module through the signal transmission structure.

Abstract: A probe head assembly for testing a device under test includes a plurality of test probes and a probe head structure. The probe head structure includes a guide plate and a template and supports a plurality of test probes that each includes a tip portion with a tip end for making electrical contact with a device under test, a curved compliant body portion and a tail portion with a tail end for making electrical contact with the space transformer. Embodiments of the invention include offsetting the position of the tail portions of the test probes with respect to the tip portions of the test probes so that the tip portions of the test probes are biased within the apertures of the guide plate, using hard stop features to help maintain the position of the test probes with respect to the guide plate and probe ramp features to improve scrubbing behavior.

Abstract: A display device and a method of testing the display device. The display device includes a substrate including both a display region on which pixel cells are located and a peripheral region; test pads, main pins connected to the pixel cells, and dummy pins that are respectively connected to the test pads, the test pads, the main pins, and the dummy pins being on the peripheral region of the substrate, and visual test lines on the peripheral region of the substrate. The visual test lines include a first portion connected to the main pins and a second portion connected to the test pads, and the first and second portions are disconnected from each other.

Abstract: A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The DPS has a second output stage coupled to the amplifier and configured to source and sink current to the output of the DPS between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Abstract: A tester may include a test head with a movable coupler, a probe card with a connector unit that is coupled with the coupler, and a needle block disposed on the probe card. In one example, the tester may test respective subsets of semiconductor devices on a wafer via a one-touch operation by moving a coupler on the test head, while the wafer remains in continuous and uninterrupted electrical contact with the tester during testing.

Abstract: A probe includes: a single base portion; a plurality of beam portions whose rear end sides are supported by the base portion and whose front end sides protrude from the base portion; and a plurality of conductive patterns formed on surfaces of the beam portions. At least a part of the plurality of beam portions has a beam bent portion which is bent in a direction inclined to or substantially perpendicular to a protruding direction of the beam portions.

Abstract: A test apparatus that test a device under test, comprising a test head that is arranged facing the device under test and that includes a test module for testing the device under test, and a probe assembly that transmits a signal and that is arranged between the test head and the device under test. The probe assembly includes a plurality of low voltage pins arranged at prescribed intervals from each other, and a plurality of high voltage pins that are arranged such that distance between each high voltage pin and each low voltage pin is greater than the prescribed interval, and that transmit a signal with a higher voltage than a signal transmitted by the low voltage pins. All of the high voltage pins are arranged in only one of two regions formed by dividing a surface of the probe assembly in half.

Abstract: Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer.

Abstract: A probe card includes a plurality of probes that contacts a plurality of electrodes provided in the semiconductor wafer and that inputs or outputs an electrical signal in or from the electrodes, a probe head that holds the probes, a substrate having a wiring which is provided near the surface of the substrate facing the probe head so as to be contactable with the probe head and is connected to the probes, a core layer formed of a material which is buried in the substrate and has a coefficient of thermal expansion lower than that of the substrate, and a connecting member that electrically connects at least some of the probes with an external device via the wiring.

Abstract: A method and system for testing a semiconductor package. At least some of the illustrative embodiments are methods comprising testing a semiconductor package unit (150, 420) by electrically coupling a top printed circuit board (208, 420) to a top-side of a semiconductor package unit (150, 420), the coupling using electrically conductive top-side pogo pins (201A, 420), and a pair of adjacent top-side pogo pins (201A, 420) bridged using an electrically conductive path (302, 420), electrically coupling a bottom printed circuit board (210, 430) to a bottom-side of the semiconductor package unit (150, 430), the coupling using electrically conductive bottom-side pogo pins (201B, 430), said top-side pogo pins (201A, 430) and said bottom-side pogo pins are of substantially equal height (201B, 430), and transmitting test signals from the bottom printed circuit board to the semiconductor device package by way of the bottom-side pogo pins (210, 440).

Abstract: A testing device of a semiconductor device includes a first board having a plurality of openings; a frame body provided in the openings, the frame body having a frame in which a plurality of probe needles is provided; and a plurality of second boards provided perpendicular to the first board in the periphery of the openings, the second boards being connected to the first board; wherein the probe needles pierce the frame so as to be connected to the second boards from the periphery of the frame body via the openings.

Abstract: The present disclosure provides a method for testing an integrated circuit having a load impedance. The method includes generating a first test signal having a first frequency and a second test signal having a second frequency, wherein the second frequency is greater than the first frequency, transmitting the first test signal to a substrate having a board circuit operable to process the first signal, transmitting the second test signal to a substrate, wherein the substrate includes an impedance matching circuit operable to transform the load impedance of the integrated circuit into a desired impedance for the second frequency, and sending the first and second test signals to the integrated circuit via the substrate.

Abstract: A probe card is provided which includes: probe needles electrically contacting input/output terminals of an IC device formed on a semiconductor wafer W; a mount base on which the probe needles are mounted; a support column supporting the mount base, a circuit board having interconnect patterns electrically connected to the probe needles via bonding wires; and a base member and stiffener for reinforcing the probe card. The mount base and the circuit board are noncontact.

Abstract: A probe wafer electrically connected to a semiconductor wafer on which a plurality of semiconductor chips are formed includes: a wafer substrate for pitch conversion including a wafer connection surface and an apparatus connection surface opposing the wafer connection surface; a plurality of wafer connection terminals formed on the wafer connection surface of the wafer substrate for pitch conversion, at least one wafer connection terminal provided for each of the semiconductor chips and electrically connected to an input/output terminal of the corresponding semiconductor chip; a plurality of apparatus connection terminals formed on the apparatus connection surface of the wafer substrate in one-to-one relation with the plurality of wafer connection terminals at an interval different from an interval of the wafer connection terminals, to be electrically connected to an external apparatus; and a plurality of transfer paths, each electrically connecting a corresponding wafer connection terminal to an apparatus co

Abstract: The invention relates to a probe card assembly comprising a stiffener (1), comprising a PCB (2) disposed in the stiffener (1), and comprising a spider (3) supported by the stiffener and the PCB (2), said spider comprising at least one probe (30) to test a wafer (5). This probe card assembly of the PCB (2) is supported in a loosely decoupled manner in the stiffener (1) to prevent transmission of high thermally-induced warping effects.