Abstract: A test controller switches the operation of output stages in an integrated circuit between a normal operation mode and a test mode. The output stages are respectively connected to switch elements. A level shifter generates a switch signal for controlling activation and deactivation of the switch elements in accordance with the normal operation mode and the test mode.

Abstract: A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.

Abstract: IDDQ testing of CMOS devices. An embodiment of a method includes applying a test pattern of inputs to a device, the device including one or more CMOS (Complementary Metal-Oxide Semiconductor) transistors, and obtaining current measurements for the device, each of the current measurements being a measurement of a current after applying an input of the test pattern to the device. A filter function is applied to the current measurements, applying the filter function including separating defect current values from the current measurements. The method further includes determining whether a defect is present in the device based at least in part on a comparison of the defect current values with a threshold value.

Abstract: A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.

Abstract: The invention relates to a tester apparatus of the kind including a portable supporting structure for removably holding and testing a substrate carrying a microelectronic circuit. An interface on the stationary structure is connected to the first interface when the portable structure is held by the stationary structure and is disconnected from the first interface when the portable supporting structure is removed from the stationary structure. An electrical tester is connected through the interfaces so that signals may be transmitted between the electrical tester and the microelectronic circuit to test the microelectronic circuit.

Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

Abstract: A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer.

Abstract: A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents.

Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract: A memory circuit includes an operational memory and a monitor circuit comprising a circuit element in the operational memory and/or a circuit element substantially identical to a corresponding circuit element in the operational memory. The monitor circuit is operative to measure at least one functional characteristic of the operational memory. A control circuit coupled to the monitor circuit is operative to generate a control signal which varies as a function of the measured characteristic of the operational memory. The memory circuit further includes a programmable voltage source coupled to the operational memory which is operative to generate at least a voltage and/or a current supplied to at least a portion of the operational memory which varies as a function of the control signal.

Abstract: An electronic component pressing device includes a first pressing member for pressing a predetermined first region of the electronic component to be tested; a second pressing member for pressing a predetermined second region other than the first region of the electronic component to be tested; a gimbal mechanism for adhering the first pressing member to the first region when the first pressing member presses the first region of the electronic component to be tested; first pressing load applying means for applying a pressing load on the gimbal mechanism; and second pressing load applying means for applying a pressing load on the second pressing member.

Abstract: A test system includes a computer and an interface device for accessing a scan chain on an application specific integrated circuit (ASIC) under test. The computer includes a memory that contains application software that when executed by the computer quantifies soft errors and soft error rates (SER) in storage elements on the ASIC. The interface device receives commands and data from the computer, translates the commands and data from a first protocol to a second protocol and communicates the commands and data in the second protocol to the ASIC. A method for measuring SER in the ASIC includes baseline, comparison, and latch up accesses of data in a scan chain in the ASIC. Between accesses, the ASIC is exposed to a neutron flux that accelerates the occurrence of soft errors due to ionizing radiation upon the ASIC.

Abstract: A method and apparatus for conducting transition testing using scan elements are disclosed. In one embodiment, an integrated circuit (IC) includes a scan chain having first and second subsets of scannable flops, the first subset having respective data inputs coupled to a memory array. The scannable flops of the second subset may each have a respective data input coupled to circuitry other than the memory array (e.g., to a logic circuit). The scannable flops of the first subset may be enabled for scan shifting during a transition test mode. The scannable flops of the second subset are inhibited from scanning during the transition test mode. The transition test mode may include at least two functional clock cycles in which the scannable flops of the first subset provide complementary first and second logic values to logic circuits coupled to respective data outputs.

Abstract: An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.

Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract: A test fixture (120) is disclosed for electrically testing a device under test (130) by forming a plurality of temporary mechanical and electrical connections between terminals (131) on the device under test (130) and contact pads (161) on the load board (160). The test fixture (120) has a replaceable membrane (150) that includes vias (151), with each via (151) being associated with a terminal (131) on the device under test (130) and a contact pad (161) on the load board (160). In some cases, each via (151) has an electrically conducting wall for conducting current between the terminal (131) and the contact pad (161). In some cases, each via (151) includes a spring (152) that provides a mechanical resisting force to the terminal (131) when the device under test (130) is engaged with the test fixture (120).

Abstract: Package (BT) for vacuum encapsulation of a microelectromechanical system (MEMS) provided with an electrically conductive element intended to be soldered to said package (BT), said package (BT) comprising a metallized base (FM), designed to be soldered to said microelectromechanical system (MEMS), and output electrical contacts (CES), electrically connected to electrical-contact elements of said microelectromechanical system. Said metallized base (FM) comprises a plurality of metallized surface portions (PSM), respectively bounded by an unmetallized solder stop region, and respectively connected to the rest of the metallized base (FM) by a metallized track (PTEM), having a small width relative to the corresponding width of said portion (PSM), said metallized surface portions (PSM) being designed to be soldered to said microelectromechanical system (MEMS).

Abstract: The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.

Abstract: Film frame assemblies and apparatus for testing and singulating integrated circuit packages, as well as associated methods for forming a film frame assembly, and testing and singulating integrated circuit packages are disclosed. A plurality of leads on a lead frame are cut to form singulated integrated circuit packages. Apparatus and methods are disclosed for mechanically aligning a set of electrical contacts attached to a contactor body with a plurality of leads on a singulated integrated circuit package.

Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

Abstract: A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit board from the integrated circuit package; performing a dye mapping to analyze bonds between the integrated circuit package and the circuit board; and performing an analysis of the integrated circuit package.

Abstract: An internal precision oscillator (IPO) is trimmed within a microcontroller integrated circuit. The microcontroller integrated circuit receives a test program into flash memory on the microcontroller integrated circuit from a tester. The microcontroller integrated circuit also receives a reference signal from the tester. The IPO generates a clock signal having a frequency that depends upon a trim value. A general purpose timer on the microcontroller integrated circuit counts the number of cycles of the clock signal during a time period defined by the reference signal and outputs a digital value. A processor on the microcontroller integrated circuit executes the test program, reads the digital output, and adjusts the trim value such that the frequency of the clock signal is calibrated with respect to the reference signal. Test-time on the tester is reduced because the decision making during the frequency trimming process is made by the processor instead of the tester.

Abstract: System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols.

Abstract: A driving circuit, which drives a display panel in a voltage range between a high negative voltage and a high positive voltage, includes: an electric charge discharging circuit; and a test external terminal. The electric charge discharging circuit connects a first terminal supplied with the high negative voltage to a second terminal of a ground voltage in response to a drop of a power source voltage. The test external terminal is connected to the electric charge discharging circuit. The high negative voltage is supplied to the semiconductor substrate. The electric charge discharging circuit interrupts a connection between the first terminal and the second terminal based on a control signal from the test external terminal.

Abstract: A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.

Abstract: A novel computer program product and method for thermally characterizing a device used for cooling an electronic device is disclosed. A cooling device, being operated, is thermally coupled to a heat pipe having a surface to receive a test chip. A heater is patterned on a circuitry side of the test chip. The heater is separate from operational circuitry of the test chip. A localized heat source is applied to at least one region on a test chip thermally coupled to the heat pipe to locally heat more than one region on a second surface of the test chip to test more than one hot spot. The second surface is the circuitry side of the test chip. The heater provides a bias heat to the test chip, independent of operating the test chip, while the localized heat source is selectively applied directly to the test chip. A temperature detector is used to measure a temperature distribution on the second surface of the test chip.

Abstract: A microelectronic contactor assembly can include a probe head having microelectronic contactors for contacting terminals of semiconductor devices to test the semiconductor devices. A stiffener assembly can provide mechanical support to microelectronic contactors and for connecting a probe card assembly to a prober machine. A stiffener assembly may include first and second stiffener bodies that are connected together at their central portions with adjustment mechanisms such as three differential screw mechanisms. A probe head may be attached to a first stiffener body at locations outside its central portion, while a prober machine may be attached to a second stiffener body at locations outside its central portion. The first and second stiffener bodies may have different coefficients of thermal expansion.

Abstract: A test structure (200) in an integrated circuit (100) includes a probe pad (210) disposed at a surface of a die (102) of the integrated circuit, a transmission gate (202) for connecting portions of an electronic circuit within the integrated circuit in response to a momentary signal applied to the probe pad, a first inverter (221) having an input coupled to the probe pad and having an output coupled to a control input of the transmission gate, and a second inverter (222) having an input coupled to an output of the first inverter and having an output coupled to another control input of the transmission gate. The output of the second inverter is coupled to the input of the first inverter. Upon power-up, the transmission gate is open. After the momentary signal is applied to the probe pad, the transmission gate closes and remains closed until power is disconnected.

Abstract: What is disclosed is an apparatus for determining the cooling characteristics of a cooling device used for transferring heat from an electronic device. The apparatus comprising a cooling device thermally coupled to a heat pipe. The heat pipe having an exposed surface for the selective application of heat thereon. A localized heat source is selectively applied to at least one region of the exposed surface. The heat source preferably capable of being varied both positionally relative to the exposed surface and in heat intensity. A heat shield is preferably positioned around the exposed surface of the heat pipe to isolate the operational cooling device from the localized heat source. A temperature detector repeatedly measures a temperature distribution across the exposed surface while the cooling device is in a heat transfer mode. The temperature distribution is then used to thermally characterize the cooling device.

Abstract: A test system tests a semiconductor integrated circuit. The semiconductor integrated circuit including a signal terminal to and from a signal is input and output, an RF circuit which processes an RF signal, and a capacitor which is connected between the signal terminal and the RF circuit. The test system has a probe which applies a test signal to the signal terminal and a tester which tests the RF circuit. Before the RF circuit is tested, with the probe and the signal terminal in contact with each other, the tester determines whether the probe and the signal terminal are in a conductive state.

Abstract: The device degradation of integrated circuits may be compensated for by appropriately adapting the duty cycle of the clock signal. For this purpose, a correlation between the duty cycle and the overall performance characteristics of the integrated circuit may be established and may be used during the normal field operation of the device in order to modify the duty cycle. Hence, an efficient control strategy may be implemented since the duty cycle may be efficiently controlled, while at the same time a change of clock signal frequency and/or an increase of supply voltage may not be required.

Abstract: A semiconductor package test apparatus having a test head and a test handler is provided. The semiconductor package test apparatus may include an insert in which a plurality of semiconductor packages are stacked and received in an offset fashion. Further, the semiconductor package test apparatus may include a plurality of sockets located adjacent to the insert and each of the inserts may have a plurality of socket pins. The sockets have different surface levels and are aligned with the semiconductor packages.

Abstract: A diagnosis board is electrically connected with a test apparatus for testing a device-under-test and used in diagnosing the test apparatus. The test apparatus has a test head containing test modules for sending/receiving signals to/from the device-under-test. The diagnosis board has a plurality of sub-boards arranged substantially on the same plane, substantially forming a plane as a unit, and connected with each part of a plurality of terminals of the test modules and used for diagnosing the connected terminals, each of the plurality of sub-boards having a plate-like shape. The diagnosis board also has a fixing section for attaching and fixing the plurality of sub-boards in a body to the test head.

Abstract: A life prediction wire 14 is connected to an emitter-wire bonding pad 2 of a semiconductor device 1. Wire deterioration is detected by checking whether or not an electric current flows from the life prediction wire 14 to the emitter-wire bonding pad 2. Thus, by directly checking a deterioration state of the semiconductor device, the life of the semiconductor device is predicted.

Abstract: A method and apparatus for determining dielectric layer properties are disclosed. Dielectric layer properties such as dielectric thickness, dielectric leakage or other electrical information may be determined for a multilayer film stack on a semiconducting or conducting substrate. The film stack may comprise a first dielectric layer between the substrate and an intermediate layer of semiconducting or conducting material, and a second dielectric layer disposed such that the intermediate layer is between the first and second dielectric layers. The dielectric layer properties may be determined by a) depositing electrical charge at one or more localized regions on an exposed surface of the second dielectric layer; b) performing a measurement of an electrical quantity at the one or more localized regions; and c) determining a property of the second dielectric layer from the one or more measurements.

Abstract: Open and short systems and methods for testing integrated circuits are disclosed. An example implementation includes engaging an integrated circuit testing module with an integrated circuit testing apparatus, the integrated circuit testing module for receiving an integrated circuit, a first set of contact points, and a second set of contact points; engaging a first probe onto at least one of the contact points of the first set of contact points, controllably engaging at least one of a second probe onto at least one contact pair of the integrated circuit testing module, and providing an electrical stimulus to the integrated circuit testing module.

Abstract: A system for making electrical contact between a transmit/receive module and a testing device for the transmission of high-frequency signals includes a mechanically guided, frame-shaped contacting unit having a plurality of contact elements for contacting the TR module. The contacting unit surrounds the T/R module and is positioned relative to the T/R module such that the contact with the T/R module is established in one operation via the contact elements. A line substrate, which is arranged on the contacting unit and electrically connected with it, is constructed as a shielded triplate line by which the high-frequency signals can be conducted to the testing device.

Abstract: A test circuit and system for testing one or more electrical properties of an electronic circuit or other device under test (DUT) by applying and monitoring test signals to the DUT is disclosed. The test circuit can utilize a plurality of universal interface channel circuits in a single automated test system to provide a unique and flexible approach for testing electronic circuits or devices that has many advantages. A single data acquisition circuit can be coupled to one or more universal interface channel circuits. Each of the universal interface channel circuits can be independently commanded by the data acquisition circuit to provide one of a variety of test signals to a DUT as desired.

Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Abstract: A heat sink assembly dissipates heat of a chip on a circuit board. A temperature collecting module of the heat sink assembly senses temperature of the chip and generates corresponding analog signals. A display module of the heat sink assembly receives the analog signals and converts the analog signals into digital signals, and then displays the digital signals with temperature unit symbol.

Abstract: A method and device for measuring a signal of a die to be placed within a package is disclosed. At least one die as a Device Under Test (DUT) is mounted on a substrate and a chip-type measurement instrument is mounted on the substrate, or embedded into the substrate, wherein the instrument analyzes and/or processes the signal of the DUT and may provide stimulus signal to the DUT. The substrate having the DUT and the measurement instrument is mounted on a circuit board that has plural electrodes to be connected to the signal paths of the DUT and the instrument. An electrode is coupled to a standard interface port to provide the signal of the chip-type instrument to an external instrument.

Abstract: A heater for heating packaged die for burn-in and heat testing is described. The heater may be a ceramic-type heater with a metal filament. The heater may be incorporated into the integrated circuit package as an additional ceramic layer of the package, or may be an external heater placed in contact with the package to heat the die. Many different types of integrated circuit packages may be accommodated. The method provides increased energy efficiency for heating the die while reducing temperature stresses on testing equipment. The method allows the use of multiple heaters to heat die to different temperatures. Faulty die may be heated to weaken die attach material to facilitate removal of the die. The heater filament or a separate temperature thermistor located in the package may be used to accurately measure die temperature.

Abstract: Provided is a test apparatus for testing a device under test, including a multi-strobe generating section that generates, for each prescribed test cycle, a multi-strobe that includes a plurality of strobes arranged at prescribed time intervals, a data detecting section that detects a logic value of a response signal output by the device under test, according to each strobe, and a data width detecting section that detects a data width indicating a period during which the logic value of the response signal matches a prescribed expected value, based on each change point of a logic value output by the data detecting section.

Abstract: A stacked semiconductor device is disclosed which is capable of conducting a test to determine whether or not there is continuity between an external terminal and a corresponding internal terminal in each chip, on an internal terminal-in each chip basis. The semiconductor device includes continuity test dedicated terminals for each chip, and continuity test elements each connected between an internal terminal in each chip and a continuity test dedicated terminal associated with the chip. A voltage is applied between an external terminal associated with an internal terminal whose connection status is to be checked and a continuity test dedicated terminal associated with a chip which includes the internal terminal such that a continuity test element associated with the internal terminal is rendered conductive. Thereafter, the value of current that flows through the continuity test element is measured to determine the connection status of the internal terminal.

Abstract: An integrated circuit die includes first and second test data inputs, a test data output, and a test arrangement for testing the integrated circuit die. The test arrangement includes a multiplexer coupled to the first and second test data inputs, a further multiplexer coupled to the test data output, a plurality of shift registers including an instruction register, each of the shift registers being coupled between the multiplexer and the further multiplexer, and a controller for controlling the multiplexers in response to the instruction register. Such a test arrangement facilitates JTAG compliant testing of a system in package (SiP) by providing a direct connection between the SiP test data input pin and the second test data input of the IC die, and the SiP test data output pin and the test data output of the IC die, thus facilitating the bypassing of other test arrangements in the SiP.

Abstract: A semiconductor arrangement has a semiconductor body (CP), comprising a semiconductor layer (HL) with a first (AB11, AB12) and at least one second (AB21, AB22) conducting terminal areas, respectively made in two parts, and with a first (TAB1) and a second (TAB2) test terminals; a first (KI1, KU1) and at least one second (KI2, KU2) contact areas, located on the semiconductor body (CP) and made of two parts, which are connected with the respective terminal areas (AB11, AB12; AB21, AB22), and a first (TK1) and a second (TK2) test contact areas that are connected with the respective test terminal areas (TAB1, TAB2); a first terminal (10) that can be arranged on the semiconductor body (CP) and that contacts both parts of the two-part first contact areas (KI1, KU1), and at least one second terminal (20) that can be placed on the semiconductor body (CP) and that contacts both parts of the at least one second two-part contact area (KI2, KU2), and a first (30) and a second (40) test terminals, which can be arranged on

Abstract: An integrated circuit includes a monitoring-target circuit portion 1200 and a debugging circuit portion 1100. The debugging circuit portion 1100 acquires a signal on a signal line of the monitoring-target circuit portion 1200 and transmits the acquired signal to an external device 2000 by radio. The debugging circuit portion 1100 includes a setting unit 1120 and a radio transmitter 1140. In order to monitor the monitoring-target circuit portion 1200, the setting unit 1120 sets an isolation unit 1300 so as to make electrical connection between the debugging circuit portion 1100 and the monitoring-target circuit portion 1200. In addition, the setting unit 1120 sets a selector 1130 to select a signal line 1131 specified as a monitoring target. The radio transmitter 1140 acquires a signal on the signal line selected by the selector 1130 and transmits the acquired signal to the external device 2000 by radio.

Abstract: A measurement apparatus that detects a defect in a device based on the quiescent current (IDDQ) of a CMOS LSI or the like detects the defect by measuring the value of IDDQ that flows when a logic vector is applied. However, the miniaturization of CMOS LSIs has caused an increase in the leak current flowing through a normal CMOS circuit. This makes it difficult to distinguish between the power supply current flowing in a defective CMOS circuit and the leak current flowing through a normal CMOS circuit. By applying the logic vector after suppressing the fluctuation of the leak current by controlling the power supply voltage applied to the device under measurement and the voltage applied to the substrate of the device under measurement, the measurement apparatus of the present invention can measure the power supply current flowing through a defective CMOS circuit to detect the defect in the CMOS circuit.

Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.

Abstract: A semiconductor integrated circuit includes: a ladder resistor; a ROM decoder; and a test circuit. The ladder resistor includes a plurality of resistors series-connected to each other and is supplied with a correction voltage at least one of both ends of the series connection and a plurality of connection points in the series connection to generate a plurality of gradation voltages at the plurality of connection points. The ROM decoder selects one of the plurality of gradation voltages generated by the ladder resistor, based on a supplied data signal. The test circuit measures a leakage current in the ROM decoder. The test circuit includes: a plurality of separation units, and a control unit. The plurality of separation units separates the series connection, which is respectively supplied with different power source voltages at both ends, at a certain portion, when the leakage current is measured. The control unit controls separation of the plurality of separation unit corresponding to the data signal.