Abstract: An apparatus for supporting BGA packages for one or more testing processes is disclosed. The apparatus includes a substrate member. The substrate member has a plurality of contact pads, with each of the contact pads being spatially disposed around a peripheral region of the substrate. The apparatus further includes a plurality of contact regions spatially configured on a portion of the substrate member. Each of the plurality of contact regions is numbered from 1 through N being electrically connected to respective contact pads numbered from 1 through N. The plurality of contact regions is configured to provide electrical contact to respective plurality of balls provided on a BGA package. The apparatus additionally includes a holder device coupled to the substrate member. The holder device is adapted to mechanically hold the BGA package in place to provide mechanical contact between the plurality of balls and respective plurality of contact regions.

Abstract: A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal.

Abstract: A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.

Abstract: A test apparatus for an electronic device package is provided, which includes a test socket having a first portion with a recess for receiving an electronic device package having external terminals arranged in a terminal configuration and a second portion. An interchangeable insert board is disposed between the first portion and the second portion and extended on the recess, which includes first contact pads arranged in a first pad configuration compatible with the terminal configuration and facing the recess and second contact pads arranged in a second pad configuration and disposed between the first and the second portions. Trace layers each electrically connects one of the first contact pads to one of the second contact pads. The contact pins each penetrates through the second portion and electrically connects to one of the second pads, wherein the contact pins are arranged in a pin configuration compatible with the second pad configuration.

Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.

Abstract: A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i?1)/N×2?. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

Abstract: Over the air or radiated testing of an RF microelectronic or integrated circuit device under test (DUT) that has an integrated millimeter wave (mmw) antenna structure, is described. The antenna structure may have multiple elements in an array design that may be driven and/or sensed by integrated RF transmitter and/or receiver circuitry. An interface printed wiring board (e.g., a tester load board or a wafer probe card assembly) has formed in it a mmw radiation passage that is positioned to pass mmw radiation to and/or from the integrated antenna of the DUT. Test equipment may be conductively coupled to contact points of the interface board, to transmit and/or receive signals for testing of the DUT and/or provide dc power to the DUT. A test antenna is designed and positioned to receive and/or transmit mmw radiation through the passage, from and/or to the integrated DUT antenna. Other embodiments are also described and claimed.

Abstract: A circuit testing apparatus for testing a device under test is disclosed. The device under test comprises a first output end and second output end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines a test result for the device under test according to the first output signal and the second output signal.

Abstract: Systems and methods for providing self-healing integrated circuits. The method is characterized in that the behavior of a circuit or a device in response to an input signal is observed. One or more operational parameters or characteristics of the circuit or the device are derived. A corrective action to bring the operational parameters or characteristics of the circuit or device within a desired range is deduced, if needed. The corrective action can be the application of a correction signal or a modification of one or more parameters or characteristics of an element in the circuit. The calculated corrective action, if needed, is applied to bring the operational parameters or characteristics of the circuit or device within the desired range. Optionally, the operational parameters or characteristics of the circuit or the device after the correction is effectuated can be checked.

Abstract: Electrical circuit apparatus and methods including hermeticity testing structures for testing the hermeticity of the electrical circuit apparatus.

Abstract: A test controller switches the operation of output stages in an integrated circuit between a normal operation mode and a test mode. The output stages are respectively connected to switch elements. A level shifter generates a switch signal for controlling activation and deactivation of the switch elements in accordance with the normal operation mode and the test mode.

Abstract: A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.

Abstract: In one embodiment, a power supply controller is configured to operate in a test mode that facilitates measuring the value of an output signal of an error amplifier of the power supply controller.

Abstract: A socketless integrated circuit (IC) contact connector is provided with an electrically conductive support post. An electrically conductive spring has a first end connected to the post, and a second end. An electrically conductive first wire has a first end connected to the spring second end, and a second end. An electrically conductive loop with a loop neck is connected to the first wire second end. Typically, the loop is formed in the first wire second end. The spring and loop work in cooperation to engage an IC contact.

Abstract: An integrated circuit (IC) that includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC is provided. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface.

Abstract: The present invention provides on IC test substrate for testing various signals, a combined flexible and rigid PCB included in the structure is applicable to perform a mission including for example: stabilizing power input/output, signal transfer by a connector; general, power, and high frequency signal transmission in preserved integrity state.

Abstract: The present invention provides a method. The method includes operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC).

Abstract: A time-to-breakdown for a dielectric layer in a semiconductor device is determined based upon a sudden change in capacitance. An alternating voltage, greater in magnitude than an operating voltage of the device, is applied to the semiconductor device, capacitance is measured across the dielectric layer during the application of the voltage until a sudden change in capacitance occurs, thereby indicating a breakdown in the dielectric layer, and the breakdown time is scaled to the operating voltage.

Abstract: An inspection method includes performing an inspection by applying a probe to pads of a contact check pattern located, together with a chip pattern, on a wafer, and performing an inspection by applying the probe to pads of the chip pattern if a result of the inspection using the contact check pattern is within a predetermined range. A pattern having the same size as that of the chip pattern, differing in external appearance from the chip pattern, and having the same pads as those of the chip pattern is used as the contact check pattern.

Abstract: Electrical circuit apparatus and methods including hermeticity testing structures for testing the hermeticity of the electrical circuit apparatus.

Abstract: An internal precision oscillator (IPO) is trimmed within a microcontroller integrated circuit. The microcontroller integrated circuit receives a test program into flash memory on the microcontroller integrated circuit from a tester. The microcontroller integrated circuit also receives a reference signal from the tester. The IPO generates a clock signal having a frequency that depends upon a trim value. A general purpose timer on the microcontroller integrated circuit counts the number of cycles of the clock signal during a time period defined by the reference signal and outputs a digital value. A processor on the microcontroller integrated circuit executes the test program, reads the digital output, and adjusts the trim value such that the frequency of the clock signal is calibrated with respect to the reference signal. Test-time on the tester is reduced because the decision making during the frequency trimming process is made by the processor instead of the tester.