Abstract: Technology for editing PLD code to be programmed into a PLD are provided. The technology includes an interface, a storage system, and a processing system configured to obtain a PLD code, with the PLD code comprising one or more logic instruction blocks and corresponding block parameters for each logic instruction block, with the PLD code being intended for programming into the PLD, compare the one or more logic instruction blocks of the PLD code to a subset of the library of logic instruction blocks applicable to the PLD according to the library of PLD devices, determine inconsistent logic instruction blocks of the one or more logic instruction blocks, indicate the inconsistent logic instruction blocks, and correct the inconsistent logic instruction blocks using the subset of the library of logic instruction blocks.

Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.

Abstract: Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port. The cross-coupled inverters in each memory cell may have a positive power supply terminal. The positive power supply terminal of each memory cell along a given column in the array may be coupled to a corresponding pull-up transistor. The pull-up transistor may receive a control signal from a pull-up weakening control circuit. The control signal may be temporarily elevated during write operations and may otherwise be driven back down to ground to help optimize read performance. The pull-up weakening control circuit may be implemented using a chain of n-channel transistors or a resistor chain.

Abstract: A semiconductor memory device to which a Peri Under Cell (PUC) structure is applied is disclosed. The semiconductor memory device includes a word line multilayered structure formed in a cell region, and extending from across the cell region; and a slimming region including a step-shaped pad structure in the word line multilayered structure.

Abstract: A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic. At least four logic elements may be interconnected with diagonal direct links.

Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.

Abstract: A programmable integrated circuit, includes an external port, a configuration memory, a hardened write path between the external port and the configuration memory and a soft read path between the configuration memory and the external port, wherein configuration data stored in the configuration memory is only read through the soft read path.

Abstract: Systems and methods for configuring circuitry for use with a field programmable gate array (FPGA) are disclosed. The circuitry includes an array of signal processing accelerators (SPAs) and an array of network nodes. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input signals from the FPGA. The array of network nodes controllably route the input signals to the array of SPAs.

Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract: Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second wire segment. An intersection element of the first bundle and the second bundle includes a first interconnecting wire segment that connects the first wire segment and the second wire segment, and the input signal is routed from the first wire segment to the second wire segment via the first interconnecting wire segment. The input signal is further transmitted to the second element from the second wire segment.

Abstract: An adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations.

Abstract: An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device.

Abstract: Techniques and mechanisms disclosed herein provide a partial reconfiguration bitstream for a region of configurable logic of a programmable logic device over a communications interface such as the Peripheral Component Interconnect Express (PCIe) protocol.

Abstract: A Bluetooth pairing method is provided which includes connecting a mobile terminal and an infotainment system of a vehicle by a wired connection. The method also includes executing a dedicated APP (application) for a Bluetooth pairing disposed in the mobile terminal by a controller disposed in the infotainment system. Information regarding the infotainment system for the Bluetooth pairing is transmitted to the dedicated APP by the controller and the information is stored to a NFC (Near Field Communication) tag by the dedicated APP.

Abstract: Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects.

Abstract: A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included.

Abstract: A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the transistor is connected to one electrode of a capacitor and the input of an inverter, and a source is connected to a first wiring. The other electrode of the capacitor is connected to a second wiring. In such a memory element, the potential of the second wiring is complementary to the potential of the first wiring when writing data; accordingly, the potential of the drain of the transistor, i.e., the potential of the input of the inverter can be higher than the high potential of the inverter. Thus, shoot-through current of the inverter at this time can be significantly reduced. As a result, power consumption in a standby state can be significantly reduced.

Abstract: The present invention provides a method for reusing and verifying electronic circuits, including the following steps of comparing company part numbers of new circuit design with company part numbers of previous circuit design; determining whether the company part numbers of the new circuit design are identical to the company part numbers of the previous circuit design; reporting the same company part numbers between the new circuit design and the previous circuit if the company part numbers of the new circuit design are identical to the company part numbers of the previous circuit design; determining whether the circuit fingerprints of the new circuit design match the circuit fingerprints of the previous circuit design; and verifying and reporting that the previous circuit design is reused in the new circuit design if the circuit fingerprints of the new circuit design match the circuit fingerprints of the previous circuit design.

Abstract: Various embodiments of the invention allow to effectively reduce device and system power consumption in both active and inactive modes without compromising performance, without large area overhead, and at low cost. In certain embodiments, the reduction of power consumption is accomplished by combining circuit control techniques with power gating methods to reduce power loss due to leakage current.

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

Abstract: A switch device includes: a first electrode; a second electrode arranged to face the first electrode; and a switch layer provided between the first electrode and the second electrode. The switch layer includes a first layer containing a chalcogen element, and a second layer containing a high resistance material.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: Invention provides an apparatus and method for performing signal processing on a crossbar array of resistive memory devices. The invention is implemented using one or multiple crossbar arrays of resistive memory devices in conjunction with devices for converting input real number representations to voltage waveforms, devices for converting current waveforms into voltage waveforms, and devices for converting voltage waveforms to real numbers outputs.

Abstract: Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.

Abstract: An integrated circuit for configuring and reconfiguring a configuration shift register (CSR) partial reconfiguration region is disclosed. The integrated circuit includes a CSR chain that is partitioned into a group of CSR partial reconfiguration regions. A multiplexer circuit is added to the end of each PR region to allow the PR region to be bypassed or connected to the next PR region. Each PR region is connected to a PR circuit that facilitates the CSR configuration of the respective PR region. The PR circuit includes region enable circuitry and region control circuitry. Region enable circuitry enables the configuration of the CSR PR region. Region control circuitry generates local reconfiguration control signals to control the configuration operation of the enabled CSR PR region.

Abstract: Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Abstract: A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Abstract: A unit of information technology equipment (ITE), such as a compute node or a network switch, comprises a system board in communication with network connectors that selectively connect to a network interconnect, a gravity sensor for detecting a first orientation and a second orientation of the system board, and a basic input/output system (BIOS) in communication with the gravity sensor to receive a signal identifying whether the system board is in the first or second orientation. The ITE further comprises a network ASIC (application specific integrated circuit) that inverts the pinout of transmit and receive signals in the network connectors in response to a command from the BIOS indicating that the system board is in the second orientation. A system may comprise a first ITE in a first orientation that interlocks with a second ITE in a second orientation that is inverted 180 degrees from the first orientation.

Abstract: A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

Abstract: A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells.

Abstract: Disclosed is a system in which in order to obtain the operation parameter of a circuit based on an implementable area indicating a circuit scale that can be implemented on a circuit implementation device, circuit area information, and operation parameter measuring circuit area information, an observation signal number determining means determines observation signal information on a circuit that obtains the operation parameter of the circuit. The number of the extracted signals is determined in view of the area that can be implemented on a digital LSI or an emulator and the area of the circuit to be implemented (refer to FIG. 1).

Abstract: A method for correcting a distorted input image comprises determining a local region of an image to be displayed and dividing said region into an array of rectangular tiles, each tile corresponding to a distorted tile with a non-rectangular boundary within said input image. For each tile of the local region, maximum and minimum memory address locations of successive rows of said input image sufficient to span said boundary of said distorted tile are determined. Successive rows of the distorted input from between said maximum and minimum addresses are read. Distortion of the non-rectangular portion of said distorted input image is corrected to provide a tile of a corrected output image which is stored.

Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Abstract: A method for correcting a distorted input image includes determining a local region of an image to be displayed and dividing the region into an array of rectangular tiles, each tile corresponding to a distorted tile with a non-rectangular boundary within the input image. For each tile of the local region, maximum and minimum memory address locations of successive rows of the input image sufficient to span the boundary of the distorted tile are determined. Successive rows of the distorted input from between the maximum and minimum addresses are read. Distortion of the non-rectangular portion of the distorted input image is corrected to provide a tile of a corrected output image which is stored.

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

Abstract: The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address.

Abstract: Methods and apparatus are provided for allowing components such as buffers, multiplexers, ingress cores, etc. on a device such as a programmable chip to configure themselves based on parameter information. In some examples, self-configuring components obtain parameter information from adjacent components. In other examples, self-configuring components obtain parameter information from a system environment or a processor register. Component self-configuration can occur at a variety of times including preprocessing, simulation, and run-time.

Abstract: A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit that is part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that loaded data is properly locked, to prevent overwrites. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration. The invention also provides for splitting the single FLU into multiple independent reconfigurable FLU sections, with independent user clock and reset, for implementing a plurality of independent functions or for establishing redundancy for critical functions.

Abstract: Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.

Abstract: An architecture for a specialized electronic computer for high-speed data lookup employs a set of tiles each with independent logic elements lookup memory portions. The tiles may each comprise gate-array-like functional units that may be wired together by a multi-way switch for extremely low latency.

Abstract: A system and method for routing a buffered interconnect in an IC from a source cell to a target cell thereof. In one embodiment, the system includes: (1) a path tracer operable to designate the source cell as a current node and construct a path toward the target node by: (1a) defining a boundary about the current node based on a buffer driving length, (1b) trimming the boundary by any blockage therein to yield a candidate area for placing a buffer, (1c) dividing the boundary into line segments, (1d) selecting a closest, valid one of the line segments to the target cell as the current node and (1e) repeating the defining, trimming, dividing and selecting the closest, valid one until the current node lies within the buffer driving length and (2) a buffer placer associated with the path tracer and operable to select a location along the path to place the buffer.

Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. In one embodiment clock signal selection system includes an arbitration component, a control component, and a selection component The arbitration component coordinates arbitration eligibility between a plurality of clock signals. The control component controls the coordination utilizing a clock signal from the plurality of clock signals. The selection component selects between the plurality of signals.

Abstract: A system for machine cognition includes Kanban cells (KC), Kanban cell neurons (KCN), and Kanban cell neuron networks (KCNN). The KC is an asynchronous AND-OR gate without feedback that is self-timing by the input data to process until input is equal to output. Input is a four-valued logic (4VL) based on the set {contradiction, true, false, tautology} of four-valued bit code (4vbc) where contradiction is equivalent to null. Access to a sparsely filled look up table (LUT) is minimized in hardware with a 2-bit value per logical signal.

Abstract: Integrated circuits may include embedded logic analyzer circuitry that monitors and stores data received from logic circuitry. The logic analyzer circuitry may include storage circuitry and logic analyzer control circuitry that controls the storage circuitry. The control circuitry may include trigger condition circuitry that compares the data to a trigger condition. When the data satisfies the trigger condition, the storage circuitry may stop storing the data and stored data may be conveyed to fault detection circuitry for debugging the design of the logic circuitry. The integrated circuit may include programmable memory elements that can be loaded with configuration data. The logic analyzer circuitry may include partial-reconfiguration control circuitry that reconfigures the control circuitry without reconfiguring other portions of the integrated circuit.

Abstract: An FPGA has a number of CLBs, each CLB having a number of CABs (10, 110, 210, 310, 410). Each CAB (10, 110, 210, 310, 410) comprises: a number of configurable transistors (20, 120, 220, 320, 420) each comprising one or more useable transistors M and a number of switching transistors; and, configuration circuitry comprising a number of switching transistors. The ratio of switching transistors to useable transistors for each CAB is less than 26:1. A method of configuring such an FPGA comprises optimizing each configurable transistor.