Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or more lines terminated by the termination circuitry, shunting current from the termination voltage supply and through the termination voltage delivery network in response to a second signal on one or more terminated lines, and helping to reduce the shunted current for extended shunting.

Abstract: An input/output buffer comprises an input/output pad operable to receive an input signal and transmit an output signal, an output driver coupled to the input/output pad, an input path comprising an input transistor coupled to the input/output pad operable to pass an input signal received at the input/output pad to a core circuit coupled to the input/output buffer. The input/output buffer further comprises an output path coupled to the output driver operable to pass an output signal received from the core circuit to the input/output pad, a feedback path coupled to the input transistor in the input path and operable to cut off the output path during input mode, and a biasing circuit coupled to selected transistors in the output path, feedback path and output driver.

Abstract: A method and apparatus for an output buffer with dynamic impedance control have been disclosed.

Abstract: An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto.

Abstract: The invention relates to a driver circuit with a circuit node (10), at least two first transistors (P1, P2), the load sections of which are switched in series and connect the circuit node (10) with a first voltage (U10), at least two second transistors (N1, N2), the load sections of which are switched in series and connect the circuit node (10) with a reference potential, and a control circuit (P3–P6, N3, D1–D4, R1, 16), which is formed in order to regulate at least a first control voltage (Up2) on at least one transistor (P2) of the at least two first transistors (P1, P2) and at least a second control voltage (UN2) on at least one transistor (N2) of the at least two second transistors (N1, N2) dependent on a voltage at the circuit node (10).

Abstract: In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1? are connected in series between a high-level potential HL and an output terminal U1; an NMOS transistor N1 and an NMOS transistor N1? are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1 is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1 is inputted to the gate of the PMOS transistor P1? through an inverter IV1; a clock signal Ck2 is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2 is inputted to the gate of the NMOS transister N1? through an inverter IV2.

Abstract: An output buffer circuit including a programmable impedance buffer configured to match a buffer size thereof with an external impedance, a buffer size decision circuit configured to generate a plurality of buffer size signals for determining the buffer size of the programmable impedance buffer synchronized with a first clock signal, and an impedance adjustment circuit configured to adjust the buffer size based on the buffer size signals in response to a level of an output data signal.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the circuit configurations. The respective circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.

Abstract: An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.

Abstract: The present invention provides a novel method for monitoring the reaction kinetics of the biodegradable polymers, and the surface concentration of a drug in a polymer blend matrix. Detailed information on surface concentration, degradation rates, degradation kinetics and mechanism, is provided by using Time-of-Flight Secondary Ion Mass Spectrometry (ToF SIMS) measurements. Also provided is a method for determining oligomers in hydrolyzed biodegradable polymers.

Abstract: An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a delay unit for processing one of the bit signals into a delayed bit signal with an adjustable delay period in response to a delay signal, a pull-up unit electrically connected to the delay unit and a source voltage, and selectively enabled to output the delayed bit signal as a high level, and a pull-down unit electrically connected to the delay unit and a ground voltage, and selectively enabled to output the delayed bit signal as a low level. The comparator is electrically connected to the N counts of output buffers, compares the N counts of bit signals sampled at a first time spot and a second time spot, and generates the delay signal according to the comparing result.

Abstract: An input and output circuit of a semiconductor device is disclosed having an output buffer including first and second pull-up transistors connected in series between the power supply voltage and the pad, first and second pull-down transistors connected in series between the pad and the ground voltage, a pre-driver for pulling up or down a voltage of the pad when an output enable signal is enabled and for switching off the first and second pull-up transistors and the first and second pull-down transistors when the output enable signal is disabled, and a first circuit for adjusting voltage differences between respective gates and respective sources/drains of the first and second pull-up transistors and the first and second pull-down transistors to be below a predetermined voltage level in response to the first, second and third control signals under power on or power off conditions; and an input buffer including a transmission gate for transmitting an input signal applied to the pad to a first node in response

Abstract: Area-efficient power-up and enable control circuits useful in PLD interconnection arrays. A control circuit can include a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to a control circuit output terminal. The first and second pull-ups are coupled in series between the control circuit output terminal and power high. The first pull-up has a gate terminal coupled to an enable terminal. The second pull-up has a gate terminal coupled to a pull-up control terminal. The first and second pull-downs are coupled in parallel between the control circuit output terminal and ground. The first pull-down has a gate terminal coupled to the enable terminal. The second pull-down has a gate terminal coupled to a pull-down control terminal. In other embodiments, the first and second pull-ups are coupled in parallel, and the first and second pull-downs are coupled in series.

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal, (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

Abstract: An output drive circuit is constructed by an output driving MOS transistor driving an output node in accordance with an internal read data, a termination controlling P-channel MOS transistor selectively rendered conductive in accordance with the internal read data when the output driving MOS transistor is non-conductive, and a P-channel MOS transistor rendered conductive to pull up the output node to a power supply voltage level at least when the output drive circuit is inactive. Data transfer is executed in an open drain manner, and the P-channel MOS transistor is utilized as a transistor for termination bus line. Data/signal is transferred fast in an active termination scheme with low current consumption, and an area occupied by the output drive circuit is reduced.

Abstract: The present invention relates to an input/output node in an electronic device which comprises an input/output pin, a plurality of programmable pull-up resistors and a plurality of programmable pull-down resistors. Each of the pull-up and pull-down resistors, or a combination of them, can be activated by turning on or off n-MOS and p-MOS transistors with logic contained in a mode register. The pull-up and pull-down resistance can be implemented by the inclusion of a resistor in series or by utilization of the innate resistance of the MOS-FET transistor, itself. The resistances can be strong, medium, or weak, depending on the needs of the circuitry. One advantage of such control over drive strength is the ability to transmit or receive data in virtually any electronic environment. Another advantage is the ability to reduce voltage ramp-rates, which reduces high frequency harmonics and the attendant electromagnetic interference.

Abstract: A computer system contains a small computer standard interface (SCSI) having a plurality of components to interface a plurality of external peripheral devices to the computer system in accordance with a SCSI specification. Within the computer system, the SCSI interface contains a SCSI bus having an internal SCSI terminator at an internal end of the SCSI bus, and an internal switchable SCSI terminator at an external end of the SCSI bus. The SCSI bus permits expansion beyond the computer system enclosure at the external side of the SCSI bus via an external connector and cable to interface external SCSI peripheral devices to the computer system. The internal switchable SCSI terminator senses whether any external SCSI external peripheral devices or an external terminator are attached to the SCSI bus. If external SCSI peripheral devices and/or an external terminator are attached to the SCSI bus, then the internal switchable SCSI terminator does not terminate the SCSI bus on the external side.

Abstract: An output buffer circuit 1 comprises an output transistor section 10, a first and a second driving means 40, 50, and a first and a second switch circuits 60, 70. The output transistor section 10 comprises PMOS 11, 13, and NMOS 12, 14. Each source terminal of the PMOS 11, 13 is connected to VDD, each source terminal of the NMOS 12, 14 is connected to GND, and each drain terminal of the PMOS 11, 13 and NMOS 12, 14 are all connected to an output terminal N1 of the output buffer circuit 1. The driving capability of the PMOS 13 is set to be larger than that of PMOS 11, and the driving capability of the NMOS 14 is set to be larger than that of NMOS 12.

Abstract: The present invention relates to a duty cycle adaptive data output buffer of a semiconductor device in which the current driving power of the output buffer is adaptively varied with a duty cycle, to effectively improve noise margin at slow duty cycle. The duty cycle adaptive data output buffer disclosed includes first and second pull-up transistors connected between a power supply voltage and an output terminal; first and second pull-down transistors connected to the output terminal and a ground; duty cycle detector for receiving a duty clock signal, to generate a first control signal at faster duty cycle, and to generate a second control signal at slower duty cycle; a first output driver for driving the first pull-up and pull-down transistors using first and second data signals in response to the first control signal; and a second output driver for driving the second pull-up and pull-down transistors using the first and second data signals in response to the second control signal.

Abstract: A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to provide two inverted outputs. The transistor arrangement of these two parts provides an equal delay to the two signal paths. The outputs of these two parts are sent to identical output buffers. Because the two paths have identical transistor delays, and since the metal paths on the board are arranged to have identical delays, the two paths can very low skew therebetween.

Abstract: Circuit techniques provide different trip points for a rising-edge and for a falling-edge input to a logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. Different circuit topologies are provided for delay chains on integrated circuits. Each implementation allows flexibility in delay elements through metal options to allow modifying delay chain delays with simple metal-only layout changes. Delay chains are used in integrated circuits to produce either a constant delay or to track another circuit delay.

Abstract: A static logic circuit with a pull-up network (155) and a pull-down network (160). The network is fabricated on SOI substrates and the pull-up network comprises at least one NMOS transistor (115) and the pull down network comprises at least one PMOS transistor (120).

Abstract: Embodiments of the invention include an integrated circuit output buffer, with a pre-drive stage and an output driver stage, that provides linear performance independent of the load impedance. The output driver stage includes a pull-up resistor arrangement having a plurality of branches connected in parallel and, alternatively at least one pull-down resistor arrangement having a plurality of branches connected in parallel. The branches of the pull-up resistor arrangement include at least one resistor and at least one transistor serially connected between a supply voltage and the output buffer output terminal connectable to the PAD external to the output buffer. The transistor in the pull-up arrangement is connected to both the data terminals from the pre-drive stage and the control bit terminals.

Abstract: Output drivers preferably contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively. Driver circuits may include first and second control signal lines (e.g., MRS1, MRS2), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS1) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS2) and a second control input. First and second complementary control signals lines (e.g.

Abstract: A switching device includes a phase controlling circuit (801) which shifts and outputs a phase of a command signal, and a plurality of switching units (110) connected in parallel between a power supply (101) and a load (102).

Abstract: A multi-function output driver that may be used with at least two types of busses includes a multiplexer that shifts calibration bits to the pull-down transistors. This shifting changes which transistors of the transistor array are turned on when the pull-down drive transistors are driving. By changing which transistors are turned on, the impedance of the driver is changed. This shifting is used with a disable function on the pull-up drive-transistors to allow the driver to be used as an end-of-line termination, an open-drain driver, or as a source-terminated driver.

Abstract: Ground bounce and power supply bounce are reduced in an output driver by utilizing a plurality of p-channel and n-channel transistors which are connected to an output pad, by sequentially turning off the p-channel transistors before sequentially turning on the n-channel transistors, and by sequentially turning off the n-channel transistors before sequentially turning on the p-channel transistors.

Abstract: Integrated driver circuits include a pull-up circuit having a first plurality of PMOS pull-up transistors therein which are selectively enabled by a first multi-bit impedance control signal. This first multi-bit impedance control signal is a function of a first variable resistance device. A pull-down circuit is also provided. The pull-down circuit has a first plurality of NMOS pull-down transistors therein which are selectively enabled by a second multi-bit impedance control signal. This second multi-bit impedance control signal is a function of a resistance of a second variable resistance device. The pull-up circuit and pull-down circuit have commonly connected outputs. In particular, the pull-up circuit has a first impedance which is a function of a digital value of the first multi-bit impedance control signal and the pull-down circuit has a second impedance which is a function of a digital value of the second multi-bit impedance control signal.

Abstract: Integrated buffer circuits which are less susceptible to noise and provide TTL-to-CMOS signal conversion capability include a first TTL-compatible inversion buffer, a second CMOS-compatible inversion buffer having an input electrically coupled to an output of the first inversion buffer and a preferred pull-up (or pull-down) circuit to improve noise immunity. The preferred circuit pulls the output of the first inversion buffer to a potential of the first reference signal line (e.g., Vdd) in response to a signal at an output of the second inversion buffer and a signal at an input of the first inversion buffer. This circuit comprises a first field effect transistor having a gate electrode electrically coupled to the output of the second inversion buffer and a second field effect transistor having a gate electrode electrically coupled to the input of the first inversion buffer.

Abstract: The present invention is a battery backed output buffer which provides a well-defined signal, even during battery power. The buffer includes a regular output buffer for providing output data during operation with a main power supply and for switching to a tri-state during battery power. The buffer also includes a configurable battery backed output buffer which provides a predetermined output signal during battery operation and produces a signal in the tri-stated during main power operation.

Abstract: A BiCMOS logic circuit having greater drive and speed at low voltage is provided. The logic circuit includes a switching device which allows the pull-down device of the logic circuit to be driven directly by an input signal without first having to switch a MOS device. The switching device conducts current between the input terminal of the logic device and the pull-down device when the output signal equals a certain value.

Abstract: An output driver circuit that compensates for variations in supply voltage to provide more consistent switching speed characteristics. In one embodiment, the output driver circuit includes a plurality of pull down devices which are connected in parallel with one another between an output node of the circuit and ground. One of the pull down devices is coupled to a source of a pull down signal to be turned on in response to the pull down signal. The other pull down devices are turned on selectively, depending upon the level of the supply voltage. The lower the supply voltage, the more pull down devices that are turned on. A latch is provided at the input of each of the pull down devices. The result of the selective enabling of the pull down devices is that a more uniform pull down speed is provided for different levels of the supply voltage.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.

Abstract: The semiconductor IC device has a circuit arrangement constituted by a first CMOS logic gate having input and output terminals, and a second CMOS logic gate which performs the same logic operation as that of the first CMOS logic gate and which has an input terminal connected to the input terminal of the first CMOS logic gate. The arrangement also requires a differentiator circuit which has an input terminal thereof connected to an output terminal of the second CMOS logic gate and has an output terminal connected to the output terminal of the first CMOS logic gate. With such an arrangement, the dependency of the effective gate propagation delay time on an output load is lowered. As a result, therefore, the arrangement can be effected using a low power supply voltage while securing a high operation speed as well as a low power consumption. The CMOS logic gates can also be facilitated in combination with NPN bipolar transistors which are connected therewith in an emitter follower circuit form.

Abstract: A semiconductor integrated circuit device having an input/output circuit for inputting and outputting data having a GTL level includes a pull-down output MOSFET (Q1) and a pull-up output MOSFET (Q2) both electrically connected to an input/output terminal and a gate drive signal generating circuit (DPG) electrically coupled to the gate of the pull-up output MOSFET (Q2). Upon data transmission, the gate drive signal generating circuit (DPG) controls the operation of the output MOSFET (Q2) so that the output MOSFETs (Q1 and Q2) are contemporarily brought into an ON or OFF state according to data to be transmitted. On the other hand, upon data reception, the gate drive signal generating circuit (DPG) forms a control pulse for temporarily turning ON one of the output MOSFETS (Q2) immediately after high-level data has been received, and supplies it to a gate terminal of the output MOSFET (Q2).

Abstract: This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

Abstract: A CMOS delay cell with feedback circuitry to ensure that the delay cell is operating in saturation mode. A voltage controlled oscillator (VCO) comprising a loop of an odd number of delay cells, where the VCO is operating in a saturation mode. Under normal operation any intermediate node in the VCO will generate an output signal from a delay cell with reduced supply noise. The output signal can be used to generate a PLL clock signal with a lower phase jitter than prior art VCO's operating at low supply potentials.

Abstract: A buffer apparatus having a low output impedance includes a first transistor having one terminal coupled to a voltage source, the other terminal coupled to an output terminal of the buffer, and a gate which receives an input signal of the buffer; a second transistor having one terminal coupled to the output terminal of the buffer and a gate which receives the input signal of the buffer; a current sensing circuitry, which is coupled to the other terminal of the second transistor, for sensing a current of the second transistor and amplifying an input current which flows to the second transistor; a voltage driving circuitry, which is formed between the output terminal of the buffer and a ground voltage, for decreasing an output voltage of the buffer by passing the current from the output terminal to the ground voltage according to a control signal which is applied to the voltage driving circuitry.

Abstract: A BiCMOS line driver that incorporates a fully-powered, zero- static power pull-down driver with a standard BiCMOS pullup in a novel parallel input signal path construction having substantially equal propagation delays to create a complementary signal driver with very high speed and extremely low skew in propagation.

Abstract: An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices coupled between the common output node and the base of the pull-down bipolar transistor. A second set of parallel MOS devices are coupled between the base of the pull-up output stage bipolar transistor and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.

Abstract: A data output buffer for a semiconductor memory device having a plurality of memory cells, each of the memory cells storing a data signal. The data output buffer comprises: an input line for inputting the data signal from each of the memory cells; a pull-up driver connected between a supply voltage source and an output line, the pull-up driver being driven in response to a first logic of the data signal from the input line; a pull-down driver connected between a ground voltage source and the output line, the pull-down driver being driven complementarily to the pull-up driver in response to a second logic of the data signal from the input line; at least one auxiliary pull-up driver connected in parallel to the pull-up driver; and a controller for driving the at least one auxiliary pull-up driver for a predetermined time period from a start portion of the first logic of the data signal from the input line.

Abstract: An output buffer circuit for supplying a current to an output pad of an integrated circuit comprises an output driver circuit and a feedback circuit. The output driver circuit includes a first current supply element for supplying a small current to the output pad in response to an input logic signal. The feedback circuit includes a second current supply element for supplying a large current to the output pad and a circuit for generating a feedback voltage to control the second current supply element. The feedback voltage is responsive to the input logic signal and inversely follows the output pad voltage when the output pad voltage crosses a threshold. The output buffer provides excellent short circuit protection.

Abstract: An output buffer circuit with edge-rate control capable of maintaining both rising and falling edge-rates within narrow specifications in the face of wide variations in load impedance. In particular, the output buffer of the present invention is intended for coupling to a common bus whereby it may be presented with very low resistive impedance loads and varying capacitive loads. The control schemes for both the pull-up and the pull-down parts of the circuit of the present invention utilize in part fixed currents charging a selected capacitance in order to achieve a metering of the charging or discharging current at the buffer's output. For the pull-down part of the circuit a dual MOS/Bipolar pull-down scheme is used, with the MOS transistors sequentially turning on in a gradual fashion so as to smooth the onset of current sinking. Subsequently, after a measured delay, a bipolar pull-down transistor is turned on.

Abstract: An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability.

Abstract: The present invention includes an input buffer circuit (10) having sleep mode and bus hold capability. An input section (11) of the buffer circuit is operated from an operating voltage which is lower than a supply voltage of the buffer circuit thereby minimizing the static power dissipation. Sleep mode circuitry (15, 36, 38) is included for effectively disconnecting an input signal from the rest of the buffer circuit thereby minimizing dynamic power dissipation. Bus hold circuitry (40) is included for holding the logic state appearing at an output of the input buffer circuit when the input signal is removed thereby further reducing the static power dissipation.

Abstract: A semiconductor logic circuit apparatus includes a plurality of logic circuits each including complementary field effect transistors, and a plurality bipolar transistors associated with the respective ones of the logic circuits. When any one of the outputs of the logic circuits becomes high, an associated bipolar transistor becomes conductive to cause an output terminal of the apparatus to be charged from a voltage supply. With all the outputs of the logic circuits being low, all of the bipolar transistors are non-conductive, and a current supply coupled between the output terminal and ground dicharges charge on the output terminal.