Abstract: A differential output circuit first and second transistors forming a differential pair and having control electrodes input with binary signals, a constant current circuit supplying a constant current to the first and second transistors, and a protection circuit protecting the first and second transistors from external noise. The protection circuit has transistors respectively coupled in parallel to the first and second transistors and input with a first power supply voltage, and transistors respectively coupled between a second power supply voltage and first and second output terminals of the differential output circuit.

Abstract: The output buffer stage includes a half-bridge output stage having a first pair of complementary drivers connected in series between a supply line and a ground node, the high impedance state or conduction state of which is determined through a pair of control phases. The buffer stage includes a pair of switches controlled by the control phases, connected in series between them and connecting the transistors of the first stage in series. Each driver is connected in series with a switch, that is quickly opened to prevent under-threshold currents from circulating when the respective driver is turned off, and that is rapidly turned off when the respective driver is turned on.

Abstract: A driver system, a driver calibration circuit arrangement for calibration of an impedance of a driver circuit arrangement, and a method for calibration of an impedance of a driver circuit arrangement can achieve improved driver behavior, with respect to undesirable distortions of the slew rate caused by off-chip drivers of DDR memory modules. A driver system has a first driver part with at least one variable impedance by which an operating point of the first driver part is determined with respect to a first potential and a second potential. The potentials supply the first driver part. A first monitoring device adjusts an impedance value of the variable impedance such that the operating point differs from a mid-point of the first and of the second potential.

Abstract: Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a control circuit. The pre-driver unit modifies a common mode level and the amplitude of first internal output signals to generate internal output signals in response to driver control signals. The main driver unit modifies the common mode level and the amplitude of the second internal output signals. The control circuit detects the common mode level and the amplitude of a connected circuit. The common mode level and the amplitude of the output signals may then automatically be adjusted to be the same as the common mode level and the amplitude of this connected circuit High speed signal conditioning may be accomplished.

Abstract: A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull operation. According to some embodiments, the switched capacitor buffer displays an optimal combination of design simplicity, low power consumption and high-frequency response.

Abstract: There is provided an output driver for use in a semiconductor device capable of remarkably improving linearity of impedance by reducing or minimizing a change of an impedance for output data caused due to a change of an external power supply. The output driver for outputting internal data of a semiconductor device to the exterior of a chip comprises a first driving section including a driving transistor to maintain an impedance for applied data at a certain level in response to the data; and a second driving section for compensating for linearity of the impedance in response to an operation signal from the driving transistor of the first driving section and providing an output terminal with the data.

Abstract: An embodiment of a differential output driver includes a driver to generate an inverted output signal in response to an input signal and a first control signal, and to further generate an output signal in response to an inverted input signal and a second control signal. The differential output driver also includes a controller to generate the first control signal and the second control signal in response to detecting a voltage difference between a first detected voltage difference between a reference voltage and the output signal, and a second detected voltage difference between the reference voltage and the inverted output signal.

Abstract: A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (VDD) and lower voltage level (VSS), in such a way that the paired transistors operate in subthreshold. N input terminals (X1, X2 . . . XN) are connected to the respective paired transistors. Control terminals (BP, BN) are connected to control input nodes of the transistors. The circuit element provides the possibility of real time configuration between various logic functions with a minimum of transistors and wiring.

Abstract: An H-bridge LVDS driver circuit includes a means to calibrate the output impedance of the switches of an LVDS driver to any desired value.

Abstract: A process compensation circuit for an inverting element of a CMOS device, including a duplicate inverting element connected in parallel with the inverting element of the CMOS device. An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the output of the inverting element of the CMOS device. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.

Abstract: A data output driver and a semiconductor memory device having the same are disclosed.

Abstract: A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

Abstract: An on-die termination circuit with a stable effective termination resistance value and stabilized impedance mismatching. The on-die termination circuit includes: a decoding unit for decoding set values of an extended mode register set; an ODT output driver block including a plurality of output driver units connected in parallel with an output node for outputting an output signal and assigned with different resistance values; and a control signal generation block for generating a plurality of pull up and pull down control signals for turning on/off the plurality of output driver units in response to output signals of the decoding unit.

Abstract: The present invention relates to an output driver circuit for a semiconductor memory device, in particular, a memory device using a DDR II concept or a concept similar thereto, which can reduce a variation in the slew rate of an output driver thereof between maximum and minimum values, while satisfying requirements of characteristics associated with slew rate.

Abstract: Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuit 36 receives a control signal depending on an output of a phase comparison circuit 34 from a control circuit 35, and comprises a first P-channel MOS transistor P1, a second P-channel MOS transistor P2 and a third P-channel MOS transistor P3, and a first N-channel MOS transistor N1, a second N-channel MOS transistor N2 and a third N-channel MOS transistor N3, and a first current source 61, a second current source 62, a third current source 63 and a fourth current source 64.

Abstract: A push-pull buffer amplifier and a source driver are provided. In the buffer amplifier, the N-type and the P-type comparators compare an input signal and an output signal. The input terminals of the first and the second inverters are coupled to the first output terminals of the N-type and the P-type comparators, respectively. The first and the fourth transistors are controlled by the second output terminal of the N-type comparator and the output terminal of the second inverter, respectively, so that the first voltage line charges/discharges an output load. The second and the third transistors are controlled by the second output terminal of the P-type comparator and the output terminal of the first inverter, respectively, so that the second voltage line charges/discharges the output load.

Abstract: An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

Abstract: An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided. Variations in process conditions may result in stronger or weaker relative current drive between NMOS and PMOS transistors. One or more process-dependent compensating current paths may be added to conventional pull-up and/or pull-down current paths to compensate for process variations by supplementing the current drive of transistors used to charge (PMOS) or discharge (NMOS) an output node of and end driver (e.g., inverter) stage of an OCD.

Abstract: A slew rate enhancement circuit for adjusting a gamma curve including a main output stage, a monitoring stage, an assistant output stage and a gamma curve generating device is provided. The main output stage also generates a first push signal and a first pull signal according to the input voltage, and thereafter the second push signal and second pull signal are level shifted by the monitoring stage. A second push signal and second pull signal will turn on or turn off the assistant output stage to decided whether to output an assistant current to the load or not. The gamma curve generating device receives the assistant current to outputs at least one gamma reference voltage for adjusting a gamma curve. Specially, the improved compact circuit does not increase static operating current for the original operational amplifier and occupy a small chip area.

Abstract: A driver circuit that outputs a data signal uses feedback of the data signal to the driver circuit to modulate a drive strength of the driver circuit. The driver circuit has a pull-up driver stage and a pull-down driver stage. The pull-up driver stage uses a pull-up control circuit to modulate a drive strength of the pull-up driver stage dependent on a voltage of the data signal. The pull-down driver stage uses a pull-down control circuit to modulate a drive strength of the pull-down driver stage dependent on the voltage of the data signal.

Abstract: A data output circuit is composed of first and second differential MOS transistors, first and second cascade MOS transistors, first and second outputs, and first and second resistor elements. The first and second differential MOS transistors receive first and second input voltages on the gates, respectively, sources of the differential MOS transistors being commonly connected. The first cascade MOS transistor is connected between the first differential MOS transistor and the first output, and the second cascade MOS transistor is connected between the second differential MOS transistor and the second output, gates of the first and second cascade MOS transistors being commonly connected. The first transistor element is connected between a ground line and the commonly connected gates, and the second transistor element is connected between a power supply line and the commonly connected gates.

Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.

Abstract: A differential output driver capable for selectively switching from an emphasis mode, a non-emphasis mode, and an idle state uses one pull-up device and two pull-down devices per output lead. The pull-up device is preferably always activated, and one or the other or both or neither of the pull-down devices are selectively activated to provide a desired behavior. Neither pull-down device is strong enough to singularly overcome the pull-up device and fully pull down an output lead to an emphasis logic low level. One of the pull-down devices is singularly strong enough to bring an output lead to a non-emphasis logic low level, which is higher than an emphasis logic low level. The other pull-down device is singularly strong enough to pull an output line from an emphasis logic high level to a non-emphasis logic high level. Working together, however, both devices can pull-down an output lead to an emphasis logic low level.

Abstract: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.

Abstract: A driver circuit. In one embodiment, the driver circuit includes a plurality of pull-up circuits and a plurality of pull-down circuits. The driver circuit also includes control logic that is coupled to activate/deactivate the pull-up and pull-down circuits. The driver circuit may perform emphasized signal transmissions having a voltage swing of a first magnitude or de-emphasized signal transmissions having a voltage swing of a second magnitude, wherein the first magnitude is greater than the second magnitude. The control logic is further configured to activate and/or deactivate pull-up and/or pull-down circuits such that the driver circuit output impedance in the emphasized mode is substantially equal to the output impedance in the de-emphasized mode.

Abstract: The present invention relates to an apparatus for adjusting a slew rate of a data signal outputted by a signal from an external circuit in a semiconductor memory device and a method therefor. The apparatus includes: a slew rate control signal generation block for outputting a plurality of slew rate control signals through combining control codes inputted from the external circuit in response to a command signal; and a data buffer for adjusting a slew rate of a data signal inputted by using the slew rate control signals.

Abstract: The distance between a drain contact and gate electrode in a terminating transistor, which couples a termination resistor connected to an output terminal to a power source node, is set shorter than in an output node transistor, which drives an output node in accordance with an internal signal. The area of the terminating circuit is reduced while the reliability against the surge is maintained. Thus, an output circuit containing the terminating circuit that occupies a small area and is capable of transmitting a signal/data at high speed is provided.

Abstract: The open-drain type output buffer includes a first driver and at least one of (1) at least one secondary driver and (2) at least one tertiary driver. The first driver selectively pulls an output node towards a low voltage based on input data. The secondary and tertiary drivers have first and second states. Each secondary and tertiary driver pulls the output node towards the low voltage when in the first state, and does not pull the output node towards the low voltage in the second state. A control circuit, when a secondary driver is included, controls the secondary driver such that the secondary driver is in the first state when it has been determined that at least two consecutive high voltage output data have been generated. The control circuit, when a tertiary driver is included, controls the tertiary driver such that the tertiary driver is in the second state when it has been determined that at least two consecutive low voltage output data have been generated.

Abstract: An input circuit (a first transistor pair) that receives complementary input signals is connected to a latch circuit (a second transistor pair) that converts the amplitude of an input signal into second amplitude higher than first amplitude. A current mirror circuit (a third transistor pair) is disposed between the latch circuit and a high-level power supply line. The current mirror circuit makes a source voltage of the second transistors being turned on lower than the source voltage of the second transistors being turned off. The second transistors being turned on are likely to be turned off although the on-current of corresponding first transistors is low. To the contrary, the second transistors being turned off are likely to be turned on. Accordingly, even when a voltage of a high logic level of an input signal is low, the level conversion circuit can surely operate without malfunction.

Abstract: An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance connection circuit connects a capacitance between the first and second differential output nodes. The capacitance connection circuit then adjusts the value of the capacitance in accordance with a control signal.

Abstract: A buffer for a programmable device has source current circuitry, sink current circuitry, one or more input nodes, one or more output nodes, and switch circuitry. The source current circuitry can be programmably controlled to generate a plurality of different total source currents, and the sink current circuitry can be programmably controlled to generate a plurality of different total sink currents. The one or more input nodes can receive one or more input signals, and the one or more output nodes can present one or more output signals. The switch circuitry can selectively apply at least one of a total source current and a total sink current to the one or more output nodes based on the one or more input signals.

Abstract: An apparatus and method is disclosed for transmitting signals over a signal conductor using a precompensated driver that does not use a current source, and which drives the signal conductor with an impedance similar to the characteristic impedance of the signal conductor. Since no current source is used, the precompensated driver can operate at very low supply voltage.

Abstract: A multi-stage light emitting diode (LED) driver circuit is provided. The circuit includes a driver transistor coupled to an LED. The LED is coupled at a drain of the driver transistor and the driver transistor drives current to the LED. A first transistor stack is coupled between a gate of the driver transistor and ground. A first inverter stage is coupled to a common gate of the first transistor stack. The first inverter stage is further coupled between a high voltage source and ground. A second inverter stage is coupled to a common gate of the first inverter stage. The second inverter stage is further coupled between the high voltage source and ground. The circuit further includes a first transistor coupled between the high voltage source and gate of the driver transistor. The gate of the transistor is coupled to the first inverter stage.

Abstract: A high performance adaptive load output buffer with fast switching of capacitive loads includes a first set of series connected complementary cascode structures having a first output node at the junction of the cascode connected p-channel device, a second output node at the junction of the two cascode structures, and a third output node at the junction of the cascode connected n-channel device. The buffer also may include at least one second set of series connected complementary cascode structures having the control terminal of the p-channel cascode structure of the second set connected to the inverted output from the first output node of first complementary cascode structure. The control terminal of the n-channel cascode structure of the second set may be connected to the inverted output from the third output node of first complementary cascode structure. The common terminal of the second cascode structure may be connected to the second output node of first complementary cascode structure and the output pad.

Abstract: A line driver (3) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors (14, 15) for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors (16, 17), each with the differential pair transistors (14, 15) forming a cascode circuit, onto the data transmission line (8, 9) connected to the line driver (3).

Abstract: A line driver for off-chip communication comprises multiple parallel stages each with separate inputs. The parallel stages each have a controlled impedance when driving the line driver output node to a logic zero or a logic one. A line driver controller is used to select what combination of driver stages are used to drive the output node based on whether the output node is transitioning between logic state or is remaining static. During power-up, a test program tries different combinations of driver stages for particular symbol patterns and determines what is the optimal ratio between line driver resistance for the dynamic and static cases and stores the optimum combination. The data stream feeding the line driver is sampled in real time to determine the transition states and selects the optimal number of driver stages for each case.

Abstract: A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.

Abstract: A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by the propagation delay of each gate and controlling driving transistors as a function of comparison of that history with input data so that, either the signal is driven into the transmission line at full strength, or at a level near the minimum needed to retain the state in the receiver. The advantage of the invention is that the line capacitance decays through the terminating resistors or discharge transistors, such that when the next state change is needed, then line has less stored energy needing to be discharged.

Abstract: An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Abstract: Buffer circuits and techniques that reduce skew between rising and falling times of output data as process conditions vary are provided. One or more process-dependent current sources may be utilized to compensate for process variations by supplementing the current drive of transistors used to precharge (PMOS) or discharge (NMOS) an output node of a secondary (e.g., inverter) stage of the buffer circuit.

Abstract: Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.

Abstract: A transmission line driver with slew rate control includes high and low side ramp generators for generating charge and discharge ramp signals, respectively, which are input to respective comparators and a pair of source follower transistors. A pair of additional transistors is connected to the pair of source follower transistors and a pair of staggered drivers is connected to the pair of additional transistors.

Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: Disclosed is an input device for a semiconductor device that optimizes the performance characteristic of the semiconductor device using off-chip driver information. The input device includes at least two buffers, connected in parallel to an electrostatic discharge (ESD) circuit, for buffering an input signal applied through the ESD circuit. The buffers have delay times different from each other, one of the buffers is selected using off-chip driver information detected from an output driver and the input signal is transferred through the selected buffer. The signal transfer path of the input device is optionally be selected using the off-chip driver information of the output drivers, and a stable input/output operation of the semiconductor device is achieved even if the performance characteristic of the semiconductor device is changed due to the skew occurring in the fabricating process of the semiconductor device.

Abstract: A circuit (S1) for switching on an electrical load which can be connected downstream from the circuit comprises a first electronic switching means (T1) in a first path, and a second electronic switching means (T2) in a second path, which is in parallel with it. The circuit also has a means (INV, OR, T5) for producing the electrical control variable (Ugate2) for the second switching means (T2), which determines the control variable (Ugate2) as a function of an electrical variable (U0,d) which occurs on the output side of the first switching means (T1) when switching on a load which can be connected downstream.

Abstract: An impedance controller includes a current mirror section to generate an impedance current. At least one detector includes a transistor array and an impedance corresponding to the impedance current, the at least one detector operating responsive to a code generator. And an at least one code generator generates a first code to adjust a gate voltage of the transistor array by comparing an output of the at least one detector to a reference voltage and generates a second code to adjust a size of the transistor array by comparing the output from the at least one detector to the reference voltage.

Abstract: Apparatus and method of tuning a digitally controlled input/output (I/O) driver of an integrated circuit for parameter variation compensation, a bus impedance of the I/O driver being controlled by a first digital code comprises in one embodiment: controlling a bus impedance of a reference I/O driver network by a second digital code; monitoring a voltage potential of the bus and generating the second digital code based on the monitored bus voltage potential; and tuning the second digital code to generate the first digital code.

Abstract: A slew rate enhancement circuit of an operational amplifier including a main output stage, a monitoring stage and an assistant output stage is provided. An input voltage of the operational amplifier is detected by the main output stage to decide whether to output a main current to the load or not. The main output stage also generators a first push signal and a first pull signal according to the input voltage, and thereafter the second push signal and second pull signal are level shifted by the monitoring stage. A second push signal and second pull signal will turn on or turn off the assistant output stage to decided whether to output an assistant current to the load or not. Specially, the improved compact circuit does not increase state operating current for the original operational amplifier and occupy a small chip area.

Abstract: The present invention provides a semiconductor device that can shorten the initialization cycle of impedance matching of interface buffers and reduce as much as possible affects on other circuits at the time of fine control thereafter. The semiconductor device (1) includes interface buffers (18a to 18c) whose internal impedances are controlled by impedance control data and an impedance control circuit (35) that generates the impedance control data. The impedance control circuit includes a first impedance control mode that initially generates the impedance control data by a binary search and comparison operation resulting from predetermined impedance control steps and sets the impedance control data in the interface buffers, and a second impedance control mode that updates the impedance control data set in the interface buffers by a sequential comparison operation resulting from the predetermined impedance control steps.

Abstract: One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or more lines terminated by the termination circuitry, shunting current from the termination voltage supply and through the termination voltage delivery network in response to a second signal on one or more terminated lines, and helping to reduce the shunted current for extended shunting.