Abstract: A circuit for applications such as electrical impedance tomography includes a voltage-to-current converter having an input for receiving a voltage waveform and an output for outputting a current waveform to a load at an output resistance for the voltage-to-current converter. The voltage-to-current converter includes resistance control means for adjusting the output resistance of the voltage-to-current converter under computer control. The circuit of the present invention also includes an inductance control circuit operatively connected to the voltage-to-current converter for synthesizing a selected inductance. The inductance control circuit includes inductance control means for adjusting the value of the selected inductance by computer control.

Abstract: A rail—rail current sense amplifier including a low voltage current sense amplifier circuit, a high voltage current sense amplifier circuit, a first resistive device, and a selection circuit. The current sense amplifier senses current through a current sense device coupled to a battery node. The low voltage current sense amplifier circuit develops a first current that is proportional to current through the current sense device for low voltages up to an upper voltage threshold. The high voltage current sense amplifier circuit develops a second current that is proportional to current through the current sense device for high voltages down to a lower voltage threshold. The selection circuit selectively applies the first current to the first resistive device for low voltages up to the upper voltage threshold, and selectively applies the second current to the first resistive device for high voltages down to the lower voltage threshold.

Abstract: An apparatus for providing a multi-mode interface between a baseband receiver and radio frequency (RF) circuitry. According to a preferred embodiment of the invention, the apparatus includes a first differential-to-single-ended converter, a second differential-to-single-ended converter and an analog-to-digital converter. The first differential-to-single-ended converter receives an incoming differential current pair to be converted into a first single-ended voltage signal. The second differential-to-single-ended converter receives an incoming differential voltage pair to be converted into a second single-ended voltage signal. Further, the analog-to-digital converter selectively receives an incoming single-ended voltage signal, the first single-ended voltage signal, or the second single-ended voltage signal to be converted into a digital signal to be further processed by the baseband processor.

Abstract: An input current flowing into a current-voltage conversion circuit (1) is converted to a voltage value at an output terminal SAIN and, then, a differential amplification circuit (5) amplifies and outputs a differential voltage between the voltage value and the reference voltage Vref. PMOS and NMOS transistors T1, T2 are connected between the output terminal SAIN and the power-supply voltage VCC. After the output terminal SAIN is precharged to the power-supply voltage VCC by making the transistors conductive, the current-voltage conversion operation is performed by making a voltage drop corresponding to the input current. The precharge operation precharges the output terminal SAIN up to the power-supply voltage VCC and supplies precharge to a common data line N3 and bit lines.

Abstract: A method and system is described wherein an information signals is gated at a frequency that is a sub-harmonic of the frequency of the desired output signal. In the modulation embodiments, the information signal is modulated as part of the up-conversion process. In a first modulation embodiment, one information signal is phase modulated onto the carrier signal as part of the up-conversion process. In a second modulation embodiment, two information signals are multiplied, and, as part of the up-conversion process, one signal is phase modulated onto the carrier and the other signal is amplitude modulated onto the carrier. In a third modulation embodiment, one information signal is phase modulated onto the “I” phase of the carrier signal as part of the up-conversion process and a second information signal is phase modulated onto the “Q” phase of the carrier as part of the up-conversion process.

Abstract: A current-mode pulse-width-modulation (PWM) circuit converts analog current signals into pulse signals. The PWM circuit includes a first I-V converter and one or more second I-V converters, each of the one or more second I-V converters being coupled to one of the current signals. Each of the first and second I-V converters is also coupled to a current generator which generates a current that linearly changes with time. For each of the first and second I-V converters, when a polarity of the input current thereof changes, an output changes between a high voltage level and a low voltage level. A logic circuit is coupled to the first and each second I-V converter to obtain a pulse signal that has a pulse width linearly proportional to the current level of the respective current signal.

Abstract: A voltage-to-current converter circuit is disclosed. In one embodiment, the present invention includes a first metal oxide semiconductor field effect transistor (MOSFET) stage operable in a low to medium power range. The present invention also includes a second MOSFET stage operable in a medium to high power range. An additive circuit is utilized to add the contributions of both the first MOSFET stage and the second MOSFET stage. A subtractive circuit is further used to subtract either the first MOSFET stage or the second MOSFET stage when both the first MOSFET stage and the second MOSFET stage are operating in the medium power range and outputting current in a voltage-to-current converting circuit.

Abstract: The invention relates to a method and to an electronic circuit for converting a current signal Isignal to a voltage signal Vout) comprising: a first resistor Rgain and a second resistor Rconversion, means 2 for generating a first current Igain based on a reference voltage Vreference applied over the first resistor, means 3, 4 for generating a second current, the magnitude of the second current being determined on the basis of the multiplied magnitude of the first current and the current signal, means 5 for applying the second current to the second resistor for generating the voltage signal.

Abstract: A charge pump circuit includes a high-swing transconductance amplifier. A high input swing transconductance is provided in a negative feedback loop of the charge pump circuit without an abrupt change in transconductance. The high-swing transconductance amplifier includes a transconductance cell and high-swing circuitry. The transconductance cell includes a current supply transistor, which provides current for transconductance while input voltages are within the operational range for the transconductance cell. When the input voltages increase so as to be outside of the operational range, the current source transistor enters into triode region of operation, and provides reduced current. The high-swing circuitry supplies the current in this case so that abrupt change in transconductance does not occur.

Abstract: A receiver comprising an input for receiving a first signal, said receiver further comprising a local oscillator for generating a periodical signal. The receiver further comprises a mixer for generating a third signal representative for a combination of a second signal and the periodical signal. The receiver is characterized in that it further comprises a voltage to current converter for receiving the first signal and generating the second signal as a current indicative for the first signal. The mixer comprises a plurality of controllable switches. The receiver further comprises a variable gain current to voltage converter (VGIV) coupled to the passive mixer, the VGIV receiving the third signal and generating a first voltage signal, said first voltage signal being in a linear relationship with the third signal.

Abstract: A programmable logic unit (e.g., an ASIC or FPGA) having a feedforward linear associative memory (LAM) neural network checking circuit which classifies input vectors to a faulty hardware block as either good or not good and, when a new input vector is classified as not good, blocks a corresponding output vector of the faulty hardware block, enables a software work-around for the new input vector, and accepts the software work-around input as the output vector of the programmable logic circuit. The feedforward LAM neural network checking circuit has a weight matrix whose elements are based on a set of known bad input vectors for said faulty hardware block. The feedforward LAM neural network checking circuit may update the weight matrix online using one or more additional bad input vectors. A discrete Hopfield algorithm is used to calculate the weight matrix W.

Abstract: A gain controlled voltage controlled oscillator. A current controlled oscillator is adapted to provide an output signal oscillating at a frequency controllable by controlling a current applied thereto. A first current source provides a first control current controllable by controlling a voltage applied thereto that has a predetermined range. A first current mirror is adapted to mirror the control current to the current controlled oscillator. A second current source is adapted to provide a second control current for mirroring to the current controlled oscillator by the first current mirror when the control voltage is in a low portion of the range.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network. The converter further includes a plurality of comparators corresponding to the plurality of voltage reference signals.

Abstract: System and method for analog signal generation and manipulation in an ultra-wideband (UWB) transmitter. A preferred embodiment comprises a digital portion 305 of an UWB transmitter (for example, transmitter 300), which is responsible for encoding a data stream to be transmitted, and an analog portion 330. The analog portion 330 creates a stream of short duration pulses from the encoded data stream and then filters the stream of short duration pulses. To simplify the generation of the short duration pulses, a quantized representation of the short duration pulse is used. The quantized representation is created via the use of control signals that by coupling differential amplifiers together (such as amplifier 611), generate a voltage drop across a resistor (such as resistor 619) and hence, a current.

Abstract: An optical sensing circuit is provided with a light detector, a voltage to current conversion circuit connected to the light detector, and a comparator. The voltage to current conversion circuit includes an electric resistor and a current mirror circuit connected in parallel to the resistor. The voltage to current conversion circuit increases an electric current flowing through the circuit as a voltage of the output of the light detector decreases. The comparator compares the voltage of the output of the light detector with a reference voltage.

Abstract: The present invention provides a system (200) for controlling drive signal timing parameters of an output driver circuit (206). The present invention defines a driver circuit having an output interface (204), and a first transistor (222) coupled to a first voltage supply (230), a first control signal (232), and a first node (220). The circuit also has a first resistive element, coupled between the first node and a second node (234). A second resistive element (228) is coupled to ground. A second transistor (224) is coupled to the second node, to a second control signal (236), and the second resistive element. The circuit has a third transistor (244), coupled to the first and second nodes, and to a third node (240). A third resistive element (242) is coupled between the third node and the output interface. A fourth transistor (238) is coupled to the first and third nodes, and to the output interface.

Abstract: An integrated circuit (IC) uses a current source coupled to means for current-to-voltage conversion to reject the unwanted high voltage signal and detects the wanted small voltage signal. In particular, the current source produces mirrored currents proportional to the high voltage signal, while the means for converting current-to-voltage rejects the common-mode current when there is no small signal voltage flowing through the sensing resistor. On the other hand, when the small signal voltage exists, a current flows across the sensing resistor and disturbs the balance of the current mirror. As a result, the common mode no longer exists and the means for converting current-to-voltage converts and amplifies this small signal current into a voltage proportional to the small voltage signal.

Abstract: In an I/V converter circuit and a D/A converter, a wide pass band for signal can be obtained and current consumption can be reduced. A current is supplied through an input terminal to a first node, and a first bias current is supplied from a first bias-current generating circuit to the first node. The current supplied to the first node is mirrored to a second node, and a second bias current is supplied from a second bias-current generating circuit to the second node. A first control circuit controls first and second elements of a current mirror circuit so that the voltage of the first node is substantially equal to a bias voltage, a third element converts a current flowing therethrough to a voltage by using the bias voltage as reference, and a second control circuit controls the voltage output from an output terminal so that the voltage of the second node is substantially equal to the bias voltage.

Abstract: Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to provide a second signal, and the input signal is also processed in the same manner to provide a third signal. A majority vote is taken between the first, second, and third signals by an SEU immune majority voter circuit, and an output signal is provided corresponding to the majority vote.

Abstract: It is an object of the present invention to provide a current-voltage conversion circuit in which the sensitivity varies in accordance with the amplitude of the input signal. In the current-voltage conversion circuit of the present invention, n+1 (n is an even number) amplifying inverters are connected in series between an input terminal and an output terminal; furthermore, the input of a negative feedback circuit constructed from an integrating circuit and a negative feedback inverter is connected to the output side of the nth-stage amplifying inverter, and the output of this negative feedback circuit is connected to the input side of the first-stage amplifying inverter. The integrating circuit outputs the mean value of the output potential of the nth-stage amplifying inverter into the negative feedback inverter, and the negative feedback inverter controls the current that flows the ground line from the input terminal in accordance with the output voltage of the integrating circuit.

Abstract: A night-vision optical device of the invention with controlled life expectancy contains a time measuring device built into the housing of the aforementioned device for measuring the accumulated time of active work of the device. In application to a night scope for a firearm, the device also contains a sensor, which is interlocked with activation of the scope and reacts on the shots produced from the firearm in general and separately on those shots produced during active work of the night-vision optics at nighttime. The aforementioned shots of both types are counted and stored in separate memory units. The night-time shots affects the life expectancy of the night-vision optics because of muzzle flashes which cause such devices as an image intensifier to work with an increased light load. The information obtained from the time measuring device and the shot counter makes it possible to timely receive a warning signal about the fact that the night optics or the entire firearm must be replaced.

Abstract: A current pulse receiving circuit suitable for converting a current pulse converted by a photodetector from a light pulse received in optical communications and outputting a logic level voltage pulse with an accurate pulse width is disclosed. When an output signal from a current-to-voltage converter circuit is detected to have a large amplitude by a large signal detection circuit, an amount of offset cancellation of a DC cancellation circuit is decreased to limit the amplitude of the output signal from the current-to-voltage converter circuit. Since the amplitude of an input signal of an amplifier circuit is limited, tail characteristics at a trailing edge of a pulse are small and an output is provided at an output terminal with an accurate pulse width.

Abstract: An apparatus and method of generating a current pair Ip, Im where the ratio of the pair is exponentially related to a control signal, and where either Ip or Im is greater than or less than a minimum or maximum value includes a feedback correction circuit used to sense the value of Im or Ip. The correction circuit supplies a boost current Iboost when the sensed value of Ip or Im is less than or greater than the minimum or maximum value. Iboost is preferably maintained proportional to the difference of the desired value and Ip or Im.

Abstract: The invention includes an apparatus and a method for minimizing power supply sensitivity of a differential amplifier. The apparatus includes a current source providing a differential amplifier bias current to a common source node of the differential amplifier. A voltage sensor senses variations of a power supply associated with the current source. Variations sensed by the voltage sensor control a magnitude of the differential amplifier bias current. The method includes a current source providing the source current. A voltage potential of the common source node is sensed. The current source is adjusted depending upon the sensed voltage potential of the common source node, thereby adjusting a magnitude of the source current.

Abstract: A current to voltage conversion circuit for improving the speed of a photoelectric conversion device and frequency characteristics of an amplifier by improving a method for switching the gain of an amplification circuit for a photo detector integrated circuit (PDIC). Photocurrent generated in the photoelectric conversion device, such as a photodiode, is transferred to the amplifier by means of current mirroring, so as to raise a bias voltage to the photoelectric conversion device and enhance a response speed thereof. Further, the amount of current generated in the photoelectric conversion device is adjusted through control of a resistance ratio of a current mirror circuit. Therefore, a fixed feedback resistor can be used for the amplifier irrespective of modes, so as to enhance frequency characteristics of the amplifier.

Abstract: A charge pump circuit includes a high-swing transconductance amplifier. A high input swing transconductance is provided in a negative feedback loop of the charge pump circuit without an abrupt change in transconductance. The high-swing transconductance amplifier includes a transconductance cell and high-swing circuitry. The transconductance cell includes a current supply transistor, which provides current for transconductance while input voltages are within the operational range for the transconductance cell. When the input voltages increase so as to be outside of the operational range, the current source transistor enters into triode region of operation, and provides reduced current. The high-swing circuitry supplies the current in this case so that abrupt change in transconductance does not occur.

Abstract: A word line driver circuit is coupled to a word line of an associated Content Addressable Memory (CAM) array. The word line driver circuit adjusts the word line read voltage in response to a compare signal indicative of whether the CAM array is performing a concurrent compare operation. For some embodiments, the word line driver circuit selectively provides a relatively high word line read voltage or a relatively low word line read voltage in response to the compare signal.

Abstract: A modified Brokaw cell-based circuit produces a current which varies linearly with temperature. The collector-emitter current flow path of a diode-connected transistor is connected in series with the PTAT current produced by a control transistor. The base of the control transistor receives a control voltage whose value defines a limited range of variation of output current with temperature. The output transistor is coupled to an input port of a current mirror, which mirrors the linear collector current from the output transistor. The current through the output transistor is controlled by a composite of a CTAT base-emitter voltage of the diode-connected transistor and a PTAT voltage across a resistor, so that the output transistor produces an output current having a linear temperature coefficient.

Abstract: A transconductance control circuit includes a master device having first and second field effect devices coupled to respective first and second current sources, a reference device coupled to a third current source, and comparison circuitry. The comparison circuitry includes at least first, second and third inputs and at least one output, with the first input configured to receive a reference signal associated with the reference device, the second and third inputs coupled to respective terminals of the first and second field effect devices, and the output coupled to current control inputs of one or more of the current sources. The transconductance control circuit provides a feedback control arrangement in which, for example, the comparison circuitry output is utilized to adjust one or more of the current sources such that a difference signal Vg between voltages at the respective terminals of the first and second field effect devices converges to a reference signal VR.

Abstract: An improved voltage to current converter circuit having three stages. The first stage amplifies the input voltage signals. The second stage includes first and second/third current sources that are connected in a current mirror configuration with a common node therebetween. The third stage consists of an output transistor to form a half cascode current mirror having its drain connected to the second/third current sources and to the output terminal. The gate of the output transistor is coupled to a bias voltage and to the drain of an additional transistor so that the potential on the gate of the output transistor can vary to have both transistors of the third stage in the saturation state for a wide range of the current flowing through the transistors of the half cascode current mirror.

Abstract: Device for reducing the lag and the dark current of a particle detector, and in particular a photon detector.

Abstract: The invention intends to reduce noises by resistors in an output filter for a delta sigma modulator. The output filter uses an FIR filter with constant current sources as the current source, extracts output data of the delta sigma modulator from each taps of a shift register, controls MOS transistors by the extracted delayed signals, attains currents weighted according to the FIR filter coefficients corresponding to the number of the taps from the constant current sources, adds the currents attained, and performs the current-to-voltage conversion of the currents thus attained by feedback resistors of a full differential operational amplifier.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network. The converter further includes a plurality of comparators corresponding to the plurality of voltage reference signals.

Abstract: A semiconductor integrated circuit comprises a digital-to-analogue converter for converting a digital signal into an analogue signal to output an analogue current signal, a current-to-voltage converter for converting the analogue current signal output by the digital-to-analogue converter, into an analogue voltage signal whose level has been controlled, and a filter for filtering the analogue voltage signal converted by the current-to-voltage converter. The current-to-voltage converter converts the current signal into the voltage signal in which a factor variable in accordance with manufacturing process conditions and/or environmental conditions has been corrected.

Abstract: A filter circuit having an input resistance portion including a first transconductor having a positive input port impressed with a first voltage, a negative input port impressed with a second voltage, a positive output port and a negative output port; a second transconductor having a positive input port impressed with the second voltage, a negative input port impressed with a third voltage, a positive output port and a negative output port; and a third transconductor having a positive input port coupled to the positive output ports of the first and second transconductors and the negative output port of the third transconductor, a negative input port coupled to the negative output ports of the first and second transconductors and the positive output port of the third transconductor, a positive output port and a negative output port.

Abstract: A neuron circuit generates a sigmoid transfer function and its derivative. The neuron circuit comprises an I-V converter that converts a current input signal into a voltage signal, a first output circuit having a first differential amplifier with a first current mirror as an active load, and a second output circuit having a second differential amplifier with a second current mirror as an active load, both the first and second output circuit being coupled to the voltage signal. While an output of one of the first and second output circuits is a sigmoid function of the current input, a difference between the two outputs of the two output circuits is a derivative of the sigmoid function.

Abstract: A translinear variable-gain amplifier. The translinear variable gain amplifier receives a differential input voltage and produces a differential output current having a selected gain. The amplifier comprises a buffer amplifier that receives the differential input voltage and produces a differential input current. The amplifier further comprises a translinear gain cell coupled to receive the differential input current and produce the differential output current. The gain cell includes a first adjustable bias source that operates to set a linear input range of the gain cell, and a second adjustable bias source that operates to set a gain value of the gain cell.

Abstract: There is provided a frequency voltage converter comprises a first transmission line for transmitting an input signal and a second transmission line provided with a delay line circuit, a third transmission line for transmitting a reference signal and a fourth transmission line provided with a delay line circuit, a mixer circuit, and a locked loop having a control circuit for outputting the same control signal to control portions of both delay line circuits so that the amount of a delay by the delay line circuit reaches one cycle of the reference signal, thereby holding linearity with respect to the frequency of a modulated wave signal and executing frequency voltage conversion even when a center frequency is low.

Abstract: A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter, an active current mirror, and a current multiplier to provide a current signal indicative of a weighted sampled voltage signal. The current signals from the filter taps are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential. The voltage-to-current converter may include a common-mode high-pass filter to reject common-mode voltage variations.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network.

Abstract: The improved voltage to current (V2I) converter circuit (31) is basically comprised of three stages in CMOSFET technology. The first stage (11) amplifies the input voltage signals (VFILTP, VFILTN). The second stage (12) coupled to the first stage includes first and second/third current sources (20,21/22) loaded by respective transistors (TN1, TN2) that are connected in a current mirror configuration with a common node (23) therebetween. The third stage (13) coupled to the second stage consists of an output transistor (TN3) loaded by another transistor (TN4) to form a half cascode current mirror having its drain connected to said second/third current sources and to the output terminal (24).

Abstract: An absolute value circuit includes an operational amplifier, the output of which is coupled to control inputs of complementary polarity transistors having current flow paths therethrough coupled in series with inputs of current mirror amplifier stages. A common node of the current flow paths through the transistors is coupled to an input of the operational amplifier to which a current waveform is applied. The current mirror amplifier stages are configured so as to provide like polarity output currents. The outputs of the current mirror amplifier stages are combined to produce an output current that corresponds to a full wave rectification or absolute value of an input current coupled to the operational amplifier.

Abstract: A circuit for generating a linear current control signal and method thereof is provided so that the error between the input voltage and the linear current remains constant. The circuit of the invention comprises a resistor, an operational amplifier and a MOSFET, which forms an ideal linear relationship between an input voltage and an output current. The operational amplifier generates a gate-controlled voltage when a reference voltage and an input voltage are inputted thereto. The gate voltage turns on the MOSFET so that a linear current control signal is outputted from the source of the MOSFET.

Abstract: A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a reference voltage to be trimmed, as generated by the integrated circuit. Once the correct value of the trim current is determined, isolation circuitry is programmed to isolate the trim circuitry from the remainder of the IC, thereby freeing the logic and package pins associated with the IC for use by users of the IC. The preferred trim circuitry includes fuses which are blown in accordance with a bit value supplied to the trim cell to permanently fix a trim current value, once a best fit value is determined.

Abstract: A transconductor for generating a current corresponding to an input voltage. The transconductor has a crossing pairs structure. The transconductor comprises a first and a second MOS (Metal-Oxide Semiconductor) transistors mutually connected in series to a voltage source. A first bipolar transistor is connected to a current source. A collector terminal of the first bipolar terminal is connected to an output current terminal. An emitter terminal of the first bipolar terminal is connected to a gate terminal of the second MOS transistor. A second bipolar transistor is connected in series to the first bipolar transistor. A base terminal of the second bipolar transistor is connected to a node between the first MOS transistor and the second MOS transistor. A third MOS transistor is provided. A gate terminal of the third MOS transistor is connected to an input terminal for a signal from outside. A drain terminal of the third MOS transistor is connected to an emitter terminal of the second bipolar transistor.

Abstract: What is involved is a transconductance circuit is discussed, having at least one transconductance subcircuit (100) that is connected between two supply terminals (20, 21) and includes at least one MOS transistor (M1, M1′). It comprises means (200) for biasing the MOS transistor (M1, M1′) in the subcircuit (100) with a biasing current whose variation as a function of temperature substantially compensates for that of the mobility of the majority carriers in the channel of the MOS transistor (M1, M1′) in the subcircuit (100), in such a way as to make the transconductance of the circuit substantially independent of temperature.

Abstract: The invention concerns a current-voltage converter comprising electronic means (3,R) to supply a voltage (Vout)from a current (Iph). The converter comprises first means (4, K) to apply or not apply the current at converter input, second means (ECH1) to sample and memorize a voltage (Vout1) at converter output when the current is applied at converter input, third means (ECH2) to sample and memorize a voltage (Vout2, Vout3) at converter output when the current is not applied at converter input, and fourth means (S) for subtracting the voltage sampled and memorized by the third means (ECH2) from the voltage sampled and memorized by the second means (ECH1).

Abstract: A balanced transconductor having a pair of voltage inputs and a pair of current outputs comprises a pair of single-ended transconductors, one in each signal path and a cancellation network. The cancellation network cancels at the inputs to the single-ended transconductors a common mode voltage appearing at the voltage inputs so that no common mode output current results. The cancellation network may comprise four half-size single-ended transconductors drawing half the supply current of full-size single-ended transconductors.

Abstract: Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to provide a second signal, and the input signal is also processed in the same manner to provide a third signal. A majority vote is taken between the first, second, and third signals by an SEU immune majority voter circuit, and an output signal is provided corresponding to the majority vote.

Abstract: A low power voltage-to-current converter is provided for use in a phase lock loop circuit. The low power voltage-to-current converter includes an input stage, and output stage, and a non-differential output terminal. The input stage includes a pair of differential signal input terminals to receive a differential input signal pair, a first and second switching transistor pair coupled to the differential input signal pair, and a first and second complementary transistor pair coupled to the first and second switching transistor pair. The output stage is coupled to the first complementary transistor. The non-differential output terminal is coupled to the output stage, and is operable to transmit an output current signal, wherein the output current signal is a function of the differential input signals. The voltage-to-current converter is also designed for use in a phase lock loop.