Converting Input Voltage To Output Current Or Vice Versa Patents (Class 327/103)
  • Patent number: 6664818
    Abstract: The current controlled sigmoid neural circuit is used for approximating sigmoid function and is simple constructed, current controlled and gain adjustable circuit with highly precision. The present invention comprises a voltage generator for converting a current input into a voltage, a pair of differential amplifier for generating sigmoid-like function and few pairs of current mirrors for providing reference currents. By using adjustable reference current and gain factor, the circuit has a large range and high noise immunity and can approximate sigmoid function with insignificant error.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: December 16, 2003
    Assignee: Winbond Electronics Corporation
    Inventors: Bingxue Shi, Lu Chen, Chun Lu
  • Patent number: 6661274
    Abstract: In the level converter circuit, when input signal is L level, a first NMOS transistor and a first PMOS transistor P1 are turned on by a first power supply potential, a second power supply potential is output to a first output terminal, a second NMOS transistor is turned on, and thereby, a reference potential VSS is output to a second output terminal. On the other hand, when the input signal is H level, a third NMOS transistor is turned on, the reference potential is output to the first output terminal, a fourth NMOS transistor and a second PMOS transistor are turned on, and thereby, the first power supply potential VDH is output to the second output terminal.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: December 9, 2003
    Assignee: Fujitsu Limited
    Inventors: Naoaki Naka, Junko Nakamoto
  • Patent number: 6661280
    Abstract: The invention relates to an electronic filter circuit comprising a controllable transconductance circuit wherein a feedback loop is added to a substantially linear transconductance amplifier G, between two electronic leads having an input portion before the feedback loop and an output portion thereafter.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: December 9, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Henk Derks
  • Patent number: 6642753
    Abstract: A charge pump circuit includes a high-swing transconductance amplifier. A high input swing transconductance is provided in a negative feedback loop of the charge pump circuit without an abrupt change in transconductance. The high-swing transconductance amplifier includes a transconductance cell and high-swing circuitry. The transconductance cell includes a current supply transistor, which provides current for transconductance while input voltages are within the operational range for the transconductance cell. When the input voltages increase so as to be outside of the operational range, the current source transistor enters into triode region of operation, and provides reduced current. The high-swing circuitry supplies the current in this case so that abrupt change in transconductance does not occur.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: November 4, 2003
    Assignee: Broadcom Corporation
    Inventor: Ka Lun Choi
  • Patent number: 6639457
    Abstract: The present invention provides a CMOS transconductor circuit that features high frequency with high linearity, and the circuit includes an transistor. The source electrode of this output transistor is for receiving a current source. The gate electrode of this output transistor is for receiving another current source, and the drain electrode of this output transistor is for outputting current. Also included within the present invention is resistance that's coupled to the source electrode of the output transistor. A local negative feedback loop used as a negative feedback to connect the gate electrode of the output transistor to the source electrode itself, which makes the transconductance of this CMOS transconductor circuit to become the reciprocal of the resistance.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: October 28, 2003
    Assignee: Industrial Technology Research Institute
    Inventor: Chih-Hong Lou
  • Patent number: 6639445
    Abstract: The gate terminals of several Pch transistors are connected to an output terminal and controlled with second and third potentials. The gate terminals of several Nch transistors are connected to the output terminal and controlled with first and fourth potentials. In this way, an input signal between a VDD potential and a GND potential can be level-shifted to an output signal between a VPP potential and a VBB potential with a simple circuit structure. Also, the operation speed in switching potentials can be improved.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: October 28, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Akira Maruyama
  • Patent number: 6636085
    Abstract: There is disclosed a phase shifter using a polyphase filter, which achieves a broad band, suppresses errors in both amplitude and phase, and achieves low power consumption. A driving section includes a voltage-to-current conversion circuit for converting a voltage value of an input signal Si into a current value, and outputting an input current signal Ci. An RC polyphase filter 2 outputs a corresponding polyphase phase-shifted current signal Co according to supplying of the input current signal Ci. A load circuit 3 includes a polyphase current-to-voltage conversion circuit for converting a current value of the polyphase phase-shifted current signal Co into a voltage value, and outputting an output signal Vo.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: October 21, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Yukio Okazaki, Hisaya Ishihara
  • Patent number: 6624668
    Abstract: Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: September 23, 2003
    Assignee: Xilinx, Inc.
    Inventors: Moises E. Robinson, Michael J. Gaboury, Bernard L. Grung
  • Patent number: 6621331
    Abstract: An effective means and apparatus for generating a negative resistance including a circuit element that exhibits an increase in current as the applied voltage is decreased. Other embodiments of the present invention provide electronic means for improving the quality Q factor of on-chip resonators, which enables the creation of high-performance bipolar RF circuits with a minimum of external components.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: September 16, 2003
    Assignee: HRL Laboratories, LLC
    Inventors: Carl W. Pobanz, Gopal Raghavan
  • Publication number: 20030169080
    Abstract: A transconductor for generating a current corresponding to an input voltage. The transconductor has a crossing pairs structure. The transconductor comprises a first and a second MOS(Metal-Oxide Semiconductor) transistors mutually connected in series to a voltage source. A first bipolar transistor is connected to a current source. A collector terminal of the first bipolar terminal is connected to an output current terminal. An emitter terminal of the first bipolar terminal is connected to a gate terminal of the second MOS transistor. A second bipolar transistor is connected in series to the first bipolar transistor. A base terminal of the second bipolar transistor is connected to a node between the first MOS transistor and the second MOS transistor. A third MOS transistor is provided. A gate terminal of the third MOS transistor is connected to an input terminal for a signal from outside. A drain terminal of the third MOS transistor is connected to an emitter terminal of the second bipolar transistor.
    Type: Application
    Filed: February 6, 2003
    Publication date: September 11, 2003
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Won Lee, Gea-Ok Cho, Jung-Eun Lee
  • Publication number: 20030132787
    Abstract: What is involved is a transconductance circuit is discussed, having at least one transconductance subcircuit (100) that is connected between two supply terminals (20, 21) and includes at least one MOS transistor (M1, M1′). It comprises means (200) for biasing the MOS transistor (M1, M1′) in the subcircuit (100) with a biasing current whose variation as a function of temperature substantially compensates for that of the mobility of the majority carriers in the channel of the MOS transistor (M1, M1′) in the subcircuit (100), in such a way as to make the transconductance of the circuit substantially independent of temperature.
    Type: Application
    Filed: December 17, 2002
    Publication date: July 17, 2003
    Inventor: Herve Jean Francois Marie
  • Patent number: 6590431
    Abstract: The current passing in a main trans-conductor circuit is compared in analog domain with a reference current. If the passing current exceeds the reference current, another trans-conductor circuit may be switched on to cause the effective area of trans-conductor circuits to be increased. Using such a feature, the trans-conductance value may be maintained substantially constant without substantially increasing power.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: July 8, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijit Kumar Das, Srinivasan Venkatraman
  • Patent number: 6586919
    Abstract: The invention concerns a voltage-current converter having: a first current mirror containing two transistors that are designed such that under identical drive conditions the current flowing through the first transistor is greater than the current flowing through the second transistor by a predetermined factor. The current through the second transistor constitutes the output current of the voltage-current converter. The very large area required in integrated circuits for known voltage-current converters is reduced by providing a second current mirror containing two transistors. The two current mirrors are connected in series to a supply voltage. A MOSFET is connected in series with the first transistor of the first current mirror. The gate of the MOSFET is connected to the input voltage.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: July 1, 2003
    Assignee: Infineon Technologies AG
    Inventor: Hans-Heinrich Viehmann
  • Patent number: 6586972
    Abstract: This invention relates to a method and apparatus for converting a current signal into a two-level output voltage depending on a reference current signal. In one embodiment, a first current, which is the reference current signal is applied to the apparatus. A negative feedback sets the output of the apparatus in a certain configuration. Any current signal to be compared to the reference current signal may be then applied. The output voltage level depends on whether the current signal is lower or higher than the reference current signal.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: July 1, 2003
    Assignee: Valorbec, Limited Partnership
    Inventors: Chunyan Wang, Omair M. Ahmad, M. N. Srikanta Swamy
  • Patent number: 6583652
    Abstract: An improved programmable transconductor can be efficiently implemented utilizing a programmable resistor circuit that allows for only a selected portion of the resistor circuit (associated with a desired transconductor gain) to be coupled between summing nodes of the transconductor. Additional switching circuits can be used to reduce gain errors associated with the switches used to implement the aforementioned solution. Additionally, the improved programmable transconductor can be integrated into fully differential programmable analog integrated circuits, thereby enhancing the performance of such integrated circuits.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: June 24, 2003
    Assignee: Lattice Semiconductor Corporation
    Inventors: Hans W. Klein, Jian Li, Paul Hildebrant
  • Patent number: 6577170
    Abstract: A CMOS transconductor that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to a prior art transconductor circuit is provided. One embodiment, among others, comprises an input stage circuit comprising several pluralities of transistors with each plurality configured such that certain terminals of the transistors are electrically connected, and the several pluralities are electrically interconnected through one or more terminals of each plurality. Another embodiment comprises modifying an input stage of an existing transconductor circuit to provide a transconductor circuit that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to the existing transconductor circuit.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: June 10, 2003
    Inventor: Vladimir I. Prodanov
  • Patent number: 6570412
    Abstract: A semiconductor amplification circuit having a pair of differential input terminals, and a first MOS transistor having a gate thereof connected to a mutual conductance controlling terminal. The semiconductor amplification circuit also includes a pair of second and third MOS transistors, and a pair of fourth and fifth MOS transistors. Furthermore, the semiconductor amplification circuit has first and second current sources connected to the source and drain of the first MOS transistor, respectively, and third and fourth current sources connected to the drains of the fourth and fifth MOS transistors, respectively. In addition, the semiconductor amplification circuit includes a pair of differential output terminals and first and second capacitances.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: May 27, 2003
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Yamazaki
  • Publication number: 20030080786
    Abstract: A balanced transconductor having a pair of voltage inputs and a pair of current outputs comprises a pair of single-ended transconductors, one in each signal path and a cancellation network. The cancellation network cancels at the inputs to the single-ended transconductors a common mode voltage appearing at the voltage inputs so that no common mode output current results. The cancellation network may comprise four half-size single-ended transconductors drawing half the supply current of full-size single-ended transconductors.
    Type: Application
    Filed: September 24, 2002
    Publication date: May 1, 2003
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: John B. Hughes
  • Patent number: 6545620
    Abstract: Summarizing, the present invention provides an IVC (100), comprising an operational amplifier (110) with an inverting input (112) and an output (113), and a feedback resistor ladder network (120) coupled between the output (113) and the inverting input (112). The feedback resistor ladder network (120) comprises a main chain (121) composed of a plurality of substantially identical unit resistors (RU) connected in series, and a plurality of branches (124i), each branch (124i) coupling a node (Xi) in the main chain (121) to the inverting input (112) of the operational amplifier (110), each branch (124i) comprising a selectable feedback switch (123i). Further, some of the branches (124i) comprise a non-unit resistor (RNUi) coupled in series with the corresponding selectable feedback switch (123i). Further, the present invention provides a circuit comprising a FIRDAC (20) and a bias block (30) for providing at least one bias current for the FIRDAC (20).
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: April 8, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Willem Hendrik Groeneweg
  • Patent number: 6522175
    Abstract: A current/voltage converter includes a current source connected to a first node; a first transistor element connected between the first node and a power supply or ground; a second transistor element which is connected between a second node and the power supply or ground, whose control terminal is connected to that of the first transistor element; a first control circuit which controls the voltages of control terminals of the first and second transistor elements so that the voltage of the first node becomes substantially equal to that of a bias voltage as one of inputs to the first control circuit; a second control circuit controlling the voltage of the second node so as to become substantially equal to that of the first node; and a resistance element one end of which is connected to the second node, and which converts the current flowing through the second transistor element into a voltage.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: February 18, 2003
    Assignee: Kawasaki Microelectronics Inc.
    Inventors: Masayuki Ueno, Masatoshi Takada, Chie Serizawa
  • Publication number: 20030001628
    Abstract: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Applicant: Intel Corporation
    Inventors: Steven K. Hsu, Mark A. Anders, Ram K. Krishnamurthy
  • Patent number: 6483383
    Abstract: A current controlled complementary metal-oxide-semiconductor transconductive amplifier arrangement includes a first transconductive amplifier and a control circuit to control the transconductance of the first transconductive amplifier. The control circuit contains a second transconductive amplifier and an error amplifier formed in a feedback circuit, a current source to provide a current flowing through a resistor so as to supply an input voltage for the second transconductive amplifier, and a second current source and the output of the second transconductive amplifier coupled to the positive input of the error amplifier such that the transconductance of the second transconductive amplifier is in a linear relation with its bias current. The bias current of the first transconductive amplifier is mirrored from the bias current of the second transconductive amplifier by a current mirror, thus the transconductance of the first transconductive amplifier is linearly current controlled.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: November 19, 2002
    Assignee: Elan Microelectronics Corporation
    Inventor: Kao-Pin Wu
  • Patent number: 6483380
    Abstract: A GmC filter that suppresses unwanted signals generated by a GmC compression stage. The GmC filter utilizes the same compression stage for the decompression stages. By using the same compression stage for the decompression stages unwanted in-band signals generated by the compression stage are suppressed. Further, over all circuitry is decreased, power is saved, and GmC filter design is simplified.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: November 19, 2002
    Assignee: Conexant Systems, Inc.
    Inventors: Alyosha C. Molnar, Rahul Magoon
  • Publication number: 20020167344
    Abstract: A circuit structure for performing current amplification. The circuit structure may be standardized as a current amplifier cell such that many types of applications requiring current amplification may be created. The basic amplifier cell, which may accept voltage or current sources as an input signal, produces two identical output signals which may be used for feedback or serve as input to additional amplifier stages. This simple structure may be extended to perform current amplification with variable gain or AC or DC voltage-to-current conversion through the use of appropriately selected resistive elements.
    Type: Application
    Filed: February 8, 2002
    Publication date: November 14, 2002
    Inventors: Gang Zha, Solomon Ng
  • Patent number: 6480042
    Abstract: The invention provides a current-to-voltage converting circuit and an optical pickup head apparatus using the same. The current-to-voltage converting circuit converts, to a voltage signal, a current signal received from a photodetector which receives a light reflected on the recording medium such as an optical disk and provides a current signal corresponding to amount of the received light, for reproduction of data. The current-to-voltage converting circuit comprises a differential amplifier comprising transistors Q1 and Q2 applied with a negative feedback, current sources I1 and I2 for supplying the differential amplifier with two kinds of idling currents, and switches SW1 and SW2 for selecting current source I1 or I2 to determine the idling current to be supplied to the differential amplifier according to a level of the current signal received from the photodetector or a reflectance of the recording medium.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: November 12, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shin-ichi Kadowaki
  • Patent number: 6462586
    Abstract: A k-WTA circuit for selecting inputs which have a maximum-magnitude and outputting the results. k-WTA is very useful in pattern classification such as k-nearest neighbor classifier, Hamming neural classifier and some cascaded classification systems, since one classifier can not achieve very high performance, however, if a small set of candidates can be provided, for example k(k<<N), then a simple classifier with small complementary feature sets can be cascaded to realize multi-stage classification. A k-WTA network is necessary to implement this function. The circuit as disclosed in the invention provides a design for a circuit in which the number of inputs with maximum magnitudes at any one time can be chosen. The circuit can have a plurality of inputs each of which has a corresponding output. In one embodiment of the invention external inputs can select the number of maximum-magnitudes inputs to be selected through the use of a current positive feedback loop.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: October 8, 2002
    Assignee: Winbond Electronics Corp.
    Inventors: Bingxue Shi, Guoxing Li
  • Patent number: 6459247
    Abstract: The present invention relates to a power supply capable of being configured to produce an equivalent negative output resistance or to produce both negative and positive output resistances. The power supply comprises components that can provide equivalent output resistance values that transition from negative values through zero to positive values, and vice versa. By selecting an appropriate negative output resistance for the power supply, the power supply can compensate for the load lead voltage drop caused by the elements (e.g., cabling) between the output sense leads of the power supply and the load. This allows the voltage level provided to the load to be set, or controlled, by setting a voltage level VSET at the power supply. Preferably, a multiplier chip is used that enables the output resistance values of the power supply to be programmably varied from a negative resistance value through 0 to a positive resistance value, and vice versa.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: October 1, 2002
    Assignee: Agilent Technologies, Inc.
    Inventor: Michael Joseph Benes
  • Patent number: 6452427
    Abstract: A dual output capacitance interface circuit (100) based on switched capacitor circuits and charge subtraction technique provides both voltage output (104) and frequency output (106). The circuit is programmable independently with sensitivity and offset adjustment, and is insensitive to fixed stray capacitance. Temperature compensation methods are described.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: September 17, 2002
    Inventors: Wen H. Ko, Qiang Wang
  • Patent number: 6445220
    Abstract: A method and apparatus for a half-circulator is described. In one embodiment, the half-circulator may be used in a bus between processing units or other logical blocks using small-signaling with current-mode logic. For this reason, the half-circulator implements addition and subtraction of small-signal currents. Using small-signal signaling, the half-circulator (and the bus containing half-circulators by extension) improves robustness against noise from the power supply lines, and minimizes the added jitter suffered by other schemes when implemented on a bus with several tapping nodes.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: September 3, 2002
    Assignee: Intel Corporation
    Inventor: Luiz M. Franca-Neto
  • Patent number: 6437609
    Abstract: An integrated circuit card receives power in the form of a radio frequency signal and includes a voltage generator that produces a first power supply voltage. The card also includes a voltage booster circuit for producing a high voltage that receives the first power supply voltage at a first supply input terminal. The voltage booster circuit also receives a second power supply voltage higher than the first power supply voltage at a second supply input terminal.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: August 20, 2002
    Assignee: STMicroelectronics S.A.
    Inventor: Mohamad Chehadi
  • Publication number: 20020105363
    Abstract: The present invention discloses a current comparator having simple, cheap and fast characteristics, especially discloses a current comparator having a small dead zone and excellent driving capability. The current comparator of the present invention comprises a first CMOS transistor, a second CMOS transistor, a diode-configured N-type transistor, a fourth CMOS transistor and a fifth CMOS transistor.
    Type: Application
    Filed: June 26, 2001
    Publication date: August 8, 2002
    Inventors: Hong-Chin Lin, Jie-Hau Haung, Shyh-Chyi Wong
  • Publication number: 20020105362
    Abstract: This invention relates to an artificial neural network (ANN), particularly to a neuron circuit and its activation function including the derivative. The neuron circuit capable of generating an adjustable sigmoid-like function and a good approximation of its derivative, comprises: a current generator for generating a current; a current-controlled transistor for changing an output voltage according to the current from the current generator; and at least one differential pair of transistors for generating the adjustable sigmoid-like function output and the good approximation of its derivative by the changed output voltage.
    Type: Application
    Filed: December 19, 2000
    Publication date: August 8, 2002
    Applicant: WINBOND ELECTRONICS CORP.
    Inventors: Bingxue Shi, Chun Lu
  • Patent number: 6429699
    Abstract: This invention relates to an artificial neural network (ANN), particularly to a neuron circuit and its activation function including the derivative. The neuron circuit capable of generating an adjustable sigmoid-like function and a good approximation of its derivative, comprises: a current generator for generating a current; a current-controlled transistor for changing an output voltage according to the current from the current generator; and at least one differential pair of transistors for generating the adjustable sigmoid-like function output and the good approximation of its derivative by the changed output voltage.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: August 6, 2002
    Assignee: Winbond Electronics Corp.
    Inventors: Bingxue Shi, Chun Lu
  • Patent number: 6420912
    Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: July 16, 2002
    Assignee: Intel Corporation
    Inventors: Michael Pang-Cheng Hsu, Rajendran Nair, Stephen R. Mooney
  • Patent number: 6420911
    Abstract: A ballast circuit for operating a lamp provided with a voltage-current converter, the ballast circuit having a differential amplifier provided with a first input terminal for connection to a reference voltage source for generating a reference voltage, a second input terminal for connection of a reference resistor, and an output. A first current generator supplies a first current to the reference resistor. A current amplifier generates a second current and is provided with an input coupled to the output of the differential amplifier. The differential amplifier is provided with a low-pass filter. The current amplifier on the one hand and the current generator and the reference resistor on the other hand exclusively comprise mutually separate components. The ballast circuit is in addition provided with a current control circuit coupled to the current amplifier and to the current generator for influencing the first current dependent upon the second current.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: July 16, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Leonardus F. P. Warmerdam, Hendrik Boezen
  • Patent number: 6417702
    Abstract: A method and circuit are provided to perform current-to-voltage conversions. The circuit is operational in one linear mode based on channel-length-modulation effects in the saturation region and two non-linear modes based on a current operation overrunning the saturation region and a logarithmic function of drain current versus gate-to-source voltage, respectively. An adaptive process is provided to set-up the quiescent point of the circuit. The conversion gain is variable with respect to the conversion mode, the current range, and the length of the converting transistor.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: July 9, 2002
    Assignee: Concordia University
    Inventor: Chunyan Wang
  • Patent number: 6407589
    Abstract: A device to sense changes in current level almost instantaneously and convert those current levels, almost instantaneously, into voltage levels that may be used by a microprocessor for logical and mathematical operations. This device employs a current conveyer to receive two inputs representing current levels. Once a sufficient difference in current levels is detected by the current conveyer, the current from each input is passed to a P-sense amplifier that converts the current to an equivalent voltage level and amplifies that voltage level. Thereafter, two outputs are generated reflecting an amplified voltage of the current input.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: June 18, 2002
    Assignee: Intel Corporation
    Inventors: Liqiong Wei, Kevin X. Zhang
  • Patent number: 6400189
    Abstract: A buffer circuit includes an amplifier, a pass gate circuit and a level shifter. The pass gate circuit communicates an input signal to the amplifiers and includes a terminal to control the communication. A level shifter furnishes a control signal to the terminal of the pass gate circuit and regulates the control signal based on a magnitude of the input signal.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: June 4, 2002
    Assignee: Intel Corporation
    Inventor: Bart R. McDaniel
  • Patent number: 6392452
    Abstract: An input buffer circuit includes a first amplifier having low load impedance and a second amplifier having high load impedance. The output signals of the input buffer circuit have wide bandwidth, although the input buffer circuit has two stage amplifiers. In addition, the bandwidth can be controlled by resistors as an equivalent active inductance of the input buffer circuit. Further, the input buffer circuit can reduce the power consumption compared with conventional input buffer circuits, since the input buffer circuit according to the present invention uses a first switching current of the first amplifier as well as a second switching current of the second amplifier to load output signals.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: May 21, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Oh Lee
  • Publication number: 20020053929
    Abstract: A current/voltage converter includes a current source connected to a first node; a first transistor element connected between the first node and a power supply or ground; a second transistor element which is connected between a second node and the power supply or ground, whose control terminal is connected to that of the first transistor element; a first control circuit which controls the voltages of control terminals of the first and second transistor elements so that the voltage of the first node becomes substantially equal to that of a bias voltage as one of inputs to the first control circuit; a second control circuit controlling the voltage of the second node so as to become substantially equal to that of the first node; and a resistance element one end of which is connected to the second node, and which converts the current flowing through the second transistor element into a voltage.
    Type: Application
    Filed: October 9, 2001
    Publication date: May 9, 2002
    Applicant: Kawasaki Microelectronics Inc.
    Inventors: Masayuki Ueno, Masatoshi Takada, Chie Serizawa
  • Patent number: 6377084
    Abstract: Single input receivers and “pseudo differential” amplifiers can conserve scarce chip surface area and still provide fast response times in a low power CMOS environment. A first embodiment includes a single ended receiver. The single ended receiver includes a pair of cross coupled inverters. Each of the inverters includes a pair of output transmission lines. A single signal input node coupled to a source region for one of the pair of cross coupled inverters and to a current mirror such that the single ended receiver is able to convert a single ended input current received at the single signal input node into a differential input signal. A second embodiment includes a pseudo differential amplifier. The pseudo differential amplifier includes a pair of cross coupled transistors. The pseudo differential amplifier includes a pair of signal output nodes.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: April 23, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 6369618
    Abstract: A voltage to current conversion circuit is described. The circuit comprises a first differential amplifier for receiving an input voltage and producing an output voltage, and a second amplifier for converting the output voltage of the first amplifier to a current. The transfer function of the voltage to current conversion circuit is proportional to an exponential function that depends on the input voltage. The circuit is temperature and process independent. In a first preferred embodiment, the first amplifier comprises a first transistor for receiving an input voltage at its base terminal, a temperature dependent current source coupled to the emitter of the first transistor, and a positive voltage supply coupled to the collector through a diode coupled transistor, and a second transistor paired with the first transistor and having a base terminal coupled to an input voltage terminal, an emitter coupled to a temperature dependent current source, and a collector coupled to a voltage supply.
    Type: Grant
    Filed: January 24, 2000
    Date of Patent: April 9, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Bryan E. Bloodworth, Davy H. Choi, Mehedi Hassan
  • Patent number: 6362662
    Abstract: A winner-take-all (WTA) circuit apparatus for comparing two current inputs from a WTA circuit to a threshold current to create a reject signal, to assist in the decision criteria of a winner-take-all network. The circuit compares the two input currents from the WTA circuit by using NMOS transistors which perform electrical mathematical functions by manipulating the currents. The end result is that the difference of the two currents is compared with a reference current and a voltage level is outputted. The reference current is adjustable, and the invention also provides a WTA circuit with weighted inputs, and the ability to select between a 1-WTA, and a 2-WTA configuration. The invention therefore solves the problems of prior art by being capable of properly selecting current levels or rejecting current levels which are too close in value, with a voltage reject signal.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: March 26, 2002
    Assignee: Winbond Electronics Corp.
    Inventors: Bingxue Shi, Guoxing Li
  • Patent number: 6359503
    Abstract: An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node.
    Type: Grant
    Filed: August 12, 1997
    Date of Patent: March 19, 2002
    Assignee: SGS-Thomson Microelectronics, S.R.L.
    Inventors: Roberto Alini, Francesco Brianti, Valerio Pisati, Marco Demicheli
  • Patent number: 6346899
    Abstract: To provide a high-speed, high-resolution current mode D/A converter, the present invention provides: (1) a current mode D/A converter comprising a resistor-type D/A converter circuit 2 having a digital decoder circuit 3, a plurality of resistors 5, and a plurality of switches turned on and off by the digital decoder circuit 3 and a highly linear transconductor 4 for receiving voltage output from the resistor-type D/A converter circuit 2 and providing current output; and (2) a transconductor comprising a first transistor differential pair and a second transistor differential pair connected to each other with their polarities reverse and having different transconductance values and current sources connected to the first and second transistor differential pairs respectively, wherein different signal voltages being proportional to input signal voltages input to the transconductor are applied to the first and second transistor differential pairs.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: February 12, 2002
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventor: Khayrollah Hadidi
  • Publication number: 20020011878
    Abstract: The invention provides a current-to-voltage converting circuit and an optical pickup head apparatus using the same. The current-to-voltage converting circuit converts, to a voltage signal, a current signal received from a photodetector which receives a light reflected on the recording medium such as an optical disk and provides a current signal corresponding to amount of the received light, for reproduction of data. The current-to-voltage converting circuit comprises a differential amplifier comprising transistors Q1 and Q2 applied with a negative feedback, current sources I1 and I2 for supplying the differential amplifier with two kinds of idling currents, and switches SW1 and SW2 for selecting current source I1 or I2 to determine the idling current to be supplied to the differential amplifier according to a level of the current signal received from the photodetector or a reflectance of the recording medium.
    Type: Application
    Filed: July 3, 2001
    Publication date: January 31, 2002
    Inventor: Shin-ichi Kadowaki
  • Patent number: 6339355
    Abstract: An offsetting comparator device includes master and slave comparator circuits and a reference differential voltage generator. The master comparator circuit supplies a sensed current corresponding to a potential difference represented by a differential signal on a transmission line. The reference differential voltage generator generates a reference differential voltage based on an intermediate potential of the differential signal. And the slave comparator circuit supplies a current corresponding to the potential difference as offset current. The offsetting comparator device outputs a differential current between the sensed and offset currents and therefore shows an offset in its input/output characteristics. The master and slave comparator circuits have the same circuit configuration.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: January 15, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Yamauchi, Yutaka Terada
  • Patent number: 6337596
    Abstract: In a source-type constant current driver circuit for driving an LED, a current of 1/&bgr; times a reference current is generated from a base current of a transistor Q2 for generating the reference current by means of the current mirror circuit composed of a transistor pair Q1a, Q1b. Further, the current generated by the current mirror circuit is amplified by a factor of n by means of a current mirror circuit composed of a transistor Q3 and one of transistors Q5a to Q5h. Then the amplified current is supplied to a base current of a transistor Q8. Thus, a base current of the transistor Q8 in a final stage is controlled.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: January 8, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Shimozono
  • Patent number: 6337585
    Abstract: To control the transconductance of a transconductor, its voltage input terminal (Vin2) is connected to the base of a first and a second transistor (Q21, Q22) via respective capacitors (C21, C22). The interconnection points between the capacitors (C21, C22) and the respective base are connected to the respective control voltage terminal (Vreg2+, Vreg2−) of the transconductor via a first and a second resistor (R21, R22), respectively. The emitters of said first and second transistors (Q21, Q22) are inter-connected, and the interconnection point is connected to a ground terminal via a third resistor (R23). The collector of the first transistor (Q21) is connected to the current output terminal (Iout2) of the transconductor, and the collector of the second transistor (Q22) is connected to the supply voltage terminal (Vcc2) of the transconductor.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: January 8, 2002
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Pär Svalange
  • Patent number: 6335642
    Abstract: A impedance-to-voltage converter for converting an impedance of a target to a voltage is described which comprises an operational amplifier (OP), a coaxial cable consisting a signal line and shielding element(s), and an AC signal generator. A feedback impedance circuit is connected between output and inverting terminals of the OP, and whereby a non-inverting terminal and the inverting terminal are an imaginal-short condition. One end of the signal line is connected to the inverting input terminal of the OP and the other end is connected to one electrode of the target and the AC signal generator is connected to the non-inverting input terminal of the OP. The shielding element comprises at least one shielding layer surrounding the signal line and is connected to the non-inverting input terminal of the OP, and thus the signal line and the shielding layer are the same voltage due to the imaginal-short of the input terminals of the OP, resulting in reduction of noise on the signal line.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: January 1, 2002
    Assignees: Sumitomo Metal Industries Limited, Hokuto Electronics Inc.
    Inventors: Tatsuo Hiroshima, Koichi Nakano, Muneo Harada, Toshiyuki Matsumoto, Yoshihiro Hirota