Abstract: Described embodiments provide circuits, systems and methods for generating a sensing signal in response to the ambient condition, comparing the sensing signal to a threshold hysteresis range to generate a digital signal, and upon powering on the sensor, determining whether the sensing signal is within the threshold hysteresis range and, if the sensing signal is within the threshold hysteresis range, setting the digital signal to a predetermined level based on a hysteresis restoration state associated with sensor before the sensor is powered off.

Abstract: A receiver circuit may be provided. The receiver circuit may include a delay circuit and a synchronization circuit. The delay circuit may variably delay a data strobe signal based on a delay select signal. The synchronization circuit may generate internal data from data in synchronization with the variably delayed data strobe signal.

Abstract: There is provided a CMOS inverter circuit device. The CMOS inverter circuit device includes a delay circuit unit configured to generate different charge and discharge paths of each gate node of a PMOS transistor and an NMOS transistor respectively at the time that an input signal transitions between high and low levels. Therefore, the present examples minimize or erase generation of a short circuit current made at the time that the input signal transition. The examples may simplify circuit architecture, and may make a magnitude of a CMOS inverter circuit device smaller.

Abstract: A semiconductor device includes: a bootstrap capacitor charged via a diode when a low-side switching device is ON, a resulting charge voltage being applied to a high-side driver circuit when the low-side switching device is OFF; a supplementary bootstrap capacitor charged when the low-side switching device is OFF; a Zener diode that regulates a charge voltage of the supplementary bootstrap capacitor; and a control circuit that applies the charge voltage of the supplementary bootstrap capacitor to the high-side driver circuit via a switch circuit when the charge voltage of the bootstrap capacitor decreases to less than a prescribed voltage while a high-side switching device is ON.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: A transistor monolithically integrated in a semiconductor body includes a first sub-transistor and a second sub-transistor that both include a first and second load contacts and a control contact for controlling an electric current through a load path. The first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor. A control circuit is configured to cause the first sub-transistor to switch from a first state to a second state at a first point of time and to cause the second sub-transistor to switch from the first state to the second state at a second point of time subsequent to the first point of time.

Abstract: A device (100) for activating an electrical consumer (105) includes a controllable current source (140) for providing a control current, a switching unit (115) for controlling a consumer current as a function of the control current, and a sampling unit (145) for determining a time delay between an activation of the current source (140) and the enabling or interruption of the current flow by the switching unit (115). Furthermore, a processing unit (135) is provided, which is configured to determine that the current source (140) is defective if the time delay lies outside a predetermined range.

Abstract: An inverter phase leg has upper and lower gate drive circuits supplying gate drive signals to upper and lower transistors. Each gate drive circuit includes an active clamp for selectively deactivating the upper and lower transistors. The transistors are comprised of semiconductor devices, each having respective gate, source, and emitter terminals. Each emitter terminal is connected to a respective output electrode structured to enhance a common source inductance between the respective gate and emitter terminals. Each emitter terminal is further connected to a respective Kelvin emitter electrode substantially bypassing the respective output electrode. Each respective active clamp is connected between the respective gate terminal and Kelvin emitter electrode so that the active clamping function remains effective in the presence of the enhanced common source inductance.

Abstract: A CMOS output circuit includes a first P-MOSFET having a source connected to a power supply terminal, a drain connected to an output terminal, and a back gate connected to a first potential terminal; a first N-MOSEFET having a drain connected to the output terminal, a source connected to the ground terminal, and a back gate connected to a second potential terminal; a first potential switching portion arranged to switch whether to connect the first potential terminal to the power supply terminal or to the output terminal; a second potential switching portion arranged to switch whether to connect the second potential terminal to the ground terminal or to the output terminal; a first gate switching portion arranged to switch whether or not to short-circuit the gate of the first P-MOSFET to the first potential terminal; a second gate switching portion arranged to switch whether or not to short-circuit the gate of the first N-MOSFET to the second potential terminal; a first driver arranged to drive the gate of the

Abstract: A power circuit includes a power transistor flowing a power current to a ground according to the voltage of a driving node, a driving circuit, and a pre-driver. The driving circuit includes a high-side transistor providing a supply voltage to the driving node according to a high-side voltage of a high-side node, a low-side transistor coupling the driving node to the ground according to a first internal signal, and a charge pump coupled to the high-side node and the driving node and generating the high-side voltage that exceeds the supply voltage according to the first internal signal. The pre-driver generates the first internal signal according to a control signal. The pre-driver is configured to improve driving capability of the control signal.

Abstract: Apparatuses and methods for power regulation based on input power using circuitry are disclosed herein. An example apparatus may include a reference circuit configured to receive a first voltage and a second voltage and to provide an output reference voltage at an output node having a value equal to the second voltage subtracted from the first voltage. The reference circuit may be configured to mirror a current of a first circuit coupled between the second voltage and a reference voltage through a second circuit coupled between the first voltage and the output node. The example apparatus may further include a power circuit configured to provide a third voltage based on the output reference voltage. The third voltage may have a value that is equal to the output reference voltage.

Abstract: To provide an electronic circuit and the like capable of extending the life greatly even when the transistors constituting the electronic circuit have property fluctuation. The electronic circuit includes switching-target circuits and a switching circuit for switching the switching-target circuits to an operating state from a stop state. The switching-target circuits include the switching-target circuit in an operating state and the switching-target circuit in an initial-to-stop state. Property fluctuation is generated in the transistors forming the switching-target circuits and the switching target due to an electric stress applied to the transistors. The switching circuit switches the switching-target circuit in the initial-to-stop state to an operating state by the transistor of the switching circuit.

Abstract: A transmit driver or transmitter is provided to generate an output data signal based on different input modes, such as low speed (LS), full speed (FS), high speed (HS), and high speed interconnect (HSIC) modes of a Universal Serial Bus (USB) standard. The transmit driver includes a rail voltage generator for generating a rail voltage for a set of transmit driver slices based on the selected mode. The transmit driver includes a bias voltage generator for generating a bias voltage based on the selected mode for protecting transistors in the transmit driver slices from over-voltage stress. The transmit driver includes a predriver and level shifter for generating input signals for the transmit driver slices to set the output impedance of the transmit driver and the slew rate of the output data signal. The transmit driver includes an emphasis equalizer for providing controllable emphasis equalization to the output data signal.

Abstract: An output circuit includes a first transistor, a second transistor, an operational amplifier that outputs a control voltage, and a switch circuit that controls voltage output in accordance with a control signal. When the control signal is in a first state, the switch circuit supplies the control voltage to the gate of the first transistor to turn on the first transistor and electrically connects the drain of first transistor to the operational amplifier so that a first output voltage is output from the drain of the first transistor. When the control signal is in a second state, the switch circuit supplies the control voltage to the gate of the second transistor to turn on the second transistor and electrically connects the drain of the second transistor to the operational amplifier so that a second output voltage is output from the drain of the second transistor.

Abstract: A drive circuit includes a control circuit configured to output a polarity signal for controlling ON/OFF of a driving switch, a pulse transformer, electrically connected to the control circuit, configured to transmit the polarity signal, and a discharge circuit, electrically connected to the pulse transformer and a gate terminal of the driving switch, configured to discharge an electric charge accumulated in the gate terminal based on the polarity signal. When the polarity signal having a first polarity is applied to the gate terminal through the pulse transformer, the driving switch is switched to and maintained in an ON state by accumulating the electric charge in the gate terminal. When the polarity signal having a second polarity different from the first polarity is applied to the discharge circuit through the pulse transformer, the driving switch is switched to an OFF state by discharging the electric charge by the discharge circuit.

Abstract: An electrical waveform generating circuit has a pair of Pulse Amplitude Controlled Switching Current Sources (PACS). A gate pulse driver circuit is coupled to an input of each of the pair of PACS for sending gate pulses for driving the pair of PACS. A digital-to-analog converter (DAC) circuit is coupled to the gate pulse driver circuit for controlling amplitudes of the gate pulses. A transducer is coupled to the PACS.

Abstract: A system includes a signal generator and a signal combiner. The signal generator is configured to output a first signal having a first frequency and to output one or more signals having the first frequency and having phases shifted relative to the first signal by predetermined amounts. The signal combiner is configured to combine the first signal and the one or more signals to output a frequency multiplied second signal having a second frequency. The second frequency is greater than the first frequency.

Abstract: A gate drive circuit includes first and second transistors for turning on and off semiconductor switching devices. The circuit includes a DC power supply for driving the first and second transistors. The gate drive circuit further includes a third transistor, a fourth transistor, and a DC power supply being a power supply for the third and fourth transistors with a voltage value lower than the voltage value of the DC power supply, thereby making lower the impedance of the path of a current flowing from the DC power supply to the gates of the switching devices through the third transistor than the impedance of the path of a current flowing from the DC power supply to the gates of the switching devices through the first transistor.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Abstract: A bus driver is provided that can withstand over voltages being applied to its output terminal without the protection circuit detracting from the voltage swing that can be provided by the driver. The circuit arrangement also allows transistors having good on state resistance and large tolerance of drain-to-source voltages to be used.

Abstract: A power converter with a dynamic preload. The power converter includes a magnetic component coupled between an input and an output of the power converter. The output of the power converter has an output voltage for providing power to a load. A switch is adapted to control current through the magnetic component according to on and off times of the switch. A dynamic preload circuit is coupled to the output of the power converter. The dynamic preload has loading characteristics that are adjusted responsive to a signal indicative of an output voltage at the output of the power converter.

Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

Abstract: An integrated circuit (“IC”) includes an input receiver with multiple hysteresis levels. An exemplary input receiver may be an input buffer with a Schmitt trigger that has multiple hysteresis windows between different high and low input voltages. This circuit may improve the input noise immunity of the external input signals and timing by allowing for a selection one of the plurality of levels depending on parameters of the input (e.g. noise level).

Abstract: According to one aspect, embodiments of the invention provide a gate driver comprising a level shifter circuit configured to be coupled to a controller, to receive control signals from the controller, each control signal having a voltage with respect to a control ground, and to redefine the voltage of each control signal with respect to a chip ground to generate redefined control signals, a gate driver chip coupled to the level shifter circuit and configured to be coupled to at least one semiconductor device, the gate driver chip further configured to provide bipolar control signals to the at least one semiconductor device based on the redefined control signals, and at least one power source configured to provide at least one positive supply voltage to the gate driver chip and at least one negative supply voltage to the gate driver chip and to the chip ground.

Abstract: A pulse generator includes a first inverter configured to inverse an input pulse and output a result, a second inverter configured to inverse the output of the first inverter and output a result, a clamp inverter configured to generate a clamping voltage by clamping the output of the second inverter and generate an output pulse through a source follower which operates according to the clamping voltage, and a temperature compensator configured to compensate for variations in the clamping voltage caused by temperature change.

Abstract: Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor are coupled in order from a memory device voltage supply rail to a low voltage supply rail. Gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor are coupled with an output of a flying capacitor circuit that level-shifts an input signal by a difference between the memory device supply and core supply voltages, while gates of the thick-oxide PMOS transistor and the thin-oxide NMOS transistor receive the input signal via a buffer.

Abstract: An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits the high power domain input signal into a high voltage signal and a low voltage signal. A high voltage input receiver receives the high voltage signal to produce a received high voltage that is level shifted into a first input signal. A low voltage input receiver receives the low voltage signal to produce a second input signal. A logic circuit generates the output signal from the first input signal and the second input signal.

Abstract: A transmitter includes: a main pull-up driver suitable for pull-up driving an output node; and an auxiliary pull-up driver suitable for pull-up driving the output node based on a voltage of the output node, wherein the auxiliary pull-up driver compensates for non-linear driving current characteristics of the main pull-up driver.

Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Tr2 switches between whether or not to provide an output of an on-potential output unit 2 to a gate terminal of Tr1 in accordance with an output of a set control unit 3. The set control unit 3 controls a gate terminal of Tr2 into a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr1. The gate potential of Tr2 is raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr1, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.

Abstract: An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.

Abstract: A circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers.

Abstract: Described is an apparatus which comprises: a first node to provide an un-gated power supply; a second node to provide a threshold dependent supply; an inverter with an input and an output, the inverter coupled to the first and second nodes, the inverter to receive the un-gated power supply at its power supply node, and to receive the threshold dependent supply for supplying ground supply at its ground node; and a transistor with its gate terminal coupled to the output of the inverter, the transistor to provide gated power supply to one or more logic units.

Abstract: A signal transmission circuit with a first circuit in a signal transmission side having first and second semiconductor switch elements transmitting a reference potential or power supply voltage of the first circuit to a second circuit by being alternatively driven on and off according to a multiple of signals. The second circuit in a signal reception side having a voltage conversion circuit, including an in-phase noise filter that eliminates in-phase noise superimposed on the voltage transmitted via the first and second semiconductor switch elements, generating first and second pulse signals in accordance with the transmitted voltage, a latch circuit latching each of the first and second pulse signals with the first and second pulse signals as a clock, and a signal analysis circuit analyzing the first and second pulse signals latched by the latch circuit, and generating an output signal according to the category of the multiple of signals.

Abstract: Apparatuses and methods for power regulation based on input power using circuitry are disclosed herein. An example apparatus may include a reference circuit configured to receive a first voltage and a second voltage and to provide an output reference voltage at an output node having a value equal to the second voltage subtracted from the first voltage. The reference circuit may be configured to mirror a current of a first circuit coupled between the second voltage and a reference voltage through a second circuit coupled between the first voltage and the output node. The example apparatus may further include a power circuit configured to provide a third voltage based on the output reference voltage. The third voltage may have a value that is equal to the output reference voltage.

Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.

Abstract: A transmitting/receiving system may include a transmitting circuit and a receiving circuit. The transmitting circuit may include: a pull-up element suitable for pull-up driving a first node in response to a signal; a pull-down element suitable for pull-down driving a second node in response to the signal; and a voltage tailor coupled between the first and second nodes, and transmitting a low-swing signal obtained by reducing the swing amplitude of the signal to a transmission line, and the receiving circuit may include: a reference voltage generator having a replica circuit of the receiving circuit and suitable for generating a reference voltage; and a differential amplifier suitable for differentially amplifying the reference voltage and the low-swing signal received through the transmission line.

Abstract: Described is an apparatus comprising a first node to receive signal; a second node to provide an output signal; a voltage limiter circuit operating under a first supply voltage, the voltage limiter coupled to the first and the second nodes; and a bypass circuit operating under the first supply voltage, the bypass circuit coupled to the voltage limiter circuit and is capable of being enabled to electrically short the first node to the second node.

Abstract: First to N-th selection signals each instantaneously having a first logic level when representing selection and a second logic level when representing deselection are generated based on selection designation data. The first to N-th selection signals are individually latched, and first to N-th delayed selection signals are generated by individually delaying the first to N-th selection signals by a greater amount of delay when the latched selection signals transition from the first logic level to the second logic level than when the latched selection signals transition from the second logic level to the first logic level. A delayed data signal is selected corresponding to a delayed selection signal having the first logic level among the first to N-th delayed selection signals. The selected delayed data signal is output.

Abstract: An input/output circuit may include a driving unit including a first transistor coupled between a power supply voltage and a first node, and a second transistor coupled in series with the first transistor through the first node at an end of the second transistor. The input/output circuit may include switch elements coupled in parallel to a second node at another end of the second transistor, and the switch elements configured to be selectively turned on in an input operation and an output operation.

Abstract: Leakage current in a standby mode of a level shifter capable of operating with low voltage is reduced. Provided is a level shifter circuit in which an n-channel silicon transistor and an oxide semiconductor transistor are provide in series between an output signal line and a low potential power supply line. The potential of a gate electrode of the oxide semiconductor transistor is raised to a potential higher than input signal voltage by capacitive coupling, so that on-state current of the oxide semiconductor transistor is increased.

Abstract: A display driver comprises a plurality of driver stages. For each stage, a source node of a first transistor is coupled to a first power supply, a gate node is coupled to a first node, and a drain node is coupled to a first output end. A source node of a second transistor is coupled to the first output end and a gate node of is coupled to a second controller and a drain node is electrically coupled to a first input end. The first controller is coupled to a second input end and a third input end to provide sampled signals to the first node and a second output end. The second controller is coupled to the first controller and a second power supply. The first output end of each driver stage is coupled to the third input end of the next driver stage.

Abstract: A circuit includes a first power node, a second power node, an output node, a plurality of first transistors and a plurality of second transistors. The plurality of first transistors is serially coupled between the first power node and the output node. The plurality of second transistors is serially coupled between the second power node and the output node.

Abstract: An integrated circuit includes a clock distribution circuit and a logic block circuit. The clock distribution circuit is segregated from the logic block circuit to restrict contributors to phase noise to the clock distribution section of the circuit. The clock distribution circuit includes a front-end amplifier which buffers a clock input signal to a differential clock signal. The front-end amplifier is configured with as few components as possible and the components are selected for high current density and sized to minimize contributions to phase noise in the clock distribution circuit. The clock distribution circuit further includes an output latch circuit that receives the output signal of the logic block circuit and the low phase noise differential clock input signal from the front-end amplifier circuit. The output latch circuit re-clocks the final output of the integrated circuit. The output is representative of the output values determined by the logic block circuit.

Abstract: A circuit with a reduced leakage current is provided. A first transistor, a third transistor, and a second transistor are electrically connected in this order in series, a drain of the second transistor and a source of the third transistor are electrically connected to each other and are electrically connected to an output node. The first transistor is a p-channel transistor. The second and third transistors are n-channel transistors each including a semiconductor region including an oxide semiconductor. The third transistor functions as a switch that controls electrical connection between a drain of the first transistor and an output node of the circuit. In the standby mode, the third transistor is in an off state.

Abstract: A circuit buffer for outputting a voltage signal having a magnitude greater than a withstand voltage of any circuit element in the circuit buffer includes a first transistor and a second transistor. The first transistor includes a first terminal and a second terminal electrically connected to an input terminal and an output terminal of the circuit buffer respectively, a third terminal electrically connected to a first power supply terminal, and a fourth terminal electrically connected to the third terminal of the first transistor. The second transistor includes a first terminal and a second terminal electrically connected to the input terminal and the output terminal of the circuit buffer respectively, a third terminal electrically connected to a second power supply terminal, and a fourth terminal electrically connected to the third terminal of the second transistor. Voltages of the first and second power supply terminal are switched between two different levels, respectively.

Abstract: A circuit for operating a half-bridge is provided. The circuit may include a first multiplier circuit. The first multiplier circuit may be configured to multiply a first signal by a first factor to provide a turn-on signal. The turn-on signal may be configured to turn a first switch of the half-bridge on. The first multiplier circuit may be further configured to multiply the first signal by a second factor to provide a turn-off signal. The turn-off signal may be configured to turn a second switch of the half-bridge off. The first factor and the second factor may be chosen so that the second switch is turned off before the first switch is turned on.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract: A setting unit sets a high-voltage set value. A first generation unit generates a high voltage based on the set value set by the setting unit and a first reference voltage supplied from a supply unit. A second generation unit generates a second reference voltage by being supplied with the first reference voltage from the supply unit. A comparing unit compares the first reference voltage with the second reference voltage. A storage unit stores a comparison result that has been obtained in advance by the comparing unit comparing the first reference voltage with the second reference voltage. A correction unit corrects the high-voltage set value based on a comparison result that is obtained by the comparing unit when the image forming apparatus is in use and the comparison result that has been obtained in advance and is stored in the storage unit.

Abstract: A liquid discharge apparatus includes a piezoelectric element in which a drive signal is applied and which is displaced to eject a liquid; a zeroth wire of a zeroth potential; a first wire of a first potential that is higher than the zeroth potential; a second wire of a second potential that is higher than the first potential; and a connection path selecting section that electrically connects one end of the piezoelectric element to the zeroth wire, the first wire, or the second wire in response to a voltage of a source drive signal that controls the voltage of the drive signal and a hold voltage of the piezoelectric element. Here, a first potential difference from the zeroth potential to the first potential is different from a second potential difference from the first potential to the second potential.