Abstract: An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.

Abstract: Variations of the impedance of each output driver of a semiconductor device can be reduced, and high-speed calibration is achieved. A calibration circuit including a replica circuit having the same configuration as each pull-up circuit or pull-down circuit included in an output driver of a semiconductor device is provided within a chip. During a first calibration operation, the replica circuit is provided with voltage conditions that allow the maximum current to flow through the output driver so that an impedance of the replica circuit is equal to a value of an external resistor. During a second calibration operation, table parameters obtained in the first calibration operation are used to adjust the impedance of the output driver without use of the replica circuit.

Abstract: The invention provides a current detection circuit for a transistor, that does not influence a current flowing through the transistor, and minimizes a power loss, an increase of the pattern area and so on. A current detection circuit includes a wiring connected to a MOS transistor and forming a current path of a current of the MOS transistor, a current detection MOS transistor of which the gate is connected to the wiring, that flows a current corresponding to the potential of the gate, and a current detector detecting a current flowing through the current detection MOS transistor. The current detection circuit is configured including a load resistor connected to the current detection MOS transistor and a voltage detection circuit detecting a drain voltage of the current detection MOS transistor.

Abstract: There is provided an output stage comprising: a phase splitter for receiving an input signal and for generating first and second drive signals of opposite phase in dependence thereon; a DC offset signal generator for generating a DC offset signal; an adder for adding the DC offset signal to the first drive signal to provide a first modified drive signal; a subtractor for subtracting the DC offset signal from the second drive signal to provide a second modified drive signal; a first drive transistor associated with a first power supply voltage, for generating a first output signal in dependence on the first modified drive signal; a second drive transistor associated with a second power supply voltage, for generating a second output signal in dependence on the second modified drive signal; and a combiner for combining the first and second output signals to generate a phase combined output signal.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

Abstract: A Schmitt trigger circuit includes a first inverter having an input coupled to an input terminal; a second inverter having an input coupled to the input terminal; a first transistor having a source coupled to VDD, a drain coupled to an output of the first inverter, and a gate coupled to an output terminal; a second transistor having a source coupled to ground, a drain coupled to an output of the second inverter, and a gate coupled to the output terminal; a third transistor having a source coupled to VDD, a drain coupled to the output terminal, and a gate coupled to the output of the first inverter; and a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter.

Abstract: An edge triggered flip-flop circuit is disclosed with a clock signal, an input signal, a switch module using the clock signal for defining a data passing window, and a latch module for receiving the input signal during the data passing window.

Abstract: A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

Abstract: In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

Abstract: A single-ended to differential converter is presented. The converter may be configured to convert full-swing single-ended signals to low-swing differential signals within a single-stage, thereby reducing signal distortion. The converter may include a passive network of resistive elements, for example resistors and/or metal oxide semiconductor (MOS) devices operating in a linear region. The converter may also allow for adjustable design parameters such as a common mode, differential amplitude, and an output swing. The adjustments may all be made within the single-stage of the converter.

Abstract: The invention provides a switching circuit of a power semiconductor device having connected in parallel SiC diodes with a small recovery current, capable of significantly reducing turn-on loss and recovery loss without increasing the noise in the MHz band, and contributing to reducing the loss and noise of inverters. The present invention provides a switching circuit and an inverter circuit of a power semiconductor device comprising a module combining Si-IGBT and SiC diodes, wherein an on-gate resistance is set smaller than an off-gate resistance.

Abstract: An output driver includes: a pull-up signal generation unit configured to control a pulse width of first data and output a pull-up pre-drive signal; a pull-down signal generation unit configured to control a pulse width of second data and output a pull-down pre-drive signal; a pull-up pre-driver unit configured to receive the pull-up pre-drive signal and generate a pull-up main drive signal; a pull-down pre-driver unit configured to receive the pull-down pre-drive signal and generate a pull-down main drive signal; a pull-up main driver unit configured to charge an output node according to the pull-up main drive signal; and a pull-down main driver unit configured to discharge the output node according to the pull-down main drive signal.

Abstract: Disclosed is a semiconductor device having an output driver and a driver replica. The output driver is based on a scalable low-voltage signaling technology and capable of operating on low power and making automatic adjustments of output characteristics in accordance with the magnitude of a reference current. The driver replica, which is a duplicate of the output driver, adjusts the magnitude of the reference current in accordance with the difference between its own output and a reference voltage and outputs the adjusted current to the output driver.

Abstract: A pre-drive circuit with an output buffer that may contain a bootstrap circuit is described. The bootstrap circuit may be configured to output a voltage level greater in magnitude than the supply voltage that the bootstrap circuit is coupled with. The pre-drive circuit may contain a timing circuit. The timing circuit may be configured to at least partially determine when the bootstrap circuit outputs a voltage greater in magnitude than the supply voltage. The pre-drive circuit may also contain a pre-drive buffer circuit. This pre-drive buffer circuit may be capable of three outputs: (1) logical zero, or roughly electrical ground; (2) logical one, or roughly the level of the voltage supply, and (3) an outputted voltage greater than the voltage supply.

Abstract: A switching device includes a first switch disposed between a power source voltage and an intermediate node, the first switch forming a current path on the basis of an input signal, a second switch disposed between the intermediate node and a ground, the second switch forming a current path on the basis of a voltage of the intermediate node, and a transmission gate receiving the input signal, the transmission gate outputting the input signal on the basis of the voltage of the intermediate node.

Abstract: Provided is a gate signal line driving circuit including: 2n clock signal lines where 2n-phase clock signals are input in the normal order of the sequence in normal-directional scanning and in the inverse order of the sequence in inverse-directional scanning, respectively; and a plurality of basic circuits, each being connected with the 2n clock signal lines and outputting a gate signal from an output terminal, in which each of the basic circuits includes a high-voltage applying switching circuit where one clock signal line is connected to an input side and applies a voltage applied to the clock signal line to the output terminal and an off-signal applying switching circuit that applies an off-voltage to a switch of the high-voltage applying switching circuit, and a clock signal line where a clock signal having an inverse phase is connected to a switch of the off-signal applying switching circuit.

Abstract: A level shifter includes first and second input terminals, first and second output terminals, first pull-down circuitry operable to pull down one of the first and second output terminals responsive to signals present on the first and second input terminals, first pull-up circuitry operable to pull up the first output terminal responsive to a signal present on the second output terminal or pull up the second output terminal responsive to a signal present on the first output terminal, and second pull-up circuitry operable to pull up one of the first and second output terminals responsive to the signals present on the first and second input terminals.

Abstract: A transistor driver includes an inductor coupled to a gate terminal of a transistor and a switching circuit coupled to the inductor and configured to charge a capacitance at a gate terminal of the transistor from a source via the inductor responsive to a first state of a control input, to block discharge of the charged capacitance responsive to a voltage at the gate terminal and to return charge from the charged capacitance to the source responsive to transition of the control input to a second state. The switching circuit may include a switch coupled in series with the inductor and the source and configured to conduct responsive to transition of the control input to the first state and a rectifier coupled in series with the inductor and the source and configured to block discharge of the charged capacitance responsive to the voltage at the gate terminal.

Abstract: A power switching circuit designed for operating in a radiation environment using non-radiation hardened components is provided. The power switching circuit provides a high-voltage rated, non-radiation hardened N-channel FET (N-FET) controlled by a relatively small, low-voltage, non-radiation hardened P-channel FET (P-FET), while both devices are operating in a radiation environment. The P-FET device is drive by a sufficiently high drive voltage in order to overcome gate threshold shifts resulting from accumulated radiation damage.

Abstract: A PWM mode for turning on and off two output transistors by an output of a high impedance circuit and a constant voltage mode for controlling voltages at two output terminals by an output of an op amp are provided. Then, the two modes are switched by a switching signal.

Abstract: A level shifter includes a driving signal generating unit, a driving unit, and a current path forming unit. The driving signal generating unit is configured to generate a pull-up signal and a pull-down signal in response to an input signal, which may swing between a first high level and a first low level. The driving unit is configured to generate an output signal swinging between a second high level and a second low level in response to the pull-up signal and the pull-down signal. The current path forming unit is configured to form a current path between the pull-up signal and the pull-down signal in response to the pull-up signal and the pull-down signal.

Abstract: One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.

Abstract: Each of a plurality of gate driving parts outputs a first potential (2 V) during a period in which the gates of a plurality of thyristors belonging to the corresponding set are driven (S1N=Low) and outputs a second potential (5 V) that is higher than the first potential at a rising part of the anode driving voltage during a period in which the gates of a plurality of thyristors belonging to the corresponding set are not driven (S1N=High). Each of a plurality of gate driving parts outputs a third potential (3 V) that is lower than the second potential at periods other than the rising part of the anode driving voltage during a period in which the gates of a plurality of thyristors belonging to the corresponding set are not driven (S1N=High).

Abstract: A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.

Abstract: To obtain a gate driving circuit in which rising of a constant current of a constant current circuit is fast and power saving is achieved, the gate driving circuit includes: a constant current driving circuit (28) for supplying a constant current; a gate terminal of a power semiconductor element (1), which is connected to an output terminal of the constant current driving circuit; a comparator (22) for comparing a voltage at the gate terminal with a predetermined voltage value and outputting a signal indicating that the voltage is higher than the predetermined voltage value; and a driving control section (20) for increasing a current from the constant current driving circuit in response to a signal for turning on the power semiconductor element, and reducing the current from the constant current driving circuit in response to the signal from the comparator.

Abstract: The invention relates to a gate control device for a JFET-type transistor that has a gate, a drain and a source. The gate control device includes a voltage generation circuit comprising an output connected to the gate of the transistor, where the circuit is designed to generate at the output a reference gate-source voltage following a predetermined voltage ramp. A voltage limiting circuit is designed to limit the reference gate-source voltage to a predetermined maximum value when the gate-source voltage at the terminals of the JFET transistor has reached said maximum value.

Abstract: A processor frequency adjustment circuit for adjusting a frequency of a processor includes a voltage converting module, a first reference voltage generating module, a clock chip, a voltage comparing module. The voltage converting module converts a pulse voltage into a constant voltage. The first reference voltage generating module generates a first reference voltage. The voltage comparing module is connected with the voltage converting module, the first reference voltage generating module, and the clock chip to compare the constant voltage with the first reference voltage, and generates a first voltage level signal to a first terminal of the clock chip; the clock chip adjusts the frequency of the processor in response to obtaining the first voltage level signal.

Abstract: A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

Abstract: A switching device has a main IGFET having a Schottky barrier diode D3 for blocking an inverse current built therein, a protective switch means, and a protective switch control means. The protective switch means is connected in between a drain electrode D and a gate electrode G of the main IGFET. The protective switch control means turns on the protective switch means when an inverse voltage is impressed to the main IGFET. Thereby, the main IGFET is protected from the inverse voltage.

Abstract: A multi-stage drive circuit is to be coupled to a semiconductor switch having a drive terminal, a first terminal and a second terminal, to switch the semiconductor switch on and off. The multi-stage drive circuit includes a first drive circuit, a second drive circuit and a selector circuit. The first drive circuit is to be coupled to provide a first drive signal to the drive terminal of the semiconductor switch and the second drive circuit is to be coupled to provide a second drive signal to the drive terminal of the semiconductor switch. The selector circuit is to be coupled to turn on the first and second drive circuits to provide the first and second drive signals to the drive terminal, respectively. The selector circuit turns on the second drive circuit responsive to a voltage between the first and second terminals of the semiconductor switch falling to a threshold value.

Abstract: A transmitter includes a capacitor from one end of which a charge voltage is derived; a first constant current source to generate a charge current for the capacitor; a second constant current source to generate a discharge current for the capacitor; a charge/discharge controller to perform charge/discharge control of the capacitor based on a logic level of a transmission input signal and a comparison result between the charge voltage and a reference voltage; an output stage to generate the transmission output signal, wherein a slew rate of which is set in response to the charge voltage, and wherein an amplitude of the transmission output signal is set in response to an output side power source voltage; a reference voltage generator to fluctuate the reference voltage depend on the output side power source voltage; and a constant current controller to fluctuate a current value of the charge current and the discharge current depend on the reference voltage.

Abstract: A switching-control circuit, which causes a first transistor, having an input electrode to be applied with an input voltage and an output electrode connected to an inductor and a diode, to be turned on and kept on for a predetermined time period, includes: a comparison circuit to compare a feedback voltage corresponding to an output voltage with a reference voltage; a detecting circuit to detect a switching period of the first transistor; and a driving circuit to turn off a second transistor connected in parallel to the diode as well as turn on the first transistor to be kept on for the predetermined time period, and thereafter, turn off the first and second transistors, when the feedback voltage becomes lower than the reference voltage, and turn off the first transistor as well as turn on the second transistor, when the switching period becomes longer than a predetermined period.

Abstract: A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal.

Abstract: A constant impedance driver provides controlled output slew rates. The driver includes a plurality of buffers, each with an output impedance that is multiple of the output impedance of the driver. Outputs of buffers are coupled in parallel to form the output of the driver. Inputs to the buffers are coupled to an input signal or delayed versions of the input signal. The buffer inputs may be selectively coupled to taps of a delay line to provide selected slew rates on the output of the driver. The buffers may be selectively enabled to change or calibrate the output impedance of the driver.

Abstract: A semiconductor device including an internal terminal, a first transistor of a first conductivity type that is coupled between a first reference potential and the internal terminal, and that includes a first control terminal, a second transistor of a second conductivity type that is coupled between a second reference potential and the internal terminal, and that includes a second control terminal, an oscillator that includes an output terminal to output a clock signal, and a comparator that is coupled to the internal terminal, and that compares a potential of the internal terminal when the internal terminal is coupled to the first reference potential with a potential of the internal terminal when the internal terminal is coupled to the second reference potential. Each control terminals is coupled to the output terminal to commonly receive the clock signal, and the first and second transistors exclusively operate in response to the clock signal.

Abstract: A buffer circuit includes first and second inputs and first and second outputs. The buffer circuit is configurable to buffer a differential input signal received at the first and the second inputs to generate a differential output signal at the first and the second outputs in a current mode logic buffer mode based on a control signal. The buffer circuit is configurable to buffer the differential input signal to generate the differential output signal in an H-bridge buffer mode based on the control signal.

Abstract: An electronic device for driving a power switch coupled to receive a first supply voltage level at one side of its channel is provided. The electronic device includes a control switch coupled with a first side of a channel to receive a varying control voltage having a maximum level that is greater than a maximum voltage level of the first voltage supply and with another side of the channel to a control gate of the power switch for selectively applying the control voltage to the control gate of the power switch. The first side of the channel is coupled with the control gate of the control switch and a capacitor is provided and coupled with a first side to the control gate of the control switch and with a second side to a constant voltage supply.

Abstract: A high voltage switch circuit of a semiconductor device includes a buffer circuit configured to output a control signal in response to an input signal and a boost circuit configured to output a block selection signal to an output terminal by connecting a current path between a voltage supply node and the output terminal in response to the control signal, and to block the current path in case where the control signal falls from a high voltage level to a low voltage level.

Abstract: To include a switch transistor inserted between a data bus and an input end of a signal receiving circuit and turned off when a potential of the data bus reaches VPERI?NVth, and an assist transistor that drives the input end of the signal receiving circuit to have VPERI. According to the present invention, because the switch transistor and the assist transistor assist a receiving operation performed by the signal receiving circuit, amplitude of a transferred signal can be reduced without reducing a transfer rate. With this configuration, power consumed by charging or discharging of the data bus can be reduced.

Abstract: A low-side off-detection signal compares the gate signal of a low-side transistor with a predetermined first level to generate a low-side off-detection signal indicating that the low-side transistor is off. The low-side detection transistor is of the same type as the low-side transistor, with the source connected to the ground terminal, and the gate receiving the low-side transistor gate signal. A first resistor is arranged between the drain of the low-side detection transistor and the power supply terminal. A first bypass circuit is arranged in parallel with the first resistor, and is configured to switch to the conduction state when a control signal is a level which instructs the low-side transistor to switch off, and to switch to the cut-off state when the control signal level instructs the low-side transistor to switch on. The drain signal of the low-side detection transistor is output as the low-side off-detection signal.

Abstract: A semiconductor device includes a termination driver for driving a data line with a predetermined termination level by using an external power supply voltage and a drive current controller for controlling a drive current flowing into the data line from the termination driver in response to a voltage level of the external power supply voltage.

Abstract: A high voltage tolerant transceiver operating at a low voltage is provided, including two input/output pads to receive a receive signal and transmit a transmit signal; a transmitter block to transmit the transmit signal; a receiver block to receive the receive signal and provide an amplified signal; at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad. Also provided is a circuit to isolate the output of a transmitter from high voltages, including a first transistor and a second transistor. Also provided is a substrate isolating circuit, including a first transistor, a second transistor, and a third transistor so that the substrate voltage is isolated from a high voltage in the pads.

Abstract: A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type transistors connected to a positive power supply line, the source of the n-type transistors connected to a ground power supply line. The gates of the p and n-type transistors connected to a first and second input signals respectively. The drains of the p and n-type transistors connected to the drain wire. The p and n-type transistors arranged so that a difference between a number of n-type transistors connected to the drain wire and a number of p-type transistors connected to the drain wire between the first end of the drain wire and all distances along the drain wire being less than two.

Abstract: Improved digital driver with transition time control of an output stage output transistor of the digital driver. A predriver circuit has a resistor that forms an RC time constant with a feedback capacitor of the output transistor. The RC time constant is adjusted to control corner resolution of the output transistor in output switching. The RC time constant can be controlled by a digitally-controlled variable capacitor. Additionally, a delay may be introduced in the turning on of the output transistor as compared with the turn off time to reduce simultaneous conduction or shoot-through current.

Abstract: An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.

Abstract: A buffer circuit includes a first node receiving a first voltage, a second node receiving a second voltage lower than the first voltage, a third node, an output node driving the first voltage and the second voltage, a first transistor coupled between the first node and the output node, a second transistor coupled between the second node and the output node, one end of the second transistor being connected to the second node, another end of the second transistor being connected to the third node, and a switch circuit coupled between the output node and the third node. Both of the first transistor and the switch circuit include a transistor having a first breakdown voltage. The second transistor has a second breakdown voltage being different from the first breakdown voltage.

Abstract: An power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Abstract: A power gating circuit responds to a power enable signal to apply and withhold power to a MMIC. The gating circuit includes an OR gate and an AND gate, each coupled to the gate of a FET for controlling its conduction. One of the two FETs sources current to a load, and the other discharges the load. The gates are coupled so that the sourcing and discharge FETS are never turned ON simultaneously.