Abstract: A circuit includes a first current source, a second current source, a third current source and a fourth current source. A load includes a first terminal connected to a first node between the first current source and the second current source and a second terminal connected to a second node between the third current source and the fourth current source. A bias control module includes a first output configured to output a first bias signal to the first and fourth current sources and a second output configured to provide a second bias signal to the second and third current sources. A capacitance is connected to the first and second outputs of the bias control module.

Abstract: A circuit includes an inverter. The inverter inverts an input signal having an input low voltage level and an input high voltage level to form an output signal having an output high voltage level and an output low voltage level. Compared to the input high voltage level, the output high voltage level is lowered. Alternatively or additionally, compared to the input low voltage level, the output low voltage level is raised.

Abstract: A driver circuit includes an output transistor circuit that includes a first transistor of a first conductivity type and a second transistor of a second conductivity type disposed between a supply voltage source and a reference voltage source, and that outputs an output signal from a connection node between the first transistor and the second transistor, a first pre-buffer circuit that drives a gate of the first transistor in response to an input signal, and a second pre-buffer circuit that drives a gate of the second transistor in response to the input signal.

Abstract: A primary circuit turns on switching elements and generates energy from a direct-current power supply to a secondary circuit through a transformer. The secondary circuit charges a driven element using the energy obtained from the primary circuit through the transformer, turns on a switching element, discharges the energy accumulated in the driven element, and generates the energy in the primary circuit through the transformer. The primary circuit returns the energy obtained from the secondary circuit to the direct-current power supply.

Abstract: Included are embodiments of a 3-level line driver. At least one embodiment of a method includes generating a repetitive wave; receiving an input signal and a complement of the input signal; providing a 3-level output signal; and filtering a feedback signal, the means for filtering including at least one of the following: a 0th order filter, and an even order filter.

Abstract: A voltage buffer may include a first signal path extending from an input terminal to an output terminal in which the first signal path further may include a buffer transistor that may have a control terminal, and a first and second current terminals responsive to the control terminal. In the first signal path, the control terminal may be connected to the input terminal, the first current terminal may be connected to the output terminal, and the first signal path may supply a load current to a load device responsive to an input signal at the input terminal. The voltage buffer further may include a second signal path extending from the input terminal to a current source node. The second signal path may include a replica load device. The voltage buffer further may include a current source supplying substantially constant current and coupled to the current source node.

Abstract: A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

Abstract: A current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the output MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the output MOSFET to set the gate voltage of the output MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET.

Abstract: An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.

Abstract: A buffer circuit includes a biasing circuit operable to generate first and second biasing signals. A capacitive network includes an input adapted to receive an input signal and the capacitive network is operable responsive to the input signal to generate first and second bootstrapped signals. A push-pull stage includes first and second control inputs and an output. The push-pull stage is coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and is coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively. The push-pull stage is operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals.

Abstract: Apparatus and methods for providing multi-mode clock signals are disclosed. In some embodiments, a multi-mode driver configured to receive a first clock signal, and to selectively output a different clock signal in response to one or more signals from a controller is provided. The driver can include an H-bridge circuit without substantial increases in the size of the design area. Advantageously, lower jitter and improved impedance matching can be accomplished.

Abstract: A Group III-N high electron mobility transistor is driven by a high-voltage gate driver that limits the gate-to-source voltage across the transistor by controlling the maximum charge that can be placed on a boot strap capacitor that charges up the gate of the transistor to turn on the transistor.

Abstract: A self-luminous display device includes: pixel circuits; and a drive circuit, wherein each of the pixel circuits includes a light-emitting diode, a drive transistor connected to a drive current channel of the light-emitting diode, and a holding capacitor coupled to a control node of the drive transistor, the drive circuit applies a light emission enabling bias to the light-emitting diode after correcting the drive transistor and writing a data voltage to the control node, provides, during a light emission enabled period in which the light emission enabling bias is applied, a light emission interruption period adapted to change the light emission enabling bias to a non-light emission bias with the data voltage held by the holding capacitor, and performs a light emission disabling process, adapted to reverse-bias the light-emitting diode to stop the light emission, for a constant period after the light emission enabled period.

Abstract: In a first pair of stacked PMOS devices comprising a first PMOS device and a second PMOS device, a first pumping circuit is coupled between a gate of the first PMOS device and a P pre-driver signal. In a second pair of stacked NMOS devices comprising a first NMOS device and a second NMOS device, a second pumping circuit is coupled between a gate of the first NMOS device and an N pre-driver signal. The pumping circuits recognizing the transition from the pre-driver signals provide a voltage to the gate of the first PMOS device and of the first NMOS device so that the first PMOS and NMOS devices are turned on better. As a result, their voltage Vds peaks are suppressed to a safe level; the devices avoid hot-carrier degradations; and their lifetimes are prolonged.

Abstract: In accordance with an embodiment, a method of driving switches includes sensing a control node of a first switch, sensing a control node of a second switch, and driving the control node of the first switch to a first active state after the control node of the second switch transitions to a second active state. The method also includes driving the control node of the second switch to a second inactive state after the control node of the first switch transitions to a first inactive state. Driving the control node of the first switch is based on sensing the control node of the second switch, and driving the control node of the second switch is based on based on sensing the control node of the first switch.

Abstract: An integrated gate driver circuit includes an output drive circuit and a voltage stabilizing circuit. The voltage stabilizing circuit is configured to stabilize an output voltage outputted by the output drive circuit thereby reducing the ripple of the output voltage.

Abstract: A semiconductor device includes a slew rate controller configured to receive a mode register set signal and data and to activate a driving strength control signal for controlling the driving strength of a driving unit using the data in response to a code value of the mode register set signal. The driving unit is configured to pull a data output terminal up and down in response to the driving strength control signal.

Abstract: A circuit for actuation of a transistor. One embodiment provides an actuation output for connection to the actuation connection of the transistor. A measurement arrangement is provided for ascertaining a load current flowing through the load path or a voltage across the load path and for providing a measurement signal. An actuation current source having an actuation current output is connected to the actuation output and supplied with the measurement signal and designed to produce an actuation current at the actuation current output. The actuation current is at a current level dependent on the measurement signal.

Abstract: A driver circuit transmits a signal generated by a signal level generation circuit to a circuit to be measured by transmitting the signal to a output buffer circuit via a circuit (prebuffer circuit) that drives the output buffer circuit and causing the output buffer circuit to drive a transmission line. The driver circuit includes the prebuffer circuit and a replica buffer circuit formed by imitating the prebuffer circuit. The prebuffer circuit and the replica buffer circuit are disposed in parallel. The driver circuit temporarily increases input bias current to be supplied to output-stage transistors of the output buffer circuit on the basis of output current of the replica buffer circuit during transition of an input or output signal.

Abstract: The invention relates to a method for switching without any interruption between two winding taps (tap n, tap n+1) of a tap-changing transformer, wherein each of the two winding taps is connected to the common load output line via in each case one mechanical switch (Ds) and a series circuit, arranged in series thereto, comprising two IGBTs (Ip, In) which are switched in opposite directions.

Abstract: To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.

Abstract: A sinusoidal waveform generation circuit is configured to continuously control a voltage applied to a gate of a MOSFET to change an output current in the form of a sinusoidal wave by utilizing, as an electric characteristic specific to the MOSFET, a characteristic between a voltage applied to a gate of a MOSFET and an output current. The waveform of the sinusoidal wave generated by the sinusoidal waveform generation circuit is not a combination of a plurality of linear lines but is continuous and smooth. As a result, noises generated by the sinusoidal waveform generation circuit can be reduced.

Abstract: Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain boundary along the output paths that generate the differential signal is staggered, such that the boundary occurs at an odd numbered stage in one differential output path and at an even numbered stage in the other differential output. Defining the power supply domain boundary in this manner can help ensure that the same logical state is present at the boundary in either of the differential output paths. This same logic signal should affect subsequent stages similarly from a speed perspective, and so should similarly affect the differential signals generated by each of the output paths.

Abstract: The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port.

Abstract: A current sensing approach makes use of two shunts in series, embedded in a switching fabric, each shunt the object of a differential measurement of voltage drop across the shunt. Methodical make-before-break cycling of the switches in the switching fabric permit real-time or very near-real-time measurement of nearly all of the errors such as offset errors present in each differential-measurement path. Additional differential measurement paths can be connected with the shunts, with RFI filtering at shorter time constants to serve electronic fuse needs.

Abstract: A capacitive load driving device includes a drive waveform generator adapted to generate a drive waveform signal, a subtraction section adapted to output a differential signal between the drive waveform signal and two feedback signals, a modulator adapted to perform pulse modulation on the differential signal to obtain a modulated signal; a digital power amplifier adapted to power-amplify the modulated signal to obtain an amplified digital signal, a low pass filter including an inductor and a capacitor, and adapted to smooth the amplified digital signal to obtain a drive signal of a capacitive load, a first feedback circuit adapted to feedback the drive signal to the subtraction section as a first feedback signal, and a second feedback circuit adapted to set forward a phase of the drive signal and to feed back the drive signal to the subtraction section as a second feedback signal.

Abstract: A spread-spectrum circuit including an inverter, a current source, a control unit and a shaping circuit is provided. An input terminal of the inverter receives an original clock signal. The current source is coupled to a current transmission terminal of the inverter. The control unit includes a control circuit, and changes the current magnitude of the current source according to the original clock signal to control the charging/discharging speed of an output terminal of the inverter, so that the output terminal outputs a voltage signal. The shaping circuit shapes the voltage signal into a spread-spectrum clock signal.

Abstract: To operate a semiconductor power switch having a control electrode and a reference electrode in response to first and second switching commands, a control voltage between a first electric pole and a second electric pole is provided. Upon each first switching command, the control electrode is coupled to the first electric pole, and the reference electrode is coupled to the second electric pole; and upon each second switching command, the control electrode is coupled to the second electric pole, and the reference electrode is coupled to the first electric pole. Upon each switching command, continuously transitioning an electric potential of the one of the control and reference electrodes during a first transition period, and continuously transitioning an electric potential of the respective other of the control and reference electrodes during a second transition period occurs, wherein the first transition period beginning before and ending after the second transition period.

Abstract: Disclosed is a circuit arrangement for generating a drive signal for a transistor. In one embodiment, the circuit arrangement includes a control circuit that receives a switching signal, a driver circuit that outputs a drive signal, and at least one transmission channel. The control circuit transmits, depending on the switching signal for each switching operation of the transistor, switching information and switching parameter information via the transmission channel to the driver circuit. The driver circuit generates the drive signal depending on the switching information and depending on the switching parameter information.

Abstract: An output circuit includes a first differential pair of transistors driven by a first current source and differentially receiving input signals and a second differential pair of transistors driven by a second current source and differentially receiving first control signals (EMT, EMB). Output pairs of the first and second differential pairs are connected to the differential output terminals. A load resistor element pair is connected between a power supply and the differential output terminals. The output circuit further includes a third differential pair of transistors driven by a third current source and differentially receiving second control signals and a fourth differential pair of transistors driven by a fourth current source and differentially receiving third control signals. An output pair of the third differential pair of transistors is connected between one of the differential output terminals and the power supply.

Abstract: The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Abstract: A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

Abstract: A semiconductor device has: a pull-up circuit connectable to an internal terminal; a pull-down circuit connectable to the internal terminal; and an operation mode switch circuit. The operation mode switch circuit switches an operation mode based on a potential of the internal terminal when the pull-up circuit is connected to the internal terminal and a potential of the internal terminal when the pull-down circuit is connected to the internal terminal.

Abstract: An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Abstract: A method and an apparatus for implementing a semiconductor switch multi-stage drive circuit. The disclosed method and an apparatus reduce losses in a semiconductor switch when it is turned from an off state to an on state or from an on state to an off state. The reduction in losses is achieved without influencing the dv/dt across the semiconductor switch during a first time period while the semiconductor switch is switching. This reduction in losses is therefore achieved with very little increase in the noise generated due to rapid dv/dt during the first time period when the semiconductor switch is switching. The configuration of the circuitry to achieve this reduction in switching losses is such that benefits are less sensitive to manufacturing tolerances and temperature effects than alternative semiconductor switch drive schemes to achieve similar results.

Abstract: An open loop modulation network for a voltage regulator including a latch network, an output sense network, a timing network, and pulse control logic. The latch network latches assertion of a pulse control signal and provides a corresponding latched control pulse indication. The output sense network detects initiation of an output pulse and provides a corresponding output pulse indication. The timing network initiates a delay period in response to the output pulse indication and resets the latched control pulse indication after expiration of the delay period. The pulse control logic terminates the output pulse after the latched control pulse indication is reset and the pulse control signal is negated, whichever occurs last. Very narrow input pulses are detected and either a minimum output pulse is generated or the output pulse is based on the pulse control signal.

Abstract: In a semiconductor device, a high-side driver is arranged in a region closer to a periphery of a semiconductor substrate than a high-side switch, and a low-side driver is arranged in a region closer to the periphery of the semiconductor substrate than the low-side switch. By this means, a path from a positive terminal of an input capacitor to a negative terminal of the input capacitor via the high-side switch and the low-side switch is short, a path from a positive terminal of a drive capacitor to a negative terminal of the drive capacitor via the low-side driver is short, and a path from a positive terminal of a boot strap capacitor to a negative terminal of the boot strap capacitor via the high-side driver is short, and therefore, the parasitic inductance can be reduced, and the conversion efficiency can be improved.

Abstract: Disclosed is a switch driving circuit for controlling the switching operation of a switch. The switch driving circuit includes a driver generating a normal gate signal for controlling the switching operation of the switch, and a gate signal correction circuit comparing the normal gate signal with a gate signal applied to a gate electrode of the switch so as to correct the gate signal in accordance with the comparison.

Abstract: A digital switched current source is coupled to a programmable current source-driver and controlled by waveforms stored in the programmable and floating complementary sourcing and sinking current source-driver. A plurality of complementary P- and N-MOSFET is coupled to the programmable floating current source driver. The transformer-less programmable ultrasound transmit beamformer integrated circuit is provided and directly coupled to the plurality of transducers.

Abstract: A multi-level transmitter circuit with substantially constant output impedance has a capacitive transducer connected between a voltage input and ground. A first voltage path connects the voltage input to a first positive voltage source. The first voltage path is controlled by a first control signal. A second voltage path connects the voltage input to a second positive voltage source, less than the first positive voltage source. The second voltage path passes through a diode and is controlled by a second control signal. A third voltage path connects the voltage input to a third voltage source, less than ground, and is controlled by the second control signal. The impedance at the voltage input during the first control signal is substantially the same as the impedance at the voltage input during the second control signal.

Abstract: According to an aspect of the embodiment, a driver outputs a driver current to a reception LSI, and a receiver included in the reception LSI receives an analog voltage signal corresponding to a value of the driver current as a receiver input. An A/D converter converts the voltage signal of the receiver input to a digital value, and transmits the digital value to a driver current controller in a transmission LSI. The driver current controller adjusts a number of PMOS driving stages in the driver or a number of NMOS driving stages in the driver, to make the digital value of the voltage signal of the receiver input belong to a predetermined range.

Abstract: An output driving device prevents an inflow of external current through an output terminal even when there is no power supply. The output driving device includes an output circuit that maintains an output terminal at a low impedance state by receiving a supply of power in an output drive operation and maintains the output terminal at a high impedance state by receiving the supply of power in a non-output drive operation and a leakage prevention unit coupled to the output terminal of the output circuit, the leakage prevention unit preventing a current inflow to the output circuit through the output terminal when the supply of power is not supplied to the output circuit.

Abstract: A semiconductor device with less power consumption and an electronic appliance using the same. The semiconductor device of the invention is supplied with a first potential from a high potential power source and a second potential from a low potential power source. Upon input of a first signal to an input node, an output node outputs a second signal. With the semiconductor device of the invention, a potential difference of the second signal can be controlled to be smaller than a potential difference between the first potential and the second potential, thereby power consumption required for charging/discharging wires can be reduced.

Abstract: A method for passive cancellation of substrate noise for a buck converter uses an on-chip capacitor to reduce the substrate noise. The capacitor achieves a close-magnitude noise with opposite phase for better noise cancellation effect in the substrate. The capacitor can be realized as a MOS capacitor, NMOS isolation ring n-well capacitor, n-well junction capacitor, isolated p-well junction capacitor, etc. The capacitor is easy to implement. Further, bond wire parasitic inductance in the buck converter is used to reduce substrate noise.

Abstract: A programmable input/output circuit includes a programmable output circuit configured to drive an output signal to an input/output pad at a plurality of voltages. The programmable input/output circuit further includes a programmable input configured to detect an input signal from the input/output pad at a plurality of voltages. The voltage levels of the input and output circuits may be independently and dynamically controllable.

Abstract: A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.

Abstract: A buffer circuit includes a current source circuit, first and second switch circuits that are coupled to the current source circuit, a first resistor coupled to the first switch circuit, a second resistor coupled to the second switch circuit, and a third switch circuit coupled to the first and the second resistors. The third switch circuit couples the first and the second resistors to a node at a first voltage when the buffer circuit is configured to function in a current mode logic buffer mode. The third switch circuit couples the first and the second resistors to a node at a second voltage when the buffer circuit is configured to function in an H-bridge buffer mode.

Abstract: An embodiment of a discharge circuit comprises an output circuit with one output connected to an electrical load to absorb a discharge current given by the load when a logic signal commands a discharge of the load. The discharge circuit also comprises a control circuit to give the output circuit an appropriate control signal so that a slope of an output potential of the output circuit diminishes gradually when the logic signal commands a discharge of the load. Limiting the slope of the output potential gradually (and not suddenly) may limit the electromagnetic radiation generated by these variations.

Abstract: An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.