Abstract: An automatic adjustment circuit for an oscillator converts an output from a register into an analog signal by means of a D/A converter. An oscillation frequency of an oscillator is controlled by an output of the D/A converter. A first counter for counting an oscillation signal of the oscillator 1 resets itself and generates a pulse when a count reaches a predetermined value. A second counter counts a reference frequency pulse having a frequency substantially higher than the oscillation frequency of the oscillator. The second counter, on completion of counting a given preset value, changes an output level. The second counter is preset by said first counter when the first counter resets itself. Outputs from the first and the second counters are processed by an AND operation in an AND circuit. A third counter counts an output from the AND circuit, and provides a count output to the register.

Abstract: A clock deskewing apparatus uses either a series terminated single transmission line system or a Thevenin terminated dual transmission line system to deliver a clock signal to a load. A plurality of series terminated clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads coupled to the clock signal simultaneously. Each series clock deskewing apparatus has a single termination resistor with the same impedance value as the transmission line that it is coupled to. Each Thevenin termination system has a voltage divider resistor network. A variable delay line within each series clock deskewing apparatus can be adjusted so that each load receives the clock signal at the same time. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing system in order that the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances.

Abstract: The invention relates to a method and an arrangement for controlling a loop filter of a digital phase lock, the loop filter filtering a difference signal, which comes from a phase comparator at a predetermined bandwidth and is proportional to a phase error. To reduce oscillation in the adjusting method and to eliminate the errors caused by noise, the loop filter is adjusted non-linearly on the basis of the difference signal from the phase comparator in such a manner that the bandwidth of the loop filter changes.

Abstract: A circuit, indicating the first or last signal activated among n signals, includes flip-flops respectively associated with pairs of signals, a first signal of each pair being applied to a reset input of a flip-flop and a second signal of each pair being applied to a set input. Logic gates are respectively associated with each considered signal and are connected to indicate whether the considered signal is the first or the last activated signal when the flip-flops associated with all the pairs of signals including the considered signal are at respective suitable states once the first or last signal is activated.

Abstract: A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively to an incoming basic clock signal. A plurality of storage elements store therein a predetermined level in response to transitions occurring in associated ones of the basic and delayed clock signals after an asynchronous trigger signal is applied thereto. A clock selection logic circuit is controlled by the output signal from the storage elements for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of the clock signals based on the result of the detection, as a synchronized clock input signal.

Abstract: A numerically controlled oscillator that outputs a complex exponential value (sine and cosine). The numerically controlled oscillator inputs a scalar phase increment and uses the scalar phase increment to approximate a complex exponential phasor increment. A complex multiplier multiplies the exponential increment by an exponential value previously output from the oscillator to yield a multiplication result. A recursive amplitude normalizer, connected to the complex multiplier, normalizes the multiplication result to yield the complex exponential value.

Abstract: A multiplexer includes 2.sup.q+1 inputs receiving periodic signals, each signal being out of phase with respect to the other signals, and is controlled so as to switch from a present input signal to a next input signal by activation of a switch signal. The next signal has its phase delayed with respect to the present signal by 360.degree./2.sup.q+1. The switching signal is synchronized with an edge of the next input signal.

Abstract: A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively relative to an incoming basic clock signal. Storage means includes a plurality of storage elements storing therein a predetermined level in response to transitions occurring in associated ones of said basic and delayed clock signals after a trigger signal which is asynchronous with the basic clock signal is applied thereto. A clock selection logic circuit is controlled by the output signal of the storage means for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of said clock signals, based on the result of the detection, as a synchronized clock signal output.

Abstract: A vertical ramp generator includes a voltage controllable charge current source and a switched discharge current source coupled across a ramp capacitor. A pair of comparators coupled to first and second reference potentials are supplied with the ramp capacitor voltage and drive a flip/flop, the output of which operates the discharge current source. A sync signal voltage is injected into the output of one of the comparators. Another comparator compares the ramp capacitor voltage with a third reference potential corresponding to the midpoint of the desired ramp voltage to control the switching of a pair of current sources that supply a square wave current to a correction capacitor which develops a DC correction voltage. The duty cycle of the square wave current is a function of the deviation of the ramp capacitor voltage from the third reference potential. The correction voltage controls the amount of current supplied by the charge current source.