Abstract: Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A common delay is removed from the phase measurement values to form normalized correction values. Target phase values and clock select values are selected using the normalized correction values. And, clock signals to independent ASIC modules are adjusted based on the target phase values and clock select values.

Abstract: A local timer includes a dividing counter which counts a first clock and outputs a reference counting signal divided from the first clock; a timing synchronizing timer which counts a timing synchronizing timer value in synchronization with a reference timer responsive to the reference counting signal; a first buffer which stores a counted value of the dividing counter in synchronization with a second clock, when operation is by the first clock; a second buffer which stores the timing synchronizing timer value in synchronization with the second clock, when operation is by the first clock; a first adder which adds a first or second offset value to the stored value in the first buffer in synchronization with the second clock, when the first clock is suspended; and a second adder which adds a set value to the timing synchronizing timer value responsive to a carry from the first adder.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: A delay locked loop (DLL) circuit comprising: a fundamental phase comparator for detecting a fundamental phase difference of two input signals; a delay circuit; a delay control circuit for adjusting a delay time of the delay circuit in response to an output signal of the fundamental phase comparator; and at least one further phase comparator for detecting a phase difference other than the fundamental phase difference such that an amount of change of the delay time is changed in accordance with the fundamental phase difference.

Abstract: A calibration apparatus is provided for adjusting the relative phase between two signals received at a memory chip, the two signals being generated such that they are synchronized with one another in a controller and are transmitted to the memory chip via separate lines. The calibration apparatus comprises a measuring device, which is arranged in the memory chip and is designed for measuring the relative phase between the two received signals, and a feedback loop containing a phase-controlling correction device. The measuring device is designed for generating an item of control information indicating the deviation of the measured relative phase from a defined tolerance range. The correction device responds to the control information to compensate for the deviation. The correction device is arranged in the controller and is designed for influencing the relative phase between the two signals to be transmitted to the memory chip.

Abstract: The present invention provides for a divider circuit for reducing anomalous output timing pulses. A latch is coupled to the division selection line. A comparator is coupled to the division selection line. A first synchronizer coupled to the output of the latch. A frequency divider is coupled to the output of the synchronizer. A second synchronizer is coupled to the output of the comparator and the output of the frequency divider. There is feedback between the output of the second synchronizer and the enable input of the latch, the reset of the first synchronizer, the reset of the second synchronized, and the reset of the divide by n divider.

Abstract: A system and method for reducing timing uncertainties in a serial data signal. A system may comprise a transmitter configured to transmit serial data to a receiver through a transmission medium. The receiver may comprise a retiming mechanism configured to sample the serial data using a particular phase of a clock at a point in time when the serial data signal may not be likely to experience jitter. The retiming mechanism may comprise a plurality of first units, e.g., flip-flops, where each of the first units is configured to sample the serial data using a particular phase of the clock. Each of the first units may be connected to a particular second unit, e.g., transmission gate. Each of the second units may be configured to output the value of the serial data sampled by the associated first unit upon activation. The data outputted may subsequently become part of the retimed data.

Abstract: An integrated circuit is provided, which includes a phase-locked loop (PLL) that is fabricated on the integrated circuit and has a selectable loop filter capacitance and a selectable output frequency range.

Abstract: A flash memory device includes a charge pump having a capacity that is preset to a particular value. The flash memory device includes a measuring circuit to measure the actual capacity of the charge pump and to reset the capacity of the charge pump to a value based on the measured capacity.

Abstract: The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a counting value, and means for applying the first clock signal and a first counting value to the first counting circuit, so as to produce a first time base signal. According to the present invention, the integrated circuit comprises means for producing a second time base signal using the second clock signal and a second counting value, and means for calibrating the second counting value such that it is equal or proportional to the number of periods of the second clock signal occurring during a determined time interval equal to a period or to a whole number of periods of the first time base signal. Application particularly to the management of a timer in a microprocessor.

Abstract: A buffer device includes a plurality of latch stages which each have a latch device and a multiplexer. At least the multiplexer of the first latch stage on the output side is associated with a feedback loop of the latch device of this latch stage. The feedback loop is provided for data buffering. The buffer device keeps a data output on an output line stable.

Abstract: A digital PLL (phase locked loop) circuit includes a sampling circuit, a plurality of internal circuits and an output switching circuit. The sampling circuit samples a burst data signal in response to a multi-phase clock signal to produce N (N is a positive integer larger than one) sampled data signals. The multi-phase clock signal includes N clock signals, each of which has substantially the same frequency as the data signal and which have phases different by a predetermined component from one after another. Each of the plurality of internal circuits is selected in response to a first selection signal, and outputs a set of a selected one of the N clock signals and an identified data signal from the N sampled data signals, which corresponds to the selected clock signal, in response to the selected clock signal, when the internal circuit is selected.

Abstract: Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A common delay is removed from the phase measurement values to form normalized correction values. Target phase values and clock select values are selected using the normalized correction values. And, clock signals to independent ASIC modules are adjusted based on the target phase values and clock select values.

Abstract: There is disclosed a phase locked loop circuit comprising a phase frequency comparator configured to output an up/down signal indicating a phase difference and a frequency difference between a reference signal and a frequency divided signal, a charge pump configured to output a current signal in accordance with said up/down signal, an oscillator configured to output an oscillation signal of a frequency in accordance with said current signal, frequency dividing parts configured to divide the frequency of said oscillation signal and generating said frequency divided signal, phase frequency judging parts configured to judge whether or not the phase difference and the frequency difference between said reference signal and said frequency divided signal exceed a predetermined reference value, and changeover parts configured to switch a value of a current flowing through said charge pump depending upon whether or not the phase difference and the frequency difference between said reference signal and said frequency d

Abstract: A synchronizer circuit manages signals in different clock domains by generating clock pulses synchronized with a system clock. The clock pulses are generated at a rate proportional to the frequency of a clock operating in a first clock domain. Digital circuitry is then driven at the frequency of the first clock and in the time domain of the system clock. A hand-shaking protocol prevents the synchronizer circuit from going into a metastable condition when passing clock or data signals into different time domains. A programmable digital filter includes multiple sampling stages that sample an input signal. A detection circuit has inputs coupled to the outputs of the multiple sampling stages and changes the logic state of an output signal when no glitches are detected in the samples of the input signal. A control circuit selectively varies a time period used by the filter for sampling the input signal.

Abstract: A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.

Abstract: A synchronous circuit according to an embodiment of the present invention, comprising: a clock selector configured to select a suitable phase clock signal from a plurality of clock signals differing in phase from each other in accordance with a clock-selecting signal; a phase comparator configured to compare a phase of input data with that of the selected clock signal; a phase control circuit configured to generate a phase control signal in accordance with the comparison result obtained by the phase comparator and to generate the clock-selecting signal in accordance with a offset control signal; and a frequency offset control circuit configured to generate the offset control signal in accordance with the phase control signal.

Abstract: A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset signal which holds all configuration registers in a reset condition until the frequency multiplier achieves a locked state. The configuration registers are dependent upon the internal clock signal generated by the frequency multiplier for proper operation. By causing the configuration registers to renew operation only after the stable frequency multiplier operation the danger of corrupting the information in the configuration registers is minimized.

Abstract: A frequency synthesizer that includes an output oscillator, a difference circuit, a reference circuit, a feedback circuit and a comparator. The output oscillator generates an output signal whose frequency, FOUT, is determined by an oscillator input signal. The difference circuit generates a sampled signal having a frequency, Fsif=FOUT−FOFFSET. The reference circuit generates a reference signal having a frequency Fref. The reference circuit includes a reference oscillator for generating a high frequency reference oscillator output signal having a frequency F1 and a first division circuit for generating a signal having a frequency equal to F1 divided by R. The feedback circuit generates a feedback signal having a frequency, Ffb. The feedback signal generating circuit includes a second division circuit having a division factor chosen such that Fsif/Ffb is minimized. The comparator compares the reference signal and the feedback signal and generates the oscillator input signal.

Abstract: A freezer (106) is provided with a connector (120) and connected to a semiconductor equipment (10). The connector (120) may include a connector for power supply (120a), a connector for data communication (120b) and a connector for analog signal (120c). Therefore, the semiconductor equipment (10) can transmit data and signal to the outside while being cooled in the freezer (106). With this constitution, a semiconductor equipment housed in a cooling system for high-speed operation and a refrigerator for cooling the semiconductor equipment are provided.

Abstract: Insertion delay associated with receiving and distributing a clock within an IC is removed using a DLL. The structure of a differential receiver in the feedback circuit of the DLL is substantially matched to the structure of an input differential receiver which receives and inputs a differential input clock into the DLL. In this manner, the insertion delay associated with the input differential receiver is removed from a delay-corrected clock output from the DLL. By substantially matching one or more aspects of the feedback circuit to one or more aspects of a clock distribution circuit for distributing the delay-corrected clock, the insertion delay associated with the clock distribution circuit can also be removed from the delay-corrected clock.

Abstract: A synchronous quad clock domain system synchronizes an external primary and secondary clock (130, 132) with an internal primary and secondary clock (134, 136). The rising edge of the internal primary and secondary clock signals are matched and a synchronous multiple ratio is applied to the internal primary clock signal to produce the internal secondary clock signal. The phase of the internal and external secondary clock signals are matched. The external secondary clock signal is sampled to produce a external sample signature and the external sample signature is matched to a pattern corresponding to the synchronous multiple ratio to produce an external clock cycle signal. The internal secondary clock signal is also sampled to produce an internal clock cycle signal. The internal and external clock cycle signals are compared and a phase adjust signal is provided to match the phase of the internal and external secondary clock signals.

Abstract: A semiconductor memory device for implementing high speed operation of a delay locked loop (DLL) generates internal clock signals synchronized with external clock signals. The semiconductor memory device includes a first input clock buffer for receiving a pair of external clock signals to generate a reference clock signal and a DLL which receives the reference clock signal and a feedback reference clock signal. The respective phases of the reference clock signal and the feedback reference clock signal are compared, and a pair of internal clock signals are generated. The semiconductor memory device further includes a first feedback clock buffer which receives the pair of internal signals and generates a first feedback clock signal; a second feedback clock buffer which receives the pair of internal signals and generates a second feedback clock signal, and a second input clock buffer which receives the first and second feedback clock signals and generates the feedback reference clock signal.

Abstract: An apparatus and method in an integrated circuit for detecting phase differences between clock signals originating from an oscillator circuit. The oscillator circuit is formed on a substrate, such that the oscillator circuit is coupled to coincidence elements responsive to clock signals originating from the oscillator circuit. In addition, a coincidence circuit is provided that includes the coincidence elements, such that the coincidence circuit provides output signals only in response to a change in all clock signals originating from the oscillator circuit. The apparatus includes a delay circuit responsive to the output signals, such that the delay circuit stretches delays between the clock signals. A phase detector is coupled to the delay circuit, such that the phase detector is responsible for detecting phase differences between the clock signals by identifying the delays.

Abstract: On the basis of a reception clock, a transmission clock and a self-running clock having higher frequency than that of the reception clock, the phases of the reception clock and the transmission clock are compared. The phase of the transmission clock is controlled on the basis of the phase comparison circuit for outputting the controlled transmission clock and a frequency division clock of the self-running clock.

Abstract: A semiconductor device for inputting/outputting data in synchronism with a reference clock signal and an internal clock signal in each circuit. In this device, a variably delay section 104 delays a generated clock signal to output an internal clock signal, and a phase error-detecting section 107 detects a time difference between the internal clock signal and the reference clock signal, thereby controlling the delay amount of the variable delay section 104 to make the time difference substantially zero.

Abstract: A method and apparatus for negotiating access to a shared resource by two independent domains. A request register is provided to each domain for receiving an ownership request signal. Request signals received from both domains are clock-synchronized and fed to a cross-coupled circuit. The cross-coupled circuit includes two blocks, each having a switch and a register for receiving a request signal. The registers are responsive to different portions of a clock cycle, e.g., rising and falling edges. The switch in each block receives a signal from one domain on one input and a signal from the output of the register in the same block on the other input. The switch of one block is controlled by the output signal of the register of the other block. The output of one of the blocks is used to control a domain switch to permit data streams from the independent domains to reach the shared resource. Each domain requests use of the shared resource by sending a request signal to its respective request register.

Abstract: An apparatus comprising a memory section and a first circuit. The memory section may be configured to present a first output in response to (i) a first clock signal, (ii) a second clock signal, (iii) an input pulse and (iv) the first output. The first circuit may be configured to generate a second output in response to (i) the first output and (ii) the second clock signal, where the second output may comprise a pulse having a width equal to a period of the second clock signal. In one example, an input circuit may be configured to present the first output to the memory section in response to the input pulse and a first feedback of the output.

Abstract: A frequency-providing circuit is disclosed for providing an output signal at a frequency fout. The circuit comprises a frequency-generating unit, a frequency-changing circuit, and a synchronizing circuit. The frequency-generating unit receives a frequency-selecting control signal and provides a frequency output at a frequency fosc, whereby the frequency-generating unit is switchable between different frequencies substantially without a settling time. The frequency-changing circuit receives the frequency output and a frequency-changing control signal and derives the output signal therefrom, whereby the frequency fout of the output signal can be changed, with respect to the frequency fosc, in accordance with the setting of the frequency-changing control signal. The synchronizing circuit synchronizes the frequency-selecting control signal and the frequency-changing control signal.

Abstract: A synchronizer circuit manages signals in different clock domains by generating clock pulses synchronized with a system clock. The clock pulses are generated at a rate proportional to the frequency of a clock operating in a first clock domain. Digital circuitry is then driven at the frequency of the first clock and in the time domain of the system clock. A hand-shaking protocol prevents the synchronizer circuit from going into a metastable condition when passing clock or data signals into different time domains. A programmable digital filter includes multiple sampling stages that sample an input signal. A detection circuit has inputs coupled to the outputs of the multiple sampling stages and changes the logic state of an output signal when no glitches are detected in the samples of the input signal. A control circuit selectively varies a time period used by the filter for sampling the input signal.

Abstract: A conversion (20, 120, 220) system for converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) in a communications system (10), the conversion system (20, 120, 220) including an oversampled analog-to-digital converter modulator (24, 124, 224) for receiving an oversampling-clock signal (29, 129, 229) and a transmitted analog signal (18, 118, 218), the oversampled analog-to-digital converter modulator (24, 124, 224) operable to sample the analog signal (18, 118, 218) and to convert the analog signal (18, 118, 218) to a first digital signal (32, 132, 232), a time adjustor (41, 141, 241) coupled to the oversampled analog-to-digital converter modulator (24, 124, 224) for receiving the first digital signal (32, 132, 232) and a first adjustment signal (48, 148, 248), and for producing an output digital signal (54, 154, 254), and a digital signal processor unit (56, 156, 256) coupled to the time adjustor (41, 141, 241) for receiving the output digital signal (54, 154, 254) and performing timing

Abstract: Apparatus for producing an oscillating signal in a predetermined phase relationship with an input signal which generates its output signal by mixing in variable proportions two or more reference oscillating signals. Preferably the reference signals should be in quadrature relationship and have approximately the same frequency as the desired output, but this is not essential. The output signal may be desired to be in phase with the input signal or to have a predetermined phase offset. In a further aspect, apparatus is described which generates quadrature related clock signals, which may be used as the reference signals in the phase-lock arrangement.

Abstract: 052450152 A power noise preventing circuit for a microcontroller unit (MCU) is provided that prevents an erroneous operation of the MCU caused by power supply noise. The power noise preventing circuit for the MCU can include a power fail detecting circuit that controls a power fail signal by comparing supplied power to a preset fail voltage of a MCU and a system clock generating circuit that receives a clock signal and generates a first system clock signal that determines a state of a system. A clock freezing and synchronizing circuit fixedly outputs a second system clock signal at a state of the first system clock signal when the power falls below the preset fail voltage and the power fail signal is enabled. The clock freezing and synchronizing circuit further outputs the second system clock signal synchronized with the first system clock signal when the power fail signal is disabled.

Abstract: The present invention provides an technique for compensating a operation speed variation based on a principle that a circuit operation speed is adjusted by reflecting a delay time of an internal circuit itself that is an object of the operation speed fluctuation compensation.An internal circuit (1 in FIG. 1) has a critical path with an output terminal pair that outputs the identical logical values till its each operation is finished, and data in a complementary signal format as soon as its each operation is finished. A logical gate (2 in FIG. 1) can detect its operation end by sensing the signal transition into a complementary signal format at the output terminal pair of the internal circuit.

Abstract: The inventive mechanism is included with each module in a chain of modules. The inventive mechanism includes a clock mechanism which is edge synchronous among all of the clock mechanisms in the other modules, meaning that each clock has the same frequency and zero phase delay with respect to the clocks of the other modules. The clock mechanism of the first module of the chain is the master, the subsequent clocks are slaves. The inventive mechanism includes a trigger mechanism which allows each module of the chain to initiate a trigger event. The trigger mechanism is tied to the clock mechanism, so that the trigger signal is sent out on the next rising edge of the clock. Since each module is tied to the same clock frequency and has zero delay, when one module sends out a trigger, the remaining modules will detect the trigger on the next clock cycle, and the trigger event will begin simultaneously in all modules.

Abstract: A phase-locked loop circuit is constituted in such a manner that a delayed signal created by causing an input signal to loop through a delay stage a plurality of times is compared in terms of phase with the input signal, and an amount of delay in the delay stage is controlled in accordance with the comparison result of the delayed signal and the input signal. Therefore, the circuit size can be reduced with a reduced number of delay units constituting the delay stage.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: A method and apparatus are provided for synchronizing communications between different integrated circuits having different individual clock rates. In accordance with exemplary embodiments of the invention, a common clock signal is provided having a frequency greater than or equal to the highest individual clock rate, and the common clock signal is divided to obtain individual clock signals for the different integrated circuits For each integrated circuit an arrangement including a switching device and an edge-triggered storage member is also provided. The arrangement has an input for receiving signals, for example from the other integrated circuits. The arrangement also has an output connected to an input of the integrated circuit. The common clock signal and the individual clock signal corresponding to the integrated circuit are provided to the arrangement.

Abstract: A semiconductor device for inputting/outputting data in synchronism with a reference clock signal and an internal clock signal in each circuit. In this device, a variably delay section delays a generated clock signal to output an internal clock signal, and a phase error-detecting section detects a time difference between the internal clock signal and the reference clock signal, thereby controlling the delay amount of the variable delay section to make the time difference substantially zero.

Abstract: Waves such as radio-waves, sound waves, or electric current waves are used for communication among system units. Each system unit includes a reference oscillation generation apparatus which receives as input a sum of a sent wave and a received wave. An upper limit and a lower limit for input amplitude range is set in said reference oscillation generation apparatus. The apparatus modulates the output (sent wave) so as to meet the input amplitude range so that synchronization among a large number of distributed reference oscillation generation systems is attained. As a result, it becomes possible to eliminate phase differences among reference oscillation systems added to a large number of distributed system units and attain synchronization.

Abstract: A method and apparatus for controlling frequency synchronization in a frequency correction feedback loop of a radio telephone. A processor in a frequency update controller ascertains increment/decrement values pro-proportionally related to confidence levels representing a ratio that a likelihood probability of estimated offset frequecies of an input carrier signal are accurate in proportion to a likelihood probability that the estimated offset frequencies are inaccurate. The processor adds or subtracts the value to a counter depending on its sign. When the counter reaches a certain predefined positive number, the counter is decremented by this number and the processor increases the frequency of a reference oscillator frequency. When the counter reaches a certain predefined negative number, the counter is incremented by the absolute value of the negative number and the processor decreases the frequency of the reference oscillator frequency.

Abstract: A system is provided for generating an accurate and stable output clock signal of a desired output frequency in response to a system clock signal having a system clock period. The system uses an accurate and stable reference clock signal. The system comprises a measuring circuit and a ratio counter. The measuring circuit receives and processes the system clock signal and produces a measurement, referred to as the system clock measurement, that is indicative of the system clock period. The ratio counter receives the system clock signal and the system clock measurement and generates the output clock signal. The system is resistant to noise in the output clock signal caused by asynchronicity between the system clock signal and the reference clock signal. The system is resistant because it employs at least one of a lock-on unit and a synchronizing controller in operating the clock measuring circuit.

Abstract: A design method for an asynchronous sequential circuit that employs synchronous design techniques wherein a synchronous sequential circuit is designed to perform a desired function. A terminating state for the synchronous sequential circuit is then defined wherein the terminating state occurs before a transition to an idle state in the synchronous sequential circuit. A circuit is provided for latching at least one asynchronous input for the asynchronous sequential circuit and a circuit is provided for generating a synchronous clock that drives the synchronous sequential circuit such that the synchronous clock is enabled by a latched asynchronous input and is disabled by the terminating state of the synchronous sequential circuit.

Abstract: The invention seeks to provide an improved method and apparatus for detecting thresholding errors in a digital signal recovered from a transmitted signal, wherein a derived threshold error signal varies linearly with the threshold error. Extraction of a threshold error signal linearly related to the actual threshold error enables increased speed of reaction of a threshold control circuit.

Abstract: A variable delay circuit is disclosed comprising first and second clock delay sections, first and second phase comparison circuits, first and second data delay sections, and a selector. The first and second clock delay sections delay a clock signal to generate first and second delayed clock signals. The first and second phase comparison circuits respectively detect a phase difference between the clock signal and the first delayed clock signal and a phase difference between the clock signal and the second delayed clock signal. The first and second phase comparison circuits then respectively supply first and second delay control signals indicating the phase differences to the first and second clock delay sections so as to equalize the delay times of the clock delay sections to a period of the clock signal. The first and second data delay circuits delay a data signal.

Abstract: A semiconductor integrated circuit device has an internal circuit node reset signal generation circuit for inverting an output signal with a predetermined time lag immediately after application of power. The internal circuit node reset generation circuit comprises an initial stage power on reset signal generation circuit, an initial stage signal transmission circuit for inputting a signal outputted by the initial stage power on reset signal generation circuit, a final stage power on reset signal generation circuit for inputting a signal outputted by the initial stage signal transmission circuit, and a final stage signal transmission circuit for inputting a signal outputted by the power on reset signal and outputting the output signal.

Abstract: A method and system for synchronizing to an incoming Hsync signal, and for generating a phase locked clock signal in response thereto. The Hsync signal and an incoming clock are coupled to a sequence of modules. Each module includes a latch for sampling the incoming clock on a transition of the Hsync signal, whose output is combined (using an XOR gate) with the Hsync signal. Each module includes a time delay for generating a delayed clock signal, incrementally delayed from the previous module in the sequence, so that the clock signal for each module is phase-offset from all other modules. The latch outputs are summed using a resistor network, to produce a triangle-shaped waveform which is phase locked to the Hsync signal and which is frequency locked to the incoming clock. The triangle-shaped waveform is compared with a constant voltage to produce a square wave.

Abstract: A series clock deskewing apparatus uses a series terminated single transmission line system to deliver a clock signal to a load. A plurality of series clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads simultaneously. Each series clock deskewing apparatus has a single series termination resistor with the same impedance value as the transmission line to which it is coupled. For each load, the clock signal travels the transmission line from a clock generator to the load and is simultaneously applied to the deskewing apparatus. A clock signal is reflected at the load back to the deskewing apparatus. The roundtrip transit time is determined by the deskewing apparatus which causes an appropriate delay to adjust each clock signal to arrive synchronously at all the loads.

Abstract: A circuit for generating a low power CPU clock signal is disclosed. The circuit includes a multi-frequency oscillator having a plurality of output signals of various frequencies that are input to a signal selector. The signal selector is controlled to route one of the various frequency signals to the output, which provides the CPU clock oscillating signal. The frequency of the CPU clock signal is compared against a reference oscillatory signal that is generated by a reference oscillator. Based upon the comparison, the frequency comparator generates an output signal that is used to control the signal selector to select an input signal of either higher or lower frequency, depending upon the comparison. Finally, an enable signal is provided for selectively enabling the operation of the CPU clock oscillating circuit.

Abstract: A numerical voltage controlled oscillator comprising an integrator for generating an estimated sine waveform and an estimated cosine waveform from a variable control signal; a normalizer, connected to the integrator, for generating a normalization factor from the estimated sine waveform and the estimated cosine waveform; and a multiplier, connected to the normalizer, for multiplying the normalization factor with the estimated sine waveform and the estimated cosine waveform. The multiplication of the estimated sine waveform and the normalization factor produces the sine waveform and the multiplication of the estimated cosine waveform and the normalization factor produces the cosine waveform. The frequency and phase of the sine and cosine waveforms vary with changes in amplitude of the variable control signal.