Abstract: A high sensitivity microphone may include a sound detecting module including a vibration film and a fixed film, a power source circuit supplying a power source to the sound detecting module through a switch control of a first switch applying a first bias and a second switch applying a second bias, a detecting circuit removing a noise included in a first capacitance signal and a second capacitance signal that are differential input from the sound detecting module, according to a switch control of a third switch inputting the first capacitance signal in conjunction with the first switch and a fourth switch inputting the second capacitance signal in conjunction with the second switch, and a switch controller performing a first switch mode linking the first switch and the third switch and a second switch mode linking the second switch and the fourth switch for differential input and output of the microphone.

Abstract: A low-side (LS) output pre-driver has a short-circuit-to-battery fault detection scheme for a MOSFET switch having a drain connection to a load connected to a battery voltage and a source connection tied to ground. The LS output pre-driver includes a comparator, a reference voltage selector, a multi-phase blank/filter, a multi-phase control timer. The first signal of the multi-phase control timer instructs the reference voltage selector to select which of the plurality of reference voltage signals is provided to the second input of the comparator. The second signal of the multi-phase control timer instructs the multi-phase blank/filter to change from one of the plurality of time intervals to another of the plurality of time intervals.

Abstract: The electronic device is arranged for generation of an audible alarm or music. It includes a coil or inductor and a buzzer provided with a capacitor connected in series with the coil. When the electronic device is actuated, the buzzer generates the audible alarm or music. The electronic device further includes, in a feedback loop, a derivative circuit connected to a connection node between the coil and the capacitor, to produce a derivative of the signal from the capacitor, and a comparator for comparing a derivative signal from the derivative circuit with a reference voltage. The comparator supplies an output signal to the coil to amplify the signal across the capacitor, so that the buzzer generates at least one audible alarm.

Abstract: A transceiver device may include a transmit path that generates a modulated transmit signal based on a baseband signal, and a receive path that receives a receive signal, which is subject to third-order order distortion caused by intermodulation noise resulting from a continuous wave blocker intermodulating with transmit leakage from the transmit path. The transceiver may also include a compensation path that models portions of the transmit path and the receive path, and generates a replica signal representative of the third-order order distortion according to at least a specified function and the modeled portions of the transmit path and the receive path. The compensation path also filters the replica signal and subtracts the filtered replica signal from the receive signal to eliminate the third-order order distortion caused by the intermodulation noise. The filtering of the replica signal may be performed by programmable finite impulse response filters.

Abstract: A flowmeter includes a process sensor assembly providing a sensor signal and a filter stage comprising a low pass filter and a high pass filter and providing a filtered signal from the sensor signal. A processor determines that a filtered signal is indicative of a low flow condition for a first fluid, alters at least one parameter of the low pass filter and at least one parameter of the high pass filter in response to the low flow condition such that the filter stage provides a new filtered signal, determines that the new filtered signal is not indicative of a low flow condition for a second fluid and generates an alarm in response to the new filtered signal not being indicative of a low flow condition for the second fluid.

Abstract: Methods, systems, and computer readable media for wideband frequency and bandwidth tunable filtering are disclosed. According to one aspect, the subject matter described herein includes a wideband frequency and bandwidth tunable filter that splits a filter input signal into first and second input signals, modifies the first input signal to produce a first output signal, modifies the second input signal to produce a second output signal having an intermediate frequency response, and combines the first and second output signals while adjusting their relative phases and/or amplitudes to produce a filter output signal with the target frequency response. Adjustment includes splitting the second input signal into third and fourth input signals, which are modified and then combined to produce the second output signal having the intermediate frequency response.

Abstract: A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell. A second tunable buffer cell is coupled to the first transmission line. A center frequency and bandwidth of the second tunable buffer cell is matched to a center frequency and bandwidth of the first tunable buffer cell to achieve low phase noise with low power. Additional transmission lines and tunable buffer cells can be cascaded in the tunable buffer circuit. Each tunable buffer cell has first and second transistors including first and second conduction terminals and control terminal coupled for receiving the input signal. An inductor and tunable capacitor are coupled between the first conduction terminals of the first and second transistor. A digital signal adjusts the tunable buffer cells in response to an RSSI which monitors the output for proper signal strength.

Abstract: A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal.

Abstract: Apparatus for implementing Adjustable Compensation Ratio (ACR) active shielding or control of physical fields (magnetic, electric, electromagnetic, acoustic, etc.), comprising the addition of a secondary internal feedback loop within a conventional primary closed feedback loop topology. Compensation-ratio transfer function order and coefficients adjustment permits accommodating frequency-dependent and frequency-independent effects within a Protected Volume when a system field sensor or sensor array is not at the exact location where external field interference must be optimally canceled. A Laplace polynomial term precisely sets this parameter in a supplementary feedback link by modeling the frequency-dependent characteristic of an Interacting Medium without deleterious effect on other desirable primary closed-loop characteristics. The inventive ACR can be used in advanced active cancellation for magnetic shielding purposes.

Abstract: A system that drives multiple MOSFETs in parallel for direct current and alternating current solid state power controller applications may include networks connected to the gates of the MOSFETs to protect the MOSFETs from being damaged during high current interruption. For direct current applications, the system may include a switching protection and damping network and a gate drive balancing network. For alternating current applications, the system may include two switching protection and damping networks and a gate drive balancing network.

Abstract: A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal.

Abstract: A low-pass filter circuit is described. The low-pass filter circuit includes a pseudo-resistor. The pseudo-resistor includes at least one metal-oxide-semiconductor field-effect transistor. The at least one metal-oxide-semiconductor field-effect transistor receives a digital power supply domain signal. The low-pass filter circuit also includes a capacitor. The capacitor is coupled to the pseudo-resistor. The capacitor provides a filtered signal. The low-pass filter circuit may pass digital signal transitions and provide low-pass filtering when there is no signal transition.

Abstract: The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.

Abstract: There are provided a noise filter circuit and an operating method thereof. A noise filter circuit includes a first delay circuit, and a second delay circuit connected to the first delay circuit in series, wherein the first delay circuit and the second delay circuit each include at least one inverter and at least one delay element for generating a predetermined delay, and the first delay circuit and the second delay circuit have different filtering characteristics.

Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.

Abstract: Provided is a pulse noise suppression circuit. The pulse noise suppression circuit includes a filter circuit converting an input signal of a pulse type into an increasing or decreasing filter signal, a level reset circuit resetting the filter signal in response to the input signal and an output signal and an output circuit converting the filter signal into the output signal of a pulse type, wherein the level reset circuit resets the filter signal to have a high level when the input signal and the output signal all have a high level, and resets the filter signal to have a low level when the input signal and the output signal all have a low level.

Abstract: A parallel amplifier, a switching supply, and a radio frequency (RF) notch filter are disclosed. The parallel amplifier has a parallel amplifier output, such that the switching supply is coupled to the parallel amplifier output. Further, the RF notch filter is coupled between the parallel amplifier output and a ground. The RF notch filter has a selectable notch frequency, which is based on an RF duplex frequency.

Abstract: A method of canceling impulsive interference from a communications signal is provided. The method includes identifying an impulse interference contained in the communications signal, generating a model of impulse interference, matching the model in at least one of amplitude, phase and envelope time delay to the identified impulse interference, and cancelling the identified impulse interference by subtracting the matched model from the identified impulse interference.

Abstract: The present invention relates to an electrical device for charging accumulator means (5), said electrical device comprising: a motor (6) connected to an external mains (11); an inverter (2) connected to the phases of said motor (6); and switching means (4) integrated into the inverter (2), said switching means (4) being configured to permit said motor (6) to be supplied and to permit the accumulator means (5) to be charged by the inverter (2). According to the invention, said electrical device further includes, for each phase of said motor (6), an RLC low-pass filter (18) connected, on the one hand, to the mid-point (16) of the phase of said motor (6) and, on the other hand, to ground.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×M+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: Various embodiments of the invention allow for active AC ripple noise cancellation. In certain embodiments, noise cancellation is accomplished by modulating an LED driver output in a polarity opposite to the ripple, thereby, preventing interference with ripple-sensitive loads. Certain embodiments take advantage of a filter network to prevent the LED driver from modulating LED current in response to ripple that falls within a visible frequency range so as to prevent flicker in an LED backlight display. In addition to protecting ripple-sensitive loads from large ripple currents, efficiency is increased by reducing both I2·R losses and peak currents, thereby, extending the useful battery life time in mobile devices.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.

Abstract: A Decision Feedback Equalizer (DFE) capable of preventing incremental increases of a jitter of a recovered clock and reduction of a voltage margin of decided data due to delay of feedback data. The DFE includes a combiner for combining received data with feedback data and outputting the combined data as equalization data, a decision circuit for deciding recovery data by receiving the equalization data, a feedback loop for supplying the recovery data to the combiner as feedback data and a clock recovery circuit for removing a delay data component from the equalization data through the feedback loop, recovering a clock with respect to the other equalization data except the delay data component and supplying the recovered clock for decision operation of the decision circuit.

Abstract: A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: An electronic device includes an optical module, a power source module powering the optical module, a processor, a controller, and a switch module. The processor generates and maintains a delay signal for a first predetermined time in response to determination that the power source module is powered on. The processor further generates a driving signal upon determination that the first predetermined time has elapsed. The controller generates and maintains a control signal for a second predetermined time in response to determination that the power source module is powered on. The switch module is turned on to establish an electrical connection between the power source module and the optical module according to the driving signal, and turned off to cut off the electrical connection according to the control signal.

Abstract: A communication device is provided. The communication device includes a circuit for reducing low-frequency interference, and the circuit for reducing low-frequency interference includes a low-frequency filter circuit and a capacitor. The low-frequency filter circuit includes a terminal and a terminal, in which the terminal is connected to a power supply, and the terminal is connected to a load; the capacitor includes a terminal and a terminal, in which the terminal is connected to the load, and the terminal is connected to the power. By setting the circuit for reducing low-frequency interference in a communication device, an input current of the communication device may be maintained stable, as a result, low-frequency interference of the communication device to other communication devices is reduced.

Abstract: A method for processing a signal with a corresponding noise profile includes analyzing spectral content of the noise profile, filtering at least one noise harmonic within the signal based on the analyzed spectral content, and limiting the filtered signal. The noise profile may include a phase noise profile. The signal may include a sinusoidal signal and/or a noise signal. At least one filter coefficient that is used to filter the at least one noise harmonic may be determined. The filtering may include low pass filtering. The limiting may include hard-limiting of the filtered signal. A phase difference between the limited signal and a reference signal may be detected.

Abstract: This invention is a clamp circuit for a video input. The clamp circuit includes: a coupling capacitor; a differential amplifier comparing a video input to predetermined reference voltage; a clamp transistor having a gate connected to the output terminal of the differential amplifier and a source-drain path connected between a power supply voltage and a second terminal; a resistive element connecting the second terminal of the clamp transistor and the coupling capacitor; a first current sink carrying a first predetermined current from the coupling capacitor to ground; and a second current sink carrying a second predetermined current from the second terminal of the said clamp transistor to ground. The resistive element can be a transistor, a resistor, a diode or a switch.

Abstract: A signal conditioning system includes a first filter, a signal processing module connected with the first filter, a second filter connected with the signal processing module, and a ?-? modulator connected with the second filter. The signal processing module makes the saturation overflow treatment to the signal output by the first filter using the characteristics of the radix complement adder. The ?-? modulator is a high order filter formed by a plurality of cascaded and inter-stage feedback second-order filters. Based on the performance of the ?-? modulator and the whole system, the stability of the signal conditioning system is improved.

Abstract: In a semiconductor device, a monitoring circuit monitors and detects a quantity of noise in the semiconductor device. A control circuit has capacitances and controls connections to the capacitances such a decoupling capacitance value provided between a first power supply and a second power supply is dynamically adjusted based on the detected noise quantity.

Abstract: An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.

Abstract: Capacitive decoupling circuits and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip with a first power rail for a first no-load bias level and a ground rail. A first voltage divider is electrically coupled between the first power rail and the ground rail and has a midpoint node. A first pair of capacitors is electrically coupled between the first power rail, the midpoint node and the ground rail to provide capacitive decoupling for power delivered to the first power rail. A second power rail has a second no-load bias less than the first no-load bias. A second pair of capacitors is electrically coupled between the ground rail and the second power rail to provide capacitive decoupling for power delivered to the second power rail.

Abstract: A signal detector arranged in a receiver of a wireless communication device includes a variable passband bandpass filter configured to bandlimit a received signal using a variable passband; a signal parameter detection unit configured to detect a signal parameter of each of a plurality of signals contained in the received signal; a detection order determination unit configured to determine a detection order for detecting the signals from the received signal based on the signal parameter; a parameter control unit configured to control the passband of the variable passband bandpass filter based on the detection order and the signal parameter; and an equalization and decision unit configured to equalize and decide the bandlimited signal output from the variable passband bandpass filter. The signals contained in the received signal are successively detected from the received signal according to the detection order by means of the variable passband bandpass filter and the equalization and decision unit.

Abstract: An adaptive equalizer including an equalizer filter and a tap coefficients generator used to process a sample data stream derived from a plurality of received signals is disclosed. The tap coefficients generator includes an equalizer tap update unit, a vector norm square estimator, an active taps mask generator, a switch and a pilot amplitude reference unit used to minimize the dynamic range of the equalizer filter. A dynamic mask vector is used to mask active taps generated by the equalizer tap update unit when an unmasked signal output by the equalizer filter is selected by the switch to generate an error signal fed to the equalizer tap update unit. A fixed mask vector is used to mask active taps generated by the equalizer tap update unit when a masked signal output by the equalizer filter is used to generate the error signal.

Abstract: A loop filter in a phase lock loop circuit comprising a reference precision resistor, a first FET and a second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and to the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.

Abstract: An adaptive equalizer including an equalizer filter and a tap coefficients generator used to process a sample data stream derived from a plurality of received signals is disclosed. The tap coefficients generator includes an equalizer tap update unit, a vector norm square estimator, an active taps mask generator, a switch and a pilot amplitude reference unit used to minimize the dynamic range of the equalizer filter. A dynamic mask vector is used to mask active taps generated by the equalizer tap update unit when an unmasked signal output by the equalizer filter is selected by the switch to generate an error signal fed to the equalizer tap update unit. A fixed mask vector is used to mask active taps generated by the equalizer tap update unit when a masked signal output by the equalizer filter is used to generate the error signal.

Abstract: A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.

Abstract: A noise reduction circuit for AC power, AC power neutral lines, and DC power. In a first embodiment for use with AC power, the invention operates by subtracting the error voltage from an incoming AC signal boosted in voltage by a small boost transformer. In a second embodiment, the present invention reduces noise in AC power neutral lines by effectively operating as a power corrector and reduces unwanted noise on the neutral line at all frequencies without introducing unwanted current in the ground line. In a third embodiment, the invention reduces noise in DC power supplies.

Abstract: A circuit device has a passive network (101) with an input (109) and an output, the output of the passive network (101) forming an output terminal (103) of the circuit device and a feedback path coupling the output terminal (103) of the circuit device to the input (109) of the passive network (101), the feedback path having an amplifier (107) configured to adjust an attenuation of the circuit device.

Abstract: A transmission system for RF signals, power and control signals over RF coaxial cables is disclosed. A coaxial cable line interconnects two devices, such as an instrument and a remote coupler. A control signal (e.g., data bit) and RF signals are multiplexed onto the coaxial cable line using a bias network at each end of the coaxial cable. In certain embodiments, power is generated at the coupler based on the state of the control bits. Each coaxial cable carries one control bit on the center conductor of the cable. A table maps the states of the one or more control bits to the desired states in the remote coupler. The all-zeroes state for the control bits is disallowed, such that at any given time, at least one of the control lines is high (e.g., at +5V). A passive network at the coupler generates the power voltage for the coupler from the control bits. In further embodiments, a power supply filter is provided at the coupler to supply power to the coupler during transitions of the passive network.

Abstract: In one embodiment, an integrated circuit comprises resonance limiter circuits coupled to a power supply connection of the integrated circuit. The resonance limiter circuits are configured to detect oscillation on the power supply connection at a resonant frequency, and to dampen the resonant frequency oscillation responsive to detecting the oscillation. In some embodiments, the resonance limiter circuits may damp oscillation at or above the resonant frequency or approximately the resonant frequency (e.g. somewhat below the resonance frequency). The resonant frequency depends on a package of the integrated circuit. In an embodiment, a resonance limiter circuit comprises a filter and a transistor coupled in parallel with the filter between a power supply connection and a ground connection. The filter is tuned to approximately a resonant frequency (e.g. the lowest resonant frequency) that depends on a package corresponding to an integrated circuit into which the resonance limiter circuit is fabricated.

Abstract: The present invention provides a filter circuit which can eliminate single noise effectively and is relatively simple in circuit configuration. First and second absolute values of differences between one-clock-preceding output data and both of one-clock-preceding input data and two-clock-preceding input data are respectively calculated by subtracters. When the first absolute value<the second absolute value, a selector selects one-clock-preceding input data as the present output data. When the first absolute value?the second absolute value, the selector selects two-clock-preceding input data as the present output data.

Abstract: A noise reduction circuit for AC power, AC power neutral lines, and DC power. In a first embodiment for use with AC power, the invention operates by subtracting the error voltage from an incoming AC signal boosted in voltage by a small boost transformer. In a second embodiment, the present invention reduces noise in AC power neutral lines by effectively operating as a power corrector and reduces unwanted noise on the neutral line at all frequencies without introducing unwanted current in the ground line. In a third embodiment, the invention reduces noise in DC power supplies.

Abstract: A loop filter and a method for adjusting its compensating current to make a control voltage of the loop filter more stable. The loop filter includes a charge/discharge path for receiving a control current and constituted by a first resister and a capacitor, a second resistor connected to the first terminal of the first resistor, an OP amplifier having an output terminal connected to the second resistor, a first input terminal connected to the capacitor, and a second input terminal, and a compensating unit connected to the output and second terminals of the second resistor. The loop filter further comprises a current source to provide a compensating current to the compensating unit. The loop filter utilizes the compensating unit to compensate the offset between the two input terminals of the amplifier. Therefore, the loop current of the OP amplifier can be reduced or eliminated.

Abstract: There is described a semiconductor Type Two phased locked loop filter having a passive capacitor part and a variable active resistor part, the variable active resistor part being integrated with the passive capacitor part. Integrating an active variable resistor will apply the same change to both poles and has no effect on the loop gain. The variable active resistor part is controlled by a resistor regulator circuit operating from a voltage that follows the type two phased locked loop voltage. The resistor regulator circuit is bootstrapped to the phased locked loop voltage using a voltage follower configured op-amp.

Abstract: A method of canceling noise in analog circuits is described along with noise cancellation circuits. Analog circuits are sensitive to noise. Especially in mixed signal environments where digital circuits and analog circuits are combined, the noise generated by relatively noisy digital circuits often cause the analog circuits to produce incorrect output signals. Instead of shielding or separating the susceptible analog circuits from noisy digital circuits, additional circuitry is added where one of the added circuits, denoted as the noise separator circuit, produce only the noise component of the output signal, the first output, of the analog circuit adversely affected by the noise. Then, another circuit is used to subtract the noise from the first output, thereby producing a noise-free output signal. Alternatively, the noise separator circuit can be made to produce the inverse of the first output, including the inverse of the noise.

Abstract: A noise filter for an integrated circuit is proposed. The noise filter comprises a CMOS inverter and two capacitors. The input of the CMOS inverter is coupled with an input pad of the integrated circuit and the output of the CMOS inverter is coupled with an input buffer. The first capacitor is inserted between the output of the CMOS inverter and a first voltage source and the second capacitor is inserted between the output of the CMOS inverter and a second voltage source. A transfer gate may be in stead of the CMOS inverter.

Abstract: Provided is a device for controlling a frequency response by scaling an impedance. The device includes a filter and a duty ratio controller. The filter generates an output signal after removing a frequency from an input signal, and comprises a first impedance component and a switch. The switch, which is serially connected to the first impedance component, is switched on or off in response to a duty-controlled clock signal. The duty ratio controller receives a clock signal, controls a duty ratio of the clock signal, and generates the duty-controlled clock signal. The duty ratio controller comprises a flip-flop, which has a clock terminal that receives the clock signal, and a reset terminal, which receives a delayed signal obtained after delaying the clock signal by a time delay. The duty ratio controller further comprises a delay component that receives the clock signal, generates the delayed signal, and controls the time delay in response to a duty control signal.