Abstract: Methods and devices to control PCM switches are disclosed. The described devices include PCM switch drivers and logic and control circuits, all integrated with the PCM and the associated heater on the same chip. Various architectures for the driver are also presented, including architectures implement feedback mechanism to mitigate variations from process, temperature, and supply voltage.

Abstract: Systems, methods and apparatus for wireless charging are disclosed. An apparatus includes or operates as a wireless charging device that has a battery charging power source coupled to a charging circuit, a plurality of charging cells provided on a surface of the wireless charging device and a controller or processing circuit, which may include one or more processors. The apparatus has a high-pass filter configured to extract high-frequency components from a measurement signal representative of voltage at a transmitting coil during a charging operation, a first attenuator configured to attenuate the measurement signal and provide an attenuated measurement signal, a mixer configured to add a signal representative of the high-frequency components to the attenuated measurement signal to obtain a scaled measurement signal, and a demodulator configured to decode one or more messages associated with the charging operation from the scaled measurement signal.

Abstract: A touch circuit includes: a touch IC; a first pull-up sub-circuit; a second pull-up sub-circuit; a first switching sub-circuit configured to transmit a signal from a data signal input terminal to a data signal port under control of a signal from a first signal input terminal; and a second switching sub-circuit configured to transmit a signal from a clock signal input terminal to a clock signal port under control of the signal from the first signal input terminal. The signal from the data signal input terminal is transmitted to the first switching sub-circuit earlier than the signal from the first signal input terminal, and the signal from the clock signal input terminal is transmitted to the second switching sub-circuit earlier than the signal from the first signal input terminal.

Abstract: A device for detecting photons and charged particles includes a first photon-detecting panel, which causes a Compton scattering of incident radiation with charged particles, such that the wavelength thereof increases, losing part of their energy, generating a signal. A central charged particle-detecting panel, following the first photon-detecting panel on a side opposite that of the incident radiation, identifies charged particles generated in the first photon-detecting panel, generating a signal. A second photon-detecting panel, follows the central charged particle-detecting panel on a side opposite that of the first photon-detecting panel. Scattered photons and/or charged particles are generated in the first photon-detecting panel interact, generating a signal.

Abstract: In an embodiment, a device includes a switching power supply configured to have a first operating mode synchronized by a first clock signal generated by a clock generator a second asynchronous operating mode. The clock generator is configured such that the first clock signal becomes equal, upon transition from the second operating mode to the first operating mode, to the signal having the closest rising edge of a second clock signal and a third clock signal complementary to the second clock signal.

Abstract: A power supply includes a primary winding, a secondary winding, a switch, and a controller. The secondary winding is magnetically coupled to the primary winding. The switch is coupled to the secondary winding and controls a state of current through the secondary winding. The controller controls the state of the switch based on an integrator voltage derived from monitoring a voltage from the secondary winding. For example, the controller activates the switch to an ON state in response to detecting a condition in which the magnitude of the monitored voltage of the secondary winding crosses a threshold value such as a magnitude of an output voltage produced from the secondary winding.

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

Abstract: Systems and methods to augment audio output in an electric vehicle (EV) include obtaining inputs from one or more sensors. The inputs include information about the EV and about one or more persons outside the EV. A current scenario is defined based on the inputs. Whether the current scenario matches a predefined scenario among a set of predefined scenarios is determined, and augmented audio output is produced according to the predefined scenario.

Abstract: An electronic device comprising circuitry configured to drive a unit pixel for a time of flight camera according to a multi-level mixing clock scheme.

Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Abstract: The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.

Abstract: Embodiments of the present disclosure include techniques for calibrating analog-to-digital converters (ADCs), such as successive approximation register SAR ADCs. In one embodiment, a pattern is applied to the input of an ADC to produce digital output codes. Counts of the digital output codes are used detect errors and adjust a clock delay of a comparator in the ADC. In other embodiments, an ADC calibration circuit is coupled to a calibration algorithm executing on a remote server to calibrate one or more ADCs.

Abstract: Low noise charge pumps are disclosed. In certain embodiments, a charge pump includes a charge pump output terminal that provides a charge pump voltage, a switched capacitor, and a plurality of switches that charge the switched capacitor during a charging operation of the charge pump and that connect the switched capacitor to the charge pump output terminal during a discharging operation of the charge pump. The switches operate with non-overlap between the charging operation and the discharging operation so that the charge pump operates with low noise.

Abstract: A power splitter for use in an amplifier (e.g., a Doherty amplifier) includes an input terminal, and first and second output terminals. The input terminal is configured to receive an input RF signal, the first output terminal is configured to produce a first RF output signal, and the second output terminal is configured to produce a second RF output signal. The power splitter also includes a first capacitance electrically coupled between the input terminal and the first output terminal, a second capacitance electrically coupled between the input terminal and the second output terminal, a first inductance electrically coupled between the input terminal and a ground reference node, a second inductance electrically coupled between the first output terminal and the ground reference node, a third inductance electrically coupled between the second output terminal and the ground reference node, and a resistance electrically coupled between the first and second output terminals.

Abstract: Provided are embodiments for a circuit for a relay drive with a power supply economizer. The circuit includes a relay having a relay coil and a relay contact. The circuit also includes a power source to generate power for a coil drive voltage to operate the relay, and a controller configured to provide a command signal to operate the circuit in a plurality of modes. The circuit includes a first gate drive coupled to a first switch, wherein the first switch connects the relay coil to the circuit, and a second gate drive coupled to a second switch, wherein the second switch changes an effective resistance of a resistor network of the circuit to modify the coil drive voltage. Also provided are embodiments for a method for operating a circuit including relay drive with a power supply economizer.

Abstract: A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.

Abstract: Techniques regarding a DSFQ logic family are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a dynamic single flux quantum logic circuit that has a self-resetting internal state and can be powered by direct current. Further, the self-resetting internal state can be characterized by two time constants.

Abstract: A variable loss attenuator is provided. Two or more controllable stages each include a differential or single-ended ? network. Each ? network includes one or more series elements connected in series between the signal input and the signal output. Each series element includes a series transistor, which may potentially be provided without an inductor in parallel. Each ? network includes a plurality of shunt elements each including at least one respective shunt transistor. An input stage connects to the first controllable stage and an output stage connects from the last controllable stage. Intermediate stages connect the controllable stages to one another. Each of the input stage, output stage, and intermediate stages include a right-handed transmission line component and coupled between the signal input and a first one of the controllable stages. Shunt inductors are located at inputs and outputs of each of the controllable stages.

Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

Abstract: A hybrid electronic optical chip has a first photonic element with which a first diode is associated, a second photonic element with which a second diode is associated and a common electrical driver connected to the first and second diodes by a common electrical connection with opposite polarity. The electrical driver generates a common electrical drive signal divided in time into first and second drive signal components for independently driving the first and second photonic elements through the common electrical connection.

Abstract: Apparatus and associated methods relate to a time-interleaved integrating sampling front-end circuit using integrating buffers. In an illustrative example, a circuit may include N sampling layers of circuits, an ith sampling layer of circuits of the N sampling layers of circuits may include: (a) Xi buffers configured to receive an analog signal, Xi?1, and, (b) Yi track-and-hold circuits, each track-and-hold circuit of the Yi track-and-hold circuits is coupled to an output of a corresponding buffer of the X buffers, Yi?1, at least one buffer of the Xi buffers may include an integrating buffer, N?i?1. By implementing integrating buffers, a faster linear type of step settling response may be obtained as opposed to a slower exponential type of settling response.

Abstract: A capacitor simulation method and nonlinear equivalent circuit model enabling dynamic simulation of nonlinear characteristics when direct-current voltage is applied with high precesion are easily provided using a simple configuration. An equivalent circuit of a capacitor is represented using a series circuit of passive circuit elements. Characteristic change ratios of the passive circuit elements when a direct-current voltage is applied are expressed as an approximate function on the basis of an actually measured value. A reference voltage is referred to by control current sources connected in parallel to the passive circuit elements. The characteristic change ratios are calculated in accordance with the reference voltage Vref.

Abstract: There is provided a driver circuit configured to drive a light emitting device, the driver circuit including an asymmetric circuit configured to receive an input signal and include a first capacitor coupled to the input signal and a signal having a fixed electric potential so as to generate a first signal, a delay circuit configured to receive the input signal and delay the input signal so as to generate a second signal, and an adder circuit configured to add the first signal and the second signal so as to generate a drive signal for driving the light emitting device.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training and deploying machine-learned compact representations of radio frequency (RF) signals. One of the methods includes: determining a first RF signal to be compressed; using an encoder machine-learning network to process the first RF signal and generate a compressed signal; calculating a measure of compression in the compressed signal; using a decoder machine-learning network to process the compressed signal and generate a second RF signal that represents a reconstruction of the first RF signal; calculating a measure of distance between the second RF signal and the first RF signal; and updating at least one of the encoder machine-learning network or the decoder machine-learning network based on (i) the measure of distance between the second RF signal and the first RF signal, and (ii) the measure of compression in the compressed signal.

Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.

Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.

Abstract: To include in a device a controller to control operation of the device in a normal-operation mode and in a test mode for performing one or more tests including an accelerated aging test, a temperature sensor to measure operating temperature of the device, and an overheat protection circuit to prevent overheating of the memory device during the test mode. With this overheat protection circuit, a device may undergo an efficient and reliable accelerated aging test with reduced or non-existent, possibility of suffering an overheat damage.

Abstract: Circuitry for generating a compliance voltage (V+) for the current sources and/or sinks in an implantable stimulator device in disclosed. The circuitry assesses whether V+ is optimal for a given pulse, and if not, adjusts V+ for the next pulse. The circuitry uses amplifiers to measure the voltage drop across active PDACs (current sources) and NDAC (current sinks) at an appropriate time during the pulse. The measured voltages are assessed to determine whether they are high or low relative to optimal values. If low, a V+ regulator is controlled to increase V+ for the next pulse; if not, the V+ regulator is controlled to decrease V+ for the next pulse. Through this approach, gradual changes that may be occurring in the implant environment can be accounted for, with V+ adjusted on a pulse-by-pulse basis to keep the voltage drops at or near optimal levels for efficient DAC operation.

Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Abstract: An LC filter circuit reduces an output voltage ripple of a switching power supply using coupled inductors in combination with a capacitor to form a notch filter, and aligning the notch region of the notch filter with a ripple frequency of the switching power supply to attenuate the frequency region of the fundamental ripple frequency by a larger amount than other frequencies.

Abstract: A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.

Abstract: A pass switch circuit for transferring the voltage of an input node to an output node and a method of controlling the pass switch circuit are disclosed herein. The pass switch circuit includes a pass switch, a first capacitor, and a first switch. The pass switch transfers a voltage level from an input node to an output node. The first capacitor is configured such that the node of one side thereof has a first level of voltage when the voltage of the control node of the pass switch is in a first state. The first switch connects the node of the one side of the first capacitor with the control node of the pass switch.

Abstract: Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.

Abstract: A clipping circuit for an amplifier, the clipping circuit using a tunneling junction. A molecular or other tunneling electronic-based component within a hybrid analog-tunneling circuit is used to produce soft or hard clipping capability with enhanced control over the output. The circuit may be used as a distortion circuit for an electric guitar signal or other electronic signals.

Abstract: One embodiment of the instant disclosure provides a compact lower power thermal sensor that comprises a combination current generator configured to selectively generate a PTAT and a CTAT current; a convertor configured to generate digital output corresponding to the current mirrored by the current-reuse charge pump; and a current-reuse charge pump coupled between the combination current generator and the convertor, configured to mirror the current generated by the combination current generator and selectively establish a charging/discharging path to/from the convertor. The combination current generator selectively generates the PTAT and the CTAT current in accordance with an output state of the convertor, and the current-reuse charge pump selectively charges and discharges a capacitor of the convertor with the PTAT and the CTAT current in accordance with the output state of the convertor.

Abstract: A signal receiver may include the following elements: a first transmission gate connected to an signal input terminal and receiving a first reference voltage; a enable switch connected to a first power supply terminal and receiving a first enable signal; a p-channel transistor connected to the enable switch and the first transmission gate; a first protection switch connected to the p-channel transistor and receiving the first reference voltage; a second transmission gate connected to the signal input terminal and receiving a second reference voltage; an n-channel transistor connected to a second power supply terminal, an signal output terminal, and the second transmission gate; a second protection switch connected to the signal output terminal, the n-channel transistor, and the first protection switch and receiving the second reference voltage; and a pull-down transistor connected to the second power supply terminal, the n-channel transistor, and the output terminal and receiving a second enable signal.

Abstract: An apparatus and method are provided for controlling the gain of a common source differential amplifier. The common source differential amplifier includes a pair of a metal-oxide-semiconductor field effect transistors (MOSFETs) each including a gate, a drain, and a source and at least one common source degeneration MOSFET in electrical communication between the sources of the pair of MOSFETs, the at least one common source degeneration MOSFET including a plurality of gate structures. A controller is in electrical communication with the gate structures and is configured to selectively activate one or more of the gate structures for controlling the gain of the common source differential amplifier.

Abstract: A method of fiber Kerr nonlinear noise estimation in an optical transmission system comprises recovering received symbols from a received signal, isolating a noise component of the received signal, estimating coefficients of a matrix based on cross-correlations between the isolated noise component and the fields of a triplet of received symbols or training symbols or estimated transmitted symbols, estimating doublet correlations of the product or the quotient of the isolated noise component and the field of a received symbol or of a training symbol or of an estimated transmitted symbol, and estimating one or more parameters related to nonlinear noise based on the estimated coefficients of the matrix and based on the estimated doublet correlations.

Abstract: One example discloses a switching capacitive power converter, SCPC, including: an energy storage element; a voltage reference controller, and configured to output an adjusted reference voltage based on a received fixed reference voltage; and a charge pumping circuit configured to operate the SCPC at a charge pumping frequency and configured to charge the energy storage element at the charge pumping frequency if an absolute value of the power converter's output voltage is below an absolute value of the adjusted reference voltage; wherein if the charge pumping frequency is within a predetermined frequency exclusion range, the voltage reference controller is configured to set the adjusted reference voltage to a value such that the charge pumping frequency is no longer within the predetermined frequency exclusion range.

Abstract: In one embodiment, a semiconductor device may include forming a first inverter and a second inverter to selectively receive separate inputs of a differential input signal and directly connecting each of the first and second inverters to receive power directly from a voltage input and a voltage return. The first inverter may be configured to include a first control switch that is configured to selectively couple together an upper transistor and a lower transistor of the first inverter. The second inverter may be configured to include a second control switch that is configured to selectively couple together an upper transistor and a lower transistor of the second inverter.

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path. A signal path may have an analog path portion and a digital signal path portion.

Abstract: An apparatus includes a control circuit that includes a configuration register and configured to receive a configuration setting across an external bus. The configuration setting encodes a first voltage state for the apparatus. The control circuit includes an input configured to be coupled to an external electrical device. The control circuit is configured to determine a value of the external device that maps to a second voltage state for the apparatus. The control logic is configured to transition the apparatus to a safe mode upon a determination that the first voltage state does not match the second voltage state.

Abstract: A wireless power transmitter apparatus is provided with: a power transmitter circuit having input terminals to which a DC power is inputted and output terminals from which the power transmitter circuit outputs the AC power and which supply the AC power to a power transmitting coil; a DC monitor circuit that monitors the DC power at the input terminals of the power transmitter circuit, and outputs a DC monitor signal indicating a change in a characteristic associated with the DC power; and a demodulator circuit that detects a load-modulated signal based on the DC monitor signal, demodulates the load-modulated signal, and outputs a first demodulated signal. The load-modulated signal is transmitted from the wireless power receiver apparatus to the wireless power transmitter apparatus by changing power consumption of the wireless power receiver apparatus.

Abstract: An electronic device includes a power-up signal generation circuit block suitable for generating a power-up signal during a power-up section of a source voltage, a delay circuit block suitable for generating a plurality of delay signals by sequentially delaying the power-up signal, and a plurality of internal circuit blocks sequentially initialized in response to a corresponding one of the power-up signal and the delay signals.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a training entry signal and a transmission signal. The second semiconductor device may generate selection codes and a control signal in response to the training entry signal. The second semiconductor device may adjust a level of a reference voltage signal for buffering the transmission signal in response to the selection codes and control a capacitance of an internal node. The reference voltage signal may be outputted from the internal node in response to the control signal.

Abstract: A programmable (multistep) resistor attenuator architecture (such as for input to a differential amplifier) provides cancellation for harmonic distortion currents. An attenuation node is coupled: (a) to an input node through R; (b) to a virtual ground through kR and a virtual ground switch Swf with on-resistance Rswf; and (c) to a differential ground through mR and a differential ground switch Swp with on-resistance Rswp. Swp can be sized relative to Swf such that a component Ipnf of Ipn through Rswp and mR to the attenuation node, and branching into kR and Rswf, matches (phase/magnitude), a harmonic current Ifn from the virtual ground through Rswf and kR to the attenuation node. Harmonic distortion cancelation at the virtual ground can be based on matching switches Swf and Swp and the resistors R, mR, kR, reducing sensitivity to PVT variations, input frequency and amplitude. The attenuator architecture is extendable to multistage configurations.

Abstract: Circuitry for generating a compliance voltage (V+) for the current sources and/or sinks in an implantable stimulator device in disclosed. The circuitry assesses whether V+ is optimal for a given pulse, and if not, adjusts V+ for the next pulse. The circuitry uses amplifiers to measure the voltage drop across active PDACs (current sources) and NDAC (current sinks) at an appropriate time during the pulse. The measured voltages are assessed to determine whether they are high or low relative to optimal values. If low, a V+ regulator is controlled to increase V+ for the next pulse; if not, the V+ regulator is controlled to decrease V+ for the next pulse. Through this approach, gradual changes that may be occurring in the implant environment can be accounted for, with V+ adjusted on a pulse-by-pulse basis to keep the voltage drops at or near optimal levels for efficient DAC operation.

Abstract: Low noise amplifiers (LNAs) are provided, the LNAs comprising: a common gate matching network; a capacitord; a resistord; a coild, wherein a side1 of coild is coupled to a side1 of capacitord, a side1 of resistord, and a V+ and a side2 of the coild is coupled to a side2 of capacitord, a side2 of resistord, and a network input; a capacitors; a resistors; a coils, wherein a side1 of coils is coupled to an LNA input, a side1 of capacitors, a side1 of resistors, and a network output and a side2 of coils is coupled to a side2 of the capacitors, a side2 of resistors, and ground; and an output coil that is magnetically coupled to coild and coils and having a side1 coupled to a first terminal of an LNA output and a side2 coupled to a second terminal of the LNA output.

Abstract: The present invention provides a voltage boost driving circuit for LED backlight, which includes a first power input port, a second power input port, an LED light bar, a positive boost circuit, a negative boost circuit, and a luminance controlling circuit configured for controlling the luminance of the LED light bar; the first and second power input ports are respectively connected to the positive and negative poles of an external power supply; the positive boost circuit is connected between the first power input port and the positive pole of the LED light bar; the second power input port is connected to the ground; the negative boost circuit is connected to the positive boost circuit via the luminance controlling circuit, an output port of the negative boost circuit is connected to the negative pole of the LED light bar. An LCD device is further provided.