Abstract: A method of determining a linear or angular position of a magnetic sensor device relative to a magnetic source, or vice versa, the sensor device includes at least four magnetic sensor elements. The method involves the steps of: a) determining a first magnetic field gradient; b) determining a second magnetic field gradient; c) determining a ratio of the first and second magnetic field gradient; d) converting the ratio into a position; while matching signal paths of the magnetic sensor elements so as to improve signal-to-noise.

Abstract: Differential-signal receivers. One example is a method of operating a differential-signal receiver, the method comprising: receiving a first differential signal on a differential-signal pair, the first differential signal accompanying a common-mode voltage that is positive relative to a reference voltage of the differential-signal receiver; clamping, when the first differential signal is positive, an OUT+ node at a first voltage; and clamping, when the first differential signal is negative, the OUT? node at a second voltage.

Abstract: The present disclosure is directed to an ultracapacitor module comprising a housing and terminals, the terminals exposed through the housing, the housing containing one or more internal capacitor cells and one or more integrated, internal bypass diodes arranged together such that the ultracapacitor module additionally comprises an integrated, internal bypass circuit connected in parallel with the terminals. The present disclosure also is directed to an ultracapacitor module comprising a housing and terminals, the terminals exposed through the housing, the housing containing one or more internal capacitor cells and at least one set of one or more integrated, internal bypass diodes connected in parallel to the at least one or more internal capacitor cells, such that the ultracapacitor module additionally comprises an integrated, internal bypass circuit.

Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

Abstract: An alternator and a rectifier thereof are provided. The rectifier includes a transistor and a gate voltage control circuit. The transistor is controlled by a gate voltage. The gate voltage control circuit generates the gate voltage according to a voltage difference between an input voltage and a rectified voltage. During a first time interval after the voltage difference drops to a first preset threshold voltage, the gate voltage control circuit determines whether the voltage difference is less than a second preset threshold voltage, and decides whether to provide the gate voltage to turn on the transistor. When the transistor is turned on, the voltage difference substantially equals to a first reference voltage. And during a second time interval, the gate voltage control circuit regulates the gate voltage to set the voltage difference substantially to a second reference voltage.

Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.

Abstract: In order to achieve both of reduction of peak power and reduction of a transmission rate, an apparatus includes a reception processing unit configured to receive transmission signals from a transmission apparatus, the transmission apparatus performing precoding processing and clipping processing on the transmission signals and outputting a plurality of the transmission signals simultaneously in an identical frequency band; a signal separating unit configured to separate reception data sets from the transmission signals; and a transmission signal estimating unit configured to estimate a signal distortion component and a noise component due to the clipping processing and an interference component between the transmission signals, based on the reception data sets and gain information related to a channel for transmitting the transmission signals, and estimate transmission data sets by removing the signal distortion component, the noise component, and the interference component being estimated from the reception

Abstract: An over-temperature protection circuit is described. The circuit comprises an input for sensing a voltage across a transistor, a voltage-to-current converter configured to generate a current in dependence upon the voltage, an accumulator storing a value indicative of power dissipated by the transistor and which depends on the current; and a comparator configured to determine whether the value exceeds a threshold value and, in dependence on the value exceeding the threshold value, to generate a signal to cause the transistor to be switched off.

Abstract: The upper arm drive circuit for controlling drive of the upper arm switching element of the power conversion device includes: a capacitor disposed between a gate of the upper switching element and the output terminal of the power conversion device; a reverse current prevention circuit that is disposed between a power supply of the power conversion device and the capacitor, and that makes a current flow from a first terminal side of the reverse current prevention circuit connected to the power supply side to a second terminal side of the reverse current prevention circuit connected to the capacitor side and prevents a reverse current from flowing from the second terminal side to the first terminal side; and a switching element for capacitor charging that is turned ON in synchronization with a command signal that turns the upper arm switching element ON.

Abstract: A switching circuit includes a power switch, an active clamping circuit, and an active clamping control unit. When the power switch is modulated between an ON state and an OFF with a predetermined frequency, the active clamping control unit is configured to activate the function of the active clamping circuit for absorbing the energy of voltage surges. When the power switch is operating in the ON state or the OFF state, the active clamping control unit is configured to deactivate the function of the active clamping circuit for preventing the counter EMF from damaging the power switch.

Abstract: A limiter system for an active speaker may include at least one lowpass filter configured to receive an input signal and output a signal lower than a crossover frequency, at least one highpass filter, configured to receive an input signal and output a signal higher than the crossover frequency, a first allpass filter configured to adjust the phase of the signal lower than the crossover frequency, a second allpass filter configured to adjust the phase of the signal higher than the crossover frequency, a first limiter, configured to receive and limit the signal from the first allpass filter, a second limiter, configured to receive and limit the signal from the second allpass filter, and a mixer, configured to mix the signal lower from the first limiter and the signal from the second limiter.

Abstract: The present disclosure provides a power clamp circuit, a chip, and a dual-clamp method. The power clamp circuit is applied to a circuit system to monitor the power supply voltage of the circuit system and includes: an EOS protection module, for outputting an EOS protection triggering signal when it is determined that the circuit system is electrically overstressed based on the power supply voltage; an ESD protection module, for outputting an ESD protection triggering signal when it is determined that an electrostatic event is present in the circuit system based on the power supply voltage; a switch control module, for turning on a discharge path based on the EOS protection signal to discharge an EOS current, and turning on the discharge path based on the ESD protection signal to discharge an electrostatic current.

Abstract: The present disclosure includes apparatuses, methods, and systems for sensing two memory cells to determine multiple data values. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two self-selecting multi-level memory cells (MLC) of the plurality of memory cells to determine multiple data values. The data values are determined by sensing a memory state of a first MLC using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing a memory state of a second MLC using a second sensing voltage in a sense window between the first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to the second memory state.

Abstract: A soft-start circuit includes an error amplifier, a reference voltage ramp circuit, and a minimum current clamp circuit. The error amplifier is configured to generate a difference voltage representing a difference of a feedback voltage and a reference voltage ramp. The reference voltage ramp circuit is configured to generate the reference voltage ramp. The minimum current clamp circuit is configured to clamp an output of the error amplifier to a predetermined minimum voltage.

Abstract: A light-triggered transponder includes one or more of photo cells, a clock recovery circuit and a reverse antenna system. The clock recovery circuit (CRC) includes a photoconductor with a source terminal, a drain terminal for receiving a voltage, the photoconductor resistance varying with received light intensity. The CRC is configured to generate a recovered clock. A reverse antenna system connected to at least one photo cell and configured to transmit data. The photoconductor configured to produce a modulated voltage signal from an incident modulated light incident. The CRC can include an amplifier coupled to the source terminal of the photoconductor via a capacitor for receiving the modulated voltage signal and outputting an analog signal generated from the voltage signal. The CRC can include an inverter coupled to the amplifier and configured to digitize the analog signal of the amplifier.

Abstract: A control device includes a current detecting section that detects a sense current for a current flowing through a semiconductor element; a transient sensing period detecting section that detects a transient sensing period from a transient rising to a transient falling of a detection signal of the sense current, in response to the semiconductor element being turned ON; and a control section that controls the semiconductor element according to a detection result of the transient sensing period, based on the sense current detection signal. By detecting the transient sensing period with the transient sensing period detecting section and controlling the semiconductor element with the control section according to the transient sensing period detection result, based on the sense current detection signal, it is possible to identify overcurrent according to the transient response detection result of the sense current during the transient sensing period, and to actively protect the semiconductor element.

Abstract: A data channel aging circuit, a memory, a data channel aging method, and a memory aging method are provided. The data channel aging circuit includes: a memory cell storing a voltage switching signal configured to provide a target voltage state for each of a plurality of data channels in an integrated circuit (IC); a control unit configured to generate a voltage control signal and to send the voltage control signal to each data channel; and a strobe unit configured to switch a conductive state of each data channel based on the voltage switching signal, and to adjust a voltage level of each data channel through the voltage control signal to induce voltage stress aging. The data channel aging circuit improves the reliability of the aging test and the operational stability of the IC products that have went through the aging test.

Abstract: An integrated circuit is formed on a substrate, and the integrated circuit includes first and second conductors for providing supply and ground voltages, respectively, a clamp device, and a trigger circuit. The clamp device includes first and second metal oxide semiconductor (MOS) transistors coupled in series between the first and second conductors, wherein the first and second MOS transistors include first and second gates, respectively. The trigger circuit is coupled between the first and second conductors and is configured to drive the first and second gates with first and second voltages, respectively, in response to an electrostatic discharge (ESD) event. The trigger circuit includes a biasing circuit for generating the first voltage as a function of the supply voltage, a PMOS transistor coupled between the first conductor and the second gate, wherein the PMOS transistors includes a third gate.

Abstract: An electronic device is described which has a sensor panel comprising a plurality of receive electrodes configured to measure signals received from one or more transmit electrodes. The device has a sensor panel control module configured to: receive signals from the plurality of receive electrodes in the presence of at least one tone interferer. The module is configured to convert the received signals from a time domain into a frequency domain; and to process the received signals in the frequency domain in order to mitigate the effect of the tone interferer.

Abstract: A control system for a central plant having subplants including devices operating to serve energy loads of a building. The system includes a high level optimization module that performs high level optimization of thermal loads subject to constraints to generate subplant load allocations. The control system includes a low level optimization module that performs low level optimization of the subplant load allocations to determine operating states for the devices. The control system includes a constraint modifier that modifies the constraints for the high level optimization module based on equipment schedules. The control system also includes a binary optimization modifier including a pruner module that receives the minimum off schedule to determine adjusted branches and a seeder module that receives the minimum on schedule to determine a starting node for use in binary optimization performed by the low optimization module.

Abstract: In a general aspect, a circuit can include a pass device configured to receive an input voltage and provide an output voltage. The circuit can further include a current sink coupled with a control terminal of the pass device, the current sink being configured to discharge the control terminal of the pass device to limit the output voltage in response to the input voltage exceeding a threshold voltage. The circuit can also include a switch coupled in series with the current sink, the switch being configured to enable the current sink in response to the input voltage exceeding the threshold voltage.

Abstract: A power switch circuit is disclosed. The power switch circuit includes an input terminal, an output terminal, a power switch, a control circuit and a voltage holding circuit. The power switch is coupled between the input terminal and the output terminal. The power switch has a control terminal. The control circuit is coupled to the input terminal and the output terminal respectively. The control circuit compares a first voltage of the input terminal with a second voltage of the output terminal to generate a control signal. The voltage holding circuit is coupled to the control circuit and the control terminal. The voltage holding circuit provides a default voltage larger than 0 V to the control terminal according to the control signal.

Abstract: A system for troubleshooting signals in a cellular communications network, and in particular, for determining the cause of distortion or corruption of such signals, includes a robotic or other type of switch. The robotic switch can tap into selected uplink fiber-optic lines and selected downlink fiber-optic lines between radio equipment and radio equipment controllers in a wireless (e.g., cellular) network to extract therefrom the I and Q data. The selected I and Q data, in an optical form, is provided to an optical-to-electrical converter forming part of the system. The system includes an FPGA (Field Programmable Gate Array) or the like, and an analytic computer unit, or web server, and SSD (Solid State Drive) and magnetic disk storage, among other components of the system. The system analyzes the I and Q data provided to it, and determines the cause, or at least narrows the field of possible causes, of impairment to transmitted signals.

Abstract: A tunable filter is described where the frequency response as well as bandwidth and transmission loss characteristics can be dynamically altered, providing improved performance for transceiver front-end tuning applications. The rate of roll-off of the frequency response can be adjusted to improve performance when used in duplexer applications. The tunable filter topology is applicable for both transmit and receive circuits. A method is described where the filter characteristics are adjusted to account for and compensate for the frequency response of the antenna used in a communication system.

Abstract: An active limiting system that is suitable to protect a low noise amplifier against the high power signals received from a signal input includes, at least one first switch, source of which is connected to a gate voltage; at least first resistor which is connected between the gate and source of the first switch; at least one second resistor, which is connected between a drain voltage and drain of the first switch; at least one second switch, source of which is connected to said drain voltage and drain of which is connected to a signal input; at least one third resistor which is connected between the drain of the first switch and gate of the second switch; at least one first filtering element, which blocks DC currents/voltages and which is connected between the source of the second switch and ground.

Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

Abstract: This application relates to monitoring of electronic devices (100) and in particular to methods and apparatus for the detection and recording of an electrical overstress applied to a connector (101, 102) of the device. The apparatus describes an integrated circuit integrated circuit (103, 105) of the host device having a first set of one or more circuit contacts (201, 203, 204, 205) for connection to a connector (101) of a host electronic device. The circuit has an electrical overstress monitor (106, 106a) for detecting and recording an electrical overstress comprising a voltage exceeding a predetermined parameter applied to at least one of said first set of circuit contacts. The electrical overstress monitor (106) may have an overvoltage detector (205) and may have a memory (206) for recording the occurrence of an overvoltage and/or a communication module (207) for communicating with other components of the host device in the event of an electrical overstress.

Abstract: An image sensor pixel may include a photodiode, a floating diffusion, and a transfer gate. Column readout circuitry coupled to the image sensor pixel via a column line. Voltage settling circuitry may be coupled to the column line. Voltage settling circuitry may include a pre-charging circuit, a reset voltage slew boosting circuit, and an image signal voltage slew boosting circuit. The pre-charging circuit may pull down the column line voltage to a grounding voltage. The reset voltage slew boosting circuit may pull up the column line voltage to a reference voltage near a reset level voltage. The image signal voltage slew boosting circuit may pull down the column line voltage to an additional reference voltage near an image signal voltage. With the use of the voltage settling circuitry, a faster pre-charge and clamping of the column line can be achieved.

Abstract: A secondary controller applied to a secondary side of a power converter includes a control signal generation circuit, a voltage detection signal generation circuit, and a gate control signal generation circuit. The control signal generation circuit generates a short-circuited control signal to a short winding switch after a gate control signal to make the short winding switch be turned on. When an output voltage of the power converter is less than a predetermined voltage, the voltage detection signal generation circuit generates a first detection signal to the control signal generation circuit. The control signal generation circuit further generates a gate pulse control signal according to the first detection signal. The gate control signal generation circuit generates a gate pulse signal according to the gate pulse control signal, wherein the gate pulse signal is used for making a primary side of the power converter be turned on.

Abstract: An apparatus includes an input port, an output port, a first bias input, a first shunt PIN diode, a first radio frequency (RF) choke inductor, and a first direct current (DC) blocking capacitor. The input port may be connected to the output port, a first terminal of the first shunt PIN diode, and a first terminal of the first RF choke inductor. A second terminal of the first RF choke inductor is connected to a first terminal of the first DC blocking capacitor and the first bias input. A second terminal of the first shunt PIN diode and a second terminal of the first DC blocking capacitor are connected to a circuit ground potential. A first bias voltage having a magnitude lower than a knee voltage of the first shunt PIN diode is applied at the first bias input.

Abstract: Disclosed is a system and method of determining the test surface profile and compensating the gain amplitude when using time reversal focal laws in ultrasound non-destructive testing. Computer simulations are used to compute the diffraction field at time of incidence of the transmitted parallel wave front on the test surface. Knowledge of the surface profile and the diffraction field allows determination of coverage at the test surface and improved accuracy of flaw sizing.

Abstract: An integrated circuit includes an input terminal configured to receive an input signal, a reference voltage node configured to provide a control voltage, and a pass transistor comprising a first terminal coupled to a first node, a control terminal coupled to the reference voltage node, and a second terminal coupled to the input terminal. The control voltage has a control voltage level sufficient to allow a signal to pass from the second terminal to the first terminal. The pass transistor is configured to linearly transfer the input signal to the first node in response to a voltage level of the input signal being below a first voltage level and configured to transfer a voltage-limited version of the input signal to the first node in response to the voltage level being above the first voltage level. At most, a negligible DC current flows through the input terminal into the second terminal.

Abstract: Briefly, embodiments of claimed subject matter relate to controlling a voltage across a circuit element utilized in a pre-driver for a bidirectional communications bus. In embodiments, a voltage control circuit may be utilized to reduce electrical stress across a capacitor coupled to the pre-driver to the communications bus. The voltage control circuit may operate to provide a voltage to a middle point between two capacitors, of a plurality of capacitors, which may operate to limit voltage across one or more capacitors to below a predetermined limit.

Abstract: A semiconductor switching string includes series-connected semiconductor switching assemblies, each having a main semiconductor switching element that, when switched on, conducts current flow from a first terminal to a second terminal, and that, while turning off, transitions from a reverse recovery mode in which a reverse recovery current flows from the second terminal to the first terminal to a blocking mode in which no current flows. Each main semiconductor switching element has an active auxiliary circuit, each including an auxiliary semiconductor switching element and a resistive element. Each control unit is connected with each auxiliary semiconductor switching element. Each control unit switches a respective auxiliary semiconductor switching element into a conducting state to divert current through the corresponding resistive element.

Abstract: A signal amplifier having an input impedance that varies over different bias currents, the signal amplifier comprising a compensation stage including a switchable variable resistance configured to provide a targeted adjustment to the input impedance. A signal amplifier comprising: a variable-gain stage configured to provide a plurality of gain levels that result in different input impedance values; and a compensation stage having a switchable variable resistance configured to provide a targeted adjustment to a respective input impedance. a compensation stage having an output coupled to an input of the gain stage, the compensation stage including a plurality of band selection switches coupled to the plurality of input nodes and a plurality of switchable variable resistance branches coupled to the band selection switches, individual switchable variable resistance branches configured to provide a targeted adjustment to a respective input impedance.

Abstract: Disclosed is a high-speed track-and-hold device including a buffer stage circuit including a PMOS source follower and a post linear circuit, and a sampling stage circuit that is responsible for supplying a source voltage (VSS) to the buffer stage circuit and that is arranged so that a switch connected to a gate is connected to the source voltage (VSS) and the NMOS transistor of a sampling stage is turned off in hold operation.

Abstract: A method for setting a MRI sequence, a magnetic resonance device, and a computer program product are provided. The method includes providing, by a limitation unit, at least one limitation; providing, by a parameter provision unit, a plurality of parameters of the sequence, wherein at least one parameter of the plurality of parameters is assigned to a default parameter value; selecting, by a selection unit, a parameter of the plurality of parameters; determining, by a simulation unit, at least one sequential pattern based on at least one default parameter value of the default parameter values; determining, by an analysis unit, a permissible range of parameter values of the selected parameter based on at least one sequential pattern and the at least one limitation; and establishing, by an establishment unit, a new parameter value of the selected parameter within the permissible range of the parameter values.

Abstract: A voltage supply system is disclosed, comprising a boost converter configured to receive an input voltage and generate a first output voltage at a first output node, a low-voltage supply circuit configured to receive the input voltage and generate a second output voltage at a second output node, and a routing circuit configured to route the first output voltage of the boost converter to the second output node during a selected condition of the input voltage.

Abstract: A circuit protective system with an input for sensing a reference current and an input for sensing a reference voltage. The system also has circuitry for determining an estimated energy in response to the reference current and the reference voltage and circuitry for generating a control signal responsive to the estimated energy exceeding a threshold.

Abstract: A two-stage high-power RF limiter circuit for an RF signal receiver incorporates a heavy limiting stage to limit high energy pulses of a received RF signal to a desired power threshold over a sustained time period, while a light limiting stage reacts quickly to high energy pulses to reduce spike leakage associated with the slower reaction time of the heavy limiting stage. Both heavy and light limiting stages incorporate PIN diodes biased to a voltage just below the desired power threshold (the light limiter biased to a slightly higher voltage than the heavy limiter) so the PIN diodes do not activate until power levels are high enough to warrant limiting. The holdoff voltage across the PIN diodes is maintained by Zener diodes biased to a voltage corresponding to the power threshold, allowing the PIN diodes to self-bias once the power threshold is reached.

Abstract: The on-state malfunction detection device detects an on-state malfunction, for instance, in an IGBT that is provided to correspond to a PTC element whose electrical resistance value varies according to temperature and that controls the electrification of the PTC element. In a state in which a turn-off instruction has been outputted from a control device to the IGBT, the on-state malfunction detection device determines through calculation an electric potential difference following voltage division of the voltage between the both ends of the PTC element, and detects an on-state malfunction of the IGBT when this electric potential difference is equal to or greater than a predetermined threshold value. This allows for the detection of an on-state malfunction in a switching element that performs an electrical conduction control for an element whose electrical resistance value varies according to temperature.

Abstract: A voltage detector includes a first node configured to have a first supply voltage, a second node configured to have a second supply voltage, and an output node. The voltage detector is configured to drive the output node to the first supply voltage in response to a difference between the first supply voltage and the second supply voltage exceeding a predetermined threshold voltage value.

Abstract: A protection circuit for an integrated circuit product die or die-let (die-let) is responsive to whether the die-let has undergone a dicing operation or not. A test circuit on the die-let's semiconductor wafer can test and/or configure the die-let. After the dicing operation, the protection circuit generates a signal to isolate the cut input lines from the test circuit to prevent any interference with the normal operation of the integrated circuit product die-let.

Abstract: Use of a closed loop APC may involve a problem of cost and power consumption due to increased circuit scale. The semiconductor device includes a power amplifier that amplifies an output from a transmission circuit and a regulator that supplies power to the power amplifier. The regulator includes an operational amplifier comprising a loop gain control circuit and a loop gain control voltage generation circuit that supplies control voltage to the loop gain control circuit. The loop gain control voltage generation circuit minimizes a loop gain of the operational amplifier when starting up the regulator.

Abstract: Techniques for limiting the output voltage of an amplifier without directly affecting an output current of the amplifier are provided. In an example, an amplifier can include a plurality of amplifier stages configured to receive an input voltage and to provide an output voltage as a function of the input voltage, and a comparator configured to receive a voltage limit and a representation of the output voltage of the amplifier, to adjust current at an input to a first amplifier stage of the plurality of amplifier stages when the output voltage violates the voltage limit, and to clamp the output voltage at an offset from the voltage limit.

Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

Abstract: To provide an inductive load driving device which can control a clamp voltage using a ground voltage as a reference, with a simple structure. An inductive load driving device includes: an inductive load whose one end is connected to a power source and whose other end is connected to a ground: an output stage semiconductor switch element connected in series with the inductive load; a clamping circuit connected between a high-voltage side electrode and a control electrode of the output stage semiconductor switch element; and a resistance value control unit connected between the control electrode of the output stage semiconductor switch element and the ground.

Abstract: A switching power conversion system includes a main power circuit structured to convert power from a power source at an input voltage to an output voltage using a first inductive current. The power conversion system also includes a secondary power circuit structured to scale the first inductive current to a second inductive current smaller than the first inductive current by a scaling factor. A controller is configured to control operations of the main power circuit and the secondary power circuit. Zero voltage switching (ZVS) and zero current switching (ZCS) is detected by sensing voltages across switches on the secondary power circuit. Accuracy can thus be improved. Output current of the conversion system is also determined by monitoring the voltage across a sense resistor in the secondary power circuit, which is a scaled representation of the output current, thus power loss can be reduced.

Abstract: Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

Abstract: Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.