Abstract: A high-speed serial computer expansion bus circuit topology, comprises: a first signal path connecting between a first interface and a second interface, a second signal path connecting between the first interface and a third interface, a third signal path connecting between the third interface and a fourth interface, a first selector circuit having a first passive element and a second passive element which are respectively disposed in the first signal path and the second signal path, a second selector circuit having a third passive element and a fourth passive element which are respectively disposed in the second signal path and the third signal path. The second signal path is conducted when the first passive element and the second passive element are conducted, the third signal path is conducted when the third passive element and the fourth passive element are conducted.

Abstract: The present disclosure provides a means to adjust the relative location of output rising and falling transitions to reduce single-ended duty cycle distortion (DCD) effects in the output data stream originating from the transmitter data path. This serves to improve high-speed single-ended signal characteristics and reduce electromagnetic interference (EMI). Another feature enabled by embodiments of the present disclosure is polarity skew (also referred to as differential skew) reduction between transmitter outputs. In an embodiment, the disclosed method and apparatus for transmitter data path single-ended DCD correction describes a closed-loop calibration system including the actuation apparatus within the transmitter, a sensing block at the output of the transmitter to measure the amount of single-ended DCD, and a calibration block operating on the sensor output to devise correction control inputs to the actuator in the transmitter to correct the data path single-ended DCD present.

Abstract: The present disclosure provides a means to adjust the relative location of output rising and falling transitions to reduce single-ended duty cycle distortion (DCD) effects in the output data stream originating from the transmitter data path. This serves to improve high-speed single-ended signal characteristics and reduce electromagnetic interference (EMI). Another feature enabled by embodiments of the present disclosure is polarity skew (also referred to as differential skew) reduction between transmitter outputs. In an embodiment, the disclosed method and apparatus for transmitter data path single-ended DCD correction describes a closed-loop calibration system including the actuation apparatus within the transmitter, a sensing block at the output of the transmitter to measure the amount of single-ended DCD, and a calibration block operating on the sensor output to devise correction control inputs to the actuator in the transmitter to correct the data path single-ended DCD present.

Abstract: A voltage comparator includes an amplifier coupled to receive an input signal at an amplifier input and generate an output signal at an amplifier output in response to the input signal. The amplifier includes a current generation circuit coupled to generate a first current flowing through a first branch and a second current flowing through a second branch. A first transistor has a first terminal coupled to the amplifier input and a second terminal coupled to the first branch. A second transistor has a third terminal coupled to the second branch, a fourth terminal coupled to a reference voltage. A second control terminal of the second transistor is coupled to the first control terminal. An output circuit is coupled to the amplifier output to generate a comparator output signal in response to the output signal. The amplifier output is coupled to the second branch.

Abstract: A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

Abstract: In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.

Abstract: A charge pump module including a ratio control circuit and a charge pump circuit is provided. The ratio control circuit provides a boost ratio based on a control signal. The ratio control circuit includes at least two ratio generation circuits having different boost ratios. The ratio control circuit dynamically switches between the ratio generation circuits to adjust the provided boost ratio based on the control signal. The charge pump circuit is coupled to the ratio control circuit. The charge pump circuit receives an input voltage and converts the input voltage into an output voltage based on the boost ratio provided by the ratio control circuit. Furthermore, a voltage generation method of a charge pump module is also provided.

Abstract: There is disclosed a power supply stage, comprising: generating means for generating a power supply voltage from a high efficiency variable voltage supply in dependence on a reference signal; adjusting means for receiving the generated power supply voltage, and adapted to provide an adjusted selected power supply voltage tracking the reference signal in dependence thereon.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×M+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: System and method for amplifying an input signal to generate an output signal. The system includes a current generator, an oscillator, and a comparator. The current generator is configured to receive a first voltage signal, and generate a first current signal based on at least information associated with the first voltage signal and the first reference signal. The oscillator is configured to receive at least the first current signal and a second reference signal, and to generate a second voltage signal based on at least information associated with the first current signal and the second reference signal, the second voltage signal being associated with a modulation frequency. Additionally, the comparator is configured to receive the second voltage signal and a third voltage signal, and to generate a modulation signal related to the modulation frequency based on at least information associated with the second voltage signal and the third voltage signal.

Abstract: A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.

Abstract: A level shifter includes a level shifting circuit which receives input signal from a function block and changes the voltage level of the input signal, to output an output signal; a current blocking circuit, which suppresses current flowing to the level shifting circuit in an input suppression mode in which power supplied to the function block is cut and deactivates the level shifting circuit; and an output control circuit, which controls the output signal of the level shifting circuit to have a direct current (DC) voltage level in the input suppression mode.

Abstract: A reference voltage generating circuit includes a current generating section, a voltage generating section, a voltage dividing circuit, and a synthesis section. The current generating section generates a first current having a positive temperature coefficient. The voltage generating section generates a voltage having a negative temperature coefficient. The voltage dividing circuit divides the voltage of the negative temperature coefficient, generated by the voltage generating section. The synthesis section generates a voltage which is the sum of a terminal voltage obtained on causing the first current through a resistor and a voltage obtained on dividing the voltage having the negative temperature coefficient by the voltage dividing circuit, and outputs the sum voltage generated as a reference voltage.

Abstract: A clamping circuit including: a subtracter for subtracting a clamping correction voltage from an input analog voltage signal; A/D converter for converting an analog voltage signal from the subtracter into a digital voltage signal of M bits; a potential difference detection circuit for detecting a potential difference between a digital voltage signal outputted from the A/D converter and a previously set clamping voltage; D/A converter for converting a digital signal of N (N<M) bits within the digital signal of M bits representing a potential difference outputted from the potential difference detection circuit into an analog signal; an adjusting voltage generation circuit for generating an adjusting voltage based on a potential difference outputted from the potential difference detection circuit and a threshold voltage set with respect to the potential difference; and an adder for adding together an output from the D/A converter and an adjusting voltage outputted from the adjusting voltage generation circuit

Abstract: An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage.

Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.

Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.

Abstract: An active voltage-clamping gate driving circuit comprises a difference comparison circuit for receiving a reference voltage, a gate driving signal, and a preset voltage level, and outputting a voltage comparison signal; and a gate driving circuit for receiving an input signal and the voltage comparison signal, and outputting a gate driving signal. The voltage comparison signal controls the gate driving circuit. When a level difference between the gate control signal and the reference voltage is equal to the preset voltage level, the gate driving circuit is turned off, so that the level of the gate control signal is clamped to the preset voltage level, and the gate driving circuit does not output quiescent direct current under the clamped state.

Abstract: This patent specification describes a backflow prevention circuit which includes a first switch configured to conduct or to shut down a current path from an input terminal to an output terminal, a logic circuit configured to binarize an input voltage at the input terminal based on an output voltage at the output terminal and to output a binary signal and a shutdown circuit configured to cause the first switch to shut down independently of a switching control signal in accordance with the binary signal output from the logic circuit. The switching control signal performs a switching control of the first switch. The logic circuit outputs a shutdown signal to shut down independently of the switching control signal when the input voltage becomes smaller than the output voltage.

Abstract: An N-channel transistor protection circuit and method are disclosed that prevent gated diode breakdown in N-channel transistors that have a high voltage on their drain. The disclosed N-channel protection circuit may be switched in a high voltage mode between a high voltage level and a lower rail voltage. A high voltage conversion circuit prevents gated diode breakdown in N-channel transistors by dividing the high voltage across two N-channel transistors, MXU0 and MXU1, such that no transistor exceeds the breakdown voltage, Vbreakdown. An intermediate voltage drives the top N-channel transistor, MXU0. The top N-channel transistor, MXU0, is gated with a voltage level that is at least one N-channel threshold, Vtn, below the high voltage level, Vep, using the intermediate voltage level, nprot.

Abstract: A circuit arrangement for control of a regulated path and a semiconductor circuit (1) comprises a control connection, with an input, to which a switching signal (3) for control of the semiconductor circuit (1) is applied, an output, to which the control connector of the semiconductor circuit (1) is coupled, a control circuit (2) arranged between input and output. The switching signal (3) may be retained at the current value by means of a hold signal and an analytical circuit (2), which measures a voltage corresponding to the voltage across the controlled path and generates the holding signal for the control circuit (2) for a given duration when the voltage across the controlled path of the semiconductor circuit (1) has a rise which indicates a switching off of the semiconductor circuit (1).

Abstract: An impedance controller that controls termination impedance of at least one output based on a reference value including a programmable reference impedance generator, at least one termination logic element, and an impedance matching controller. The programmable reference impedance generator develops a reference impedance controlled by a reference impedance control input. Each termination logic element includes a programmable termination impedance generator coupled to a corresponding output and controlled by termination impedance control input. The impedance matching controller continually adjusts the reference impedance control input to match the reference impedance with the reference value within a predetermined tolerance and generates the termination impedance control input based on the reference impedance control input.

Abstract: A method of reducing package stress includes placing matched components of an op-amp substantially in a region of a die having the least stress gradients. The region is located in the center of the die. Further, the center is the common centroid of the die. The matched components are the current mirror input stages of the op-amp. In one embodiment, a semiconductor configuration includes a die having a region with the least stress gradients, and an op-amp containing matched components that are located substantially in the region.

Abstract: In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from ?-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages.

Abstract: An amplifying circuit includes an amplifying stage for receiving input signals to generate output signals. A swing detect unit detects signal levels of the output signals. A clamp unit variably limits signal levels of the input signals based on the signal levels of the output signals detected by the swing detect unit to improve the speed of the amplifying circuit.

Abstract: An impedance control circuit designed to match the impedance between a semiconductor device and a transmission medium (PCB) by using a current source installed in the semiconductor device instead of using an external resistor is provided. Since the impedance control circuit does not use an external resistor for impedance matching, the PCB size can be reduced. In particular, a controllable current source matches the impedance more precisely compared to the external resistor.

Abstract: Various circuits and methods provide for dc offset reduction that is effective under varying circuit and signal conditions. The offset signal is first sampled and stored, and then subtracted from the signal path via a programmable transconductance amplifier that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique is capable of compensating for variations in the magnitude of the offset signal. In one embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.

Abstract: According to an aspect of the present invention there is provided an LSI device having an output terminal outputting a data, comprising a data output circuit connected to the output terminal and capable of adjusting an output impedance thereof; and an adjustment circuit which detects a transient voltage at the output terminal when an output logic of the data output circuit is switched in a condition that a transmission line not terminated by a terminating resistor is connected to the output terminal, compares the transient voltage with a reference voltage, and adjusts the output impedance of the data output circuit so as to match a characteristic impedance of the transmission line.

Abstract: A single-ended circuit, such as an LNA (300), in accordance with the present invention includes an input power matching circuit (310) and a bias circuit (305) connected to an output transistor (Qin) which provides the amplification. A degeneration inductance (Le) and load impedance (Lo) couple to the emitter and collector of the output transistor (Qin), respectively. The bias circuit (305) is configured to eliminate base shot-noise of the mirror transistor (Q1) which generates the amplification. The bias circuit (305) in accordance with the present invention also eliminates the noise of the bias resistor (Rx1) that is included within the bias circuit (305). Specifically, the bias circuit (305) includes a current reference source (Iref) and an emitter follower circuit (315) connected to a current mirror circuit (Q1, Q2, Rx2) that connects to a bias resistor (Rx1). This bias circuit (305) can be implemented in a wide-class of single-ended circuits.

Abstract: Accuracy of correction of offset drift with temperature and noise are corrected in a high voltage, high current amplifier is improved by thermal isolation and/or temperature regulation of another amplifier having greater gain and connected to a different power supply in a closed loop feedback servo system. A clamping network connected to the higher gain amplifier to avoid hard saturation due to transient feedback signals from a reactive load, especially an inductive load, also prevents hard saturation of the high voltage, high current amplifier. An adjustable feedback circuit connected to the higher gain amplifier allows adjustment to obtain critical damping of a second order system and faster response to achieve proportionality of output current to input voltage with an accuracy of very few parts per million error and with minimum settling time.

Abstract: An embodiment of the invention is directed to a buffer circuit having a closed loop negative feedback amplifier that is coupled to continuously drive a node to a predetermined set voltage. A precharge circuit is coupled to selectively drive the node at a higher rate than the amplifier. The buffer circuit is particularly useful for reducing the recovery and settling time of the node voltage when the node is suddenly subjected to a large, capacitive load.

Abstract: An automatic threshold level control circuit is provided which is capable of controlling the threshold level without causing the DUTY deterioration. The automatic threshold level control circuit comprises a timing detecting circuit 110a, used for preserving the peak voltage values of each input signals for input signals (ATCIN+ and ATCIN−) and for outputting the preserved voltage values as a reference signal for the threshold level of each input signal, and the automatic threshold level control circuit comprises a pair of peak value detecting circuits PD1 (62) and PD2 (64) for resetting the held voltage values into reference voltages Vref1 and Vref2 by reset signals PD1RST and PD1RST; and the timing detecting circuit 110a for detecting a predetermined timing and outputting the reset signals PD1RST and PD2RST to the peak value detecting circuits PD1 and PD2 for releasing the reset state in accordance with the detected timing.

Abstract: A clock-referenced switching bias current source is disclosed wherein an accurate bias current is established based on the charge dissipated by a switching capacitor over a predetermined period. The time period is established by a very accurate system clock. The value of the capacitor can be accurately selected with .+-.10%. By selecting a particular capacitance and frequency, a desired average bias current value is determined according to the amount of charge dissipated over the predetermined period. In different embodiments, the bias current source can be configured to provide a bandgap current that is temperature and/or process independent.

Abstract: Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.

Abstract: A low power current-to-frequency converter circuit provides an output frequency signal F.sub.OUT having a frequency that varies as a function of a low level analog input current signal. The analog input current signal is typically generated by an implantable sensor element, designed to sense a particular substance or parameter within body tissue or fluids to which the sensor is exposed, with the magnitude of the analog signal providing a measure of the sensed substance or parameter. Conversion of the low level analog current to the output frequency signal facilitates transmission of the data signal over a shared data bus and other digital processing of the data signal.

Abstract: The invention relates to a system for transmitting binary signals over a signal line to a signal detecting device, in which a DC source is temporarily connectable to the signal line for generating binary signals. A discharge circuit is connected to the signal line. In order to keep the power loss very low in such a system, discharge circuit (7) contains a switchable current sink (8) connected to a signal line (3). Discharge circuit (7) also has a threshold value determination device (19) connected to signal line (3) in parallel with switchable current sink (8). Output (26) of threshold value determination device (19) is connected with a control input (17) of switchable current sink (8).

Abstract: A circuit suppresses an additive transient disturbance in an input signal. A main signal path transmits the input signal, and a switchable signal path is switchable into the main signal path during a portion of the disturbance. A positive envelope detector and a negative envelope detector detects, respectively, a positive envelope signal and a negative envelope signal. In response to these signals, positive and negative envelope signals are subtracted from the main signal path only during the portion of the disturbance.

Abstract: Circuit for preventing the improper functioning of a CMOS output buffer that may occur due to the fact that since the output buffer P-channel may be coupled between a supply voltage and an output pad. If the pad is driven higher than the supply voltage by an external source, current may be injected into the parasitic diodes of the source/drain of the transistor.

Abstract: An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than the bias voltage less the pass transistor threshold. The first control voltage corresponds to the input voltage for input voltages less than the bias voltage less the pass transistor threshold.

Abstract: A nonvolatile semiconductor memory device has a semiconductor substrate of a first conductivity type, at least a pair of element isolation insulating films and a pair of spaced source/drawn regions of a second conductivity type different from the first conductivity type and formed in a surface of the semiconductor substrate. A floating gate electrode is formed above a channel region disposed between the pair of source/drain regions in the surface of the semiconductor substrate in an insulated relationship with the channel region. The floating gate electrode overlaps each of the element isolation insulating films and a gap is formed between an underside of the floating gate electrode and each of the element isolation insulating films at each of portions thereof where the floating gate electrode overlaps the pair of element isolation insulating films, respectively. A control gate electrode is formed above the floating gate electrode in an insulated relationship with the floating gate electrode.

Abstract: A filter boost preattenuator provides controlled, rapid variable signal preattenuation at the input of a filter to optimally compensate for the absolute gain increase of the filter caused by increasing the high frequency boost level of the filter. The amplitude of the filter output exhibits very little change during boost variations that dynamically occur in applications such as data and servo signal recovery in disk drives. Using the present invention, disk space overhead needed to allow for readjustment of the automatic gain control system of a read/write channel is minimized. In the present invention, the feedforward signal provided from the variable gain boost circuit is applied to a feedback circuit and subtracted from the system input. The feedback forces a drop in the overall gain of the filter that increases with boost gain.

Abstract: According to the present invention, an integrated regulator having an adjustable reset threshold is disclosed. The integrated regulator has the following elements contained within an integrated circuit device: a transistor, a voltage reference block, an internal resistive network, an operational amplifier which regulates the voltage output signal of the integrated regulator by regulating the base current of the transistor, and a comparator which senses and communicates to the user when the operational amplifier is unable to maintain the voltage output signal within an acceptable range of a desired value of the voltage output signal. External to the integrated circuit device is an external resistive network. When the reset output signal of the integrated regulator is equal to an active state, this is indicative that the operational amplifier has been unsuccessful in keeping the voltage output signal within the acceptable range of the desired value of the voltage output signal, i.e.

Abstract: An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than a value equal to the bias voltage less the pass transistor threshold, and corresponding to the input voltage for input voltages less than the bias voltage less the pass transistor threshold.

Abstract: A virtual ground array semiconductor memory device includes a matrix of memory cells, which performs writing and erasing operations utilizing FN current, reduces the electric power consumption and the deterioration of a tunnel insulating film. Each memory cell has a floating gate on one side of a channel region and a control gate covering the floating gate and the other side of the channel region.

Abstract: The present invention provides an output level control circuit for a transmitter of an automobile telephone system which can output a transmission output signal of an output level indicated by a level setting signal with a high degree of accuracy. First and second level control circuits function for a low-level side and a high-level side, respectively, of the detection output of a detection circuit and perform weighting such that the outputs vary with linearity relative to the output signal of the amplifier. A control signal generation circuit causes a selection circuit to select a first or second error signal of a first or second comparison circuit, respectively. The first and second comparison circuits receive the output of the first or second level control circuit, respectively, and these control circuits process the detection output corresponding to the output level of the output signal of the amplifier indicated by a level setting signal.