Abstract: Receiver circuit providing interface between a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor IC devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels.

Abstract: A clock buffer circuit with dc offset suppression. In one embodiment, the circuit comprises a differential amplifier providing a differential signal to a voltage follower. The output of the voltage follower is fed back through resistors to a differential amplifier to the respective inputs to the voltage follower. The feedback is negative at low frequencies and less negative or positive about the clock frequency.

Abstract: A voltage clamping circuit includes a PIN diode with a first end connected to a signal line, a capacitor connected between ground and a second end of the PIN diode; and a reference voltage applied to a junction of the PIN diode and the capacitor. Dual arrangements of the clamping circuit may be used to limit a voltage on the signal line within a desired range. The voltage clamping circuit is effective for protecting RF power transistors from overdrive conditions while operating at frequencies above 300 MHz and power levels in excess of 50 watts. The voltage clamping circuit has minimal adverse impact on circuit operation and efficiency. Specific examples include a power oscillator providing over 170 RF watts at above 700 MHz with the voltage clamping circuit providing protection from destructive feedback.

Abstract: An improved output driver for HSTL includes a bias control transistor to absorb current leaking through the base-collector capacitance of the drive transistor and maintain the base voltage on the drive transistor. The bias control transistor is biased by a series network coupled between a base of the bias control transistor and ground, which keeps the bias control transistor at a bias near its turn-on bias, with a feedback capacitor coupled between the output and the base of the bias control transistor to turn on the bias control transistor when the output rises.

Abstract: The method and circuit arrangement and/or component prevents a change of a preset or set state of a control member and/or control unit (102) during a reset of controller or regulator (100) that controls this control member and/or control unit. The circuit arrangement and/or component (101) has at least one input and at least one output (TA) and is connected between at least one terminal (P) of a controller or regulator (100) and at least one input of the control member and/or control unit (102, 104). The at least one output (TA) of the circuit arrangement and/or component is connected for feedback to the at least one terminal (P) of the controller or regulator (100) and/or the at least one input of the circuit arrangement and/or the component (101), e.g. by means of feedback element (105), which may be a feedback resistor.

Abstract: The apparatus for converting a differential input voltage to two fully balanced output currents is achieved by providing a common mode control circuit of a simplified circuit construction to an operational transconductance amplifier. The apparatus includes an operational transconductance amplifier that is comprised of an OTA input section for converting two input voltages of the differential input voltage to a pair of interim output currents and an OTA output section for converting the interim output currents to the output currents, and a common mode controlling circuit for providing a control voltage to the OTA.

Abstract: A voltage follower and a semiconductor integrated circuit including the voltage follower. In the voltage follower, an output voltage Vout from a source follower output transistor 8 is negative fed back to a gate electrode of the source follower output transistor 8 via a differential amplifier 1. A clamp circuit 28 is provided which clamps the gate potential of the source follower transistor 8 by using a source and backgate potential of the source follower transistor 8, that is, potential at an output terminal 53, as a reference potential. Since the source-gate voltage of the source follower transistor 8 is clamped at a predetermined voltage and thus the maximum electric field applied to the gate oxide film is reduced, it becomes possible to use a MOS transistor having thin gate oxide film and short channel length and having high current drive ability, as a source follower transistor, even when a power supply voltage is high.

Abstract: A circuit arrangement which, in accordance with its mode of control, operates either as input circuit or as output circuit and includes a series connection with an inverter stage, a filter stage, a cross-current avoiding stage, a switching-on voltage reducing stage, a switch stage, an output driver stage, and a Miller feedback stage, which are configured in the mode of operation as an output circuit, and parallel thereto a Schmitt trigger and an analog switch that can become effective in the mode of operation as input circuit.

Abstract: A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

Abstract: In the current limiting circuit, which is provided with: the D/A converter 2A to output the voltage signal to supply the power source onto the load 11; reversal amplifier circuit to amplify the voltage signal; capacitor 10 to absorb the fluctuation of the power source supplied onto the load 11; operational amplifier 4B to set the amplification factor of the reversal amplifier circuit; transistor 5; and resistor 3E, the current detection circuit 7 detects the current value to be inputted into the load 11, and according to the detected current value, calculates the voltage at the current detection position, and the CPU 1 sets the predetermined voltage, the comparing circuit 8 compares the setting voltage value to the calculated voltage value, and according to the comparison result, by ON/OFF-controlling the switch 9, the setting of the amplification factor of the reversal amplifier is changed.

Abstract: The present invention makes it possible to prevent feedback loops from causing oscillations in clamp circuits. When a video signal is input through a capacitor into a first inverting input terminal of an operational amplifier, the output terminal tends to reach a high level because the potential of the first inverting input terminal is lower than the potential of the non-inverting input terminal to which the black level reference signal is input. Thereby the NPN transistor whose base is connected to the output terminal is turned on to charge the capacitor. When the charging of the capacitor approaches completion, the potential of the first inverting input terminal becomes higher than the potential of the second inverting input terminal.

Abstract: A boost level clamping circuit and a method for clamping a boosted wordline voltage from a booster circuit used in a semiconductor memory device is provided which is power supply and process corner independent. The clamping circuit is formed of a plurality of parallel-connected clamp stages connected to the boosted wordline voltage from the booster circuit. Each of the plurality of clamp stages serves to clamp the boosted wordline voltage at different predetermined levels. Each of the clamp stages is formed of a sampling circuit, a comparator circuit, a pulse generator circuit, and a pull-down circuit.

Abstract: An automatic threshold level control circuit is provided which is capable of controlling the threshold level without causing the DUTY deterioration. The automatic threshold level control circuit comprises a timing detecting circuit 110a, used for preserving the peak voltage values of each input signals for input signals (ATCIN+ and ATCIN−) and for outputting the preserved voltage values as a reference signal for the threshold level of each input signal, and the automatic threshold level control circuit comprises a pair of peak value detecting circuits PD1 (62) and PD2 (64) for resetting the held voltage values into reference voltages Vref1 and Vref2 by reset signals PD1RST and PD1RST; and the timing detecting circuit 110a for detecting a predetermined timing and outputting the reset signals PD1RST and PD2RST to the peak value detecting circuits PD1 and PD2 for releasing the reset state in accordance with the detected timing.

Abstract: A method and circuit for automatically centering the control loop bias current by sensing and “memorizing” the total steady state bias current used by the function block (VGA or VCO) through the use of both digital and analog memory elements. The present invention uses an auto-centering, high-impedance current driver to supply the bias current. This current driver cancels out offset currents by exploiting the high output impedance nature of a CMOS current driver using cascoded or resistor source de-generated FET devices.

Abstract: An analog-digital converter includes a .DELTA..SIGMA. modulator, a digital filter, a high-pass filter and a multiplier which are connected in series. Analog input is converted into serial-bit strings by the .DELTA..SIGMA. modulator, for which gain `1/A` is set. The digital filter extracts low-frequency components, corresponding to the analog input, from the serial-bit strings, so the low-frequency components are converted into parallel-bit digital data. The high-pass filter removes DC offset component from output of the digital filter; and then, output thereof is multiplied by scaling gain `A` by the multiplier so that digital output is produced. The .DELTA..SIGMA. modulator includes at least three switched-capacitor integrators and a one-bit quantizer, which are connected in series, as well as a one-sample delay circuit. One-bit output, produced by the one-bit quantizer, is delayed by the one-sample delay circuit, whose output is delivered to each switched-capacitor integrator.

Abstract: A wideband level shift circuit (200) used with low voltage ECL or CML topologies includes a sub-Vbe voltage reference (201) whose output voltage is offset some fraction of a diode voltage drop below a supply voltage, where the fraction is held at a constant value as the diode voltage varies with temperature. A comparator circuit (203) is attached to the reference voltage circuit (201) as well as to a current sourcing transistor and differential buffer circuit (205). The comparator circuit (203) maintains the DC potential at the output of a current sourcing transistor so that the common-mode DC level of the output signal from a differential buffer is shifted down by a fraction of a diode drop from the common-mode DC level of a wideband AC input signal. The shift circuit (200) offers the advantages of a fraction of a diode DC voltage drop with little loss of AC signal bandwidth for circuits operating from low supply voltages.

Abstract: A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

Abstract: A clamping circuit (100) is provided for controlling an external switch, using a control signal, in response to monitoring a voltage at a first node. When the voltage at the first node exceeds a certain voltage, the clamping circuit (100) closes the external switch to complete a current path to reduce the voltage at the first node. The clamping circuit (100) includes a voltage divider circuit, a first device, a second device, a current mirror circuit, and a switch. The voltage divider circuit, which may be implemented using a resistor (30) and a resistor (32), is coupled between the first node and a fourth node and generates a divider voltage at a third node that is proportional to the voltage at the first node. The first device and the second device may be implemented using a first bipolar junction transistor (38) and a second bipolar junction transistor (40), respectively.

Abstract: A low power current-to-frequency converter circuit provides an output frequency signal F.sub.OUT having a frequency that varies as a function of a low level analog input current signal. The analog input current signal is typically generated by an implantable sensor element, designed to sense a particular substance or parameter within body tissue or fluids to which the sensor is exposed, with the magnitude of the analog signal providing a measure of the sensed substance or parameter. Conversion of the low level analog current to the output frequency signal facilitates transmission of the data signal over a shared data bus and other digital processing of the data signal.

Abstract: This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings.

Abstract: A high-speed/high-slew-rate tri-modal all bipolar buffer/switch includes a unity-gain amplifier, a voltage source, and a maximum level detector and a minimum level detector adjusting a current source to sink or source current as required to quickly make the output voltage of the switch equal to the input voltage of the switch. The maximum level detector and the minimum level detector compare the output voltage to the input voltage. If the output voltage does not equal the input voltage, the current source acts as either a sink or source to make the output voltage equal the input voltage. In addition, the voltage switch holds a constant d.c. voltage at the output of the switch when the switch is powered down.

Abstract: An automatic gain control circuit in the feedback path for a laser wavelength control circuit is described herein. This gain control circuit automatically adjusts the amplification of the analog signals output from a photodetector array, where the array detects a fringe pattern created by a laser beam. Another feature of the preferred embodiment feedback circuit is the automatic setting of a DC offset voltage that compensates for errors in the feedback path and enables an accurate determination of a dark level signal in the fringe pattern signal. This dark level signal provides a reference for measuring the magnitude of the fringe pattern signal. Varying photodetector outputs may now be more accurately measured. The preferred embodiment feedback circuit also employs a very fast amplifier anti-saturation circuit using LED's connected in a clamp circuit.

Abstract: Magnetoresistive elements are disposed facing a gear to form a sensor for detecting rotation of the gear. The signal output from MRE sensor is an alternating amplitude signal. An operational amplifier has a differential gain exceeding its operational limit relative to the amplitude value of the sensor signal, and it amplifies and outputs the difference between the sensor signal and a reference voltage. Comparators judge whether an output of the operational amplifier is within a predetermined amplitude range relative to the amplitude center thereof. When the op-amp output deviates from the predetermined amplitude range, transistors either charge or discharge a capacitor, so that the reference voltage can be changed closer to the output of the operational amplifier. Another comparator compares the output signal of the operational amplifier with a threshold value to output a binary-valued signal.

Abstract: An object is to provide a semiconductor device having an internal power supply circuit capable of supplying stable internal power supply voltage while not increasing layout area. A differential amplifying circuit in a voltage down converter controls potential level V.sub.OUT of the drain of transistor P14 such that it attains the reference potential V.sub.REF. If the potential V.sub.OUT increases, the gate potential of transistor N12 increases because of coupling function of a capacitance C2, and the transistor is rendered conductive. Thus the potential level V.sub.OUT is pulled down. By contrast, if the potential level V.sub.OUT lowers, transistor P12 is rendered conductive, and the potential level V.sub.OUT is pulled up.

Abstract: A sense and protection circuit against short circuits for digital outputs, comprising a logic gating circuit of the exclusive OR type (EX1) which has a first input terminal connected to a signal input node (IN) and an output terminal which is connected to an input terminal of a signal level shifter output stage (B). A second logic gating circuit of the exclusive OR type (EX2) has a first input terminal connected to the input node (IN) and a second input terminal connected, through an inverting circuit (IN1), to an output terminal (OUT) of the output stage (B). A second input terminal of the first logic gate circuit is coupled to an output terminal of the second logic gate circuit through a comparator circuit (SCH1) and a delay circuit means (C,R,D).

Abstract: Circuitry for controlling load current, in accordance with the present invention, utilizes a load drive transistor configuration operable to provide a first load current path having a first fraction of load current flowing therethrough and a second load current path having a second smaller fraction of load current flowing therethrough. The circuit includes a sense resistor associated with the load drive transistor to detect various load current threshold values. In order to reduce debiasing effects of the sense resistor upon the second load current path of the load drive transistor, a compensation resistor is provided between drive inputs associated with each of the two current paths. The compensation resistor has a compensation voltage established thereacross which is operable to negate the debiasing effect of the sense resistor on the load driving device.

Abstract: An op amp clamp for charging or discharging a capacitor prevents the voltage on the capacitor from going beyond a reference voltage determined by a reference clamp voltage applied to an input of a differential amplifier. The second input of the differential amplifier is connected to the capacitor. The output of the differential amplifier is provided in a feedback loop to the capacitor. The feedback loop includes a charging circuit or a discharging circuit depending upon the function of the op amp clamp. The feedback loop may be arranged with a current mirror in which current generated by the output of the differential amplifier is mirrored in the charging or discharging circuit. A signal to activate charging or discharging is applied at the output of the differential amplifier to activate or deactivate the current mirror.

Abstract: A control system using pulse width modulation, current-mode control to regulate a flyback converter for small input currents. The control system generates a ramp voltage indicative of an input current of the converter with an added bias to overcome the effects of switching noise attributable to parasitic elements in the converter. The ramp voltage is compared with an error voltage is order to obtain the pulse width modulated on-time of a primary switch. Thus, the control system maintains control for small duty cycles of the primary switch by having a control region immune to switching noise.

Abstract: An electronic clamping circuit is provided. In one preferred embodiment, the clamping circuit includes a pair of diodes connected in series, both having the same bias, which are shunted across a feedback path of a transimpedance amplifier circuit. A capacitor is connected to a node in-between the diodes and a potential (e.g., ground). The arrangement of the diodes and capacitor serve to keep the amplifier circuit's operation within its linear limits without severely degrading its bandwidth.

Abstract: A power amplifier circuit includes a first field effect transistor power amplifier having a gate; a gate voltage supply for supplying a gate voltage to the gate of the first field effect transistor; and a gate voltage control including a second field effect transistor which has the same threshold voltage as the first field effect transistor. The gate voltage control receives, as an input voltage, the gate voltage output from the gate voltage supply, and increases the gate voltage when the gate voltage is lower than the threshold voltage of the first field effect transistor, preventing the first field effect transistor from being pinched off. Therefore, when the pinch-off voltage of the first field effect transistor varies or when the voltage supplied from the gate voltage supply varies, unwanted pinch-off of the first field effect transistor is avoided in the lower power consumption state so that the stability of the circuit is improved.

Abstract: An amplifying circuit has an amplifying section including an operational amplifier for receiving an input signal and a power transistor for receiving the output of the operational amplifier to drive a load resistor. The amplifying circuit further has an over-current protective section including a current detection transistor receiving the output signal of the operational amplifier and a comparator comparing the output voltage of the current detection transistor and a reference voltage to supply a control signal to the operational amplifier when the output level representing the load current for the load resistor exceeds a threshold. The source of the power transistor and the source of the current detection transistor are maintained at the same potential by connecting both the sources or by providing a feedback section. A wide range of the voltage signal and an accurate threshold for the load current can be obtained.

Abstract: In a magnetic disk drive in which an analog signal having symmetrical positive and negative odd levels with respect to a zero-level is read out of a magnetic disk by a head, the read analog signal is processed by an AGC circuit and a low pass filter, the processed analog signal is converted into a digital signal by an A/D converter, and the digital signal is demodulated by a demodulator, a zero-level setting circuit for the A/D converter is comprised of: a reference voltage generator for the A/D converter; a zero-level error detector between the read signal and the reference voltage; an accumulator for accumulating the zero-level error from the zero-level error detector; and an equalizer for equalizing the zero-level of the A/D converter to the reference voltage in accordance to an output signal from the zero-level error accumulator. As a result, the conversion accuracy of the A/D converter is improved while employing a small number of bits.

Abstract: An apparatus for suppressing voltage transients across a first transistor is described. The first transistor has a first terminal, a second terminal, and a gate terminal, and is characterized by an avalanche breakdown voltage rating between the first and second terminals. The cathode of a first diode is coupled to the first terminal, the first diode having a reverse breakdown voltage which is less than the avalanche breakdown voltage rating. Gate driver circuitry is provided by which the gate terminal of the first transistor is coupled to the anode of the first diode. The gate driver circuitry provides a drive signal to the gate terminal of the first transistor, and comprises a plurality of bipolar transistors. Each bipolar transistor has an anode terminal (i.e., base terminal), a p-n junction, and a cathode terminal (i.e., emitter terminal). The anode terminal of each bipolar transistor is coupled to the anode of the first diode.

Abstract: An apparatus and method for performing adaptive power regulation for an integrated circuit. The present invention utilizes a voltage regulator circuit (16) to regulate the voltage provided to an integrated circuit core (12), and to thereby reduce the power consumption of the integrated circuit core (12). In one form, the voltage regulator circuit (16) utilizes two voltage converting mechanisms, namely an inductive converter (22) and a resistive converter (24). The inductive converter (22) and the resistive converter (24) supplement each other in order to supply the current required by integrated circuit core (12). All or a portion of voltage regulator (16) may be located on the same integrated circuit substrate as integrated circuit core (12).

Abstract: A current limit circuit (10) uses a reference current (28) with zero temperature coefficient. A feedback loop (18, 26, 22) maintains substantially equal V.sub.GS for first (22) and second (24) transistors. The reference current sets the current through the first transistor which therefore limits the current in the second transistor. The second transistor is a power device that supplies current to a squib detonation device (38) in automotive air bag application.

Abstract: An electronic clamping circuit is provided in one preferred embodiment, the clamping circuit includes a pair of series-connected diodes, both having the same bias, which are shunted across a feedback path of a transimpedance amplifier circuit. A capacitive element is connected to a node in-between the diodes and a potential (e.g., ground). The arrangement of the diodes and capacitive element serve to keep the amplifier circuit's operation within its linear limits without severely degrading its bandwidth.

Abstract: An object of the present invention is to provide a buffer circuit little sensitive to a deviation from a threshold voltage of each of transistors. In order to achieve the above object, the present invention provides a typical buffer circuit comprising the following components.

Abstract: In a magnetic disk drive in which an analog signal having symmetrical positive and negative odd levels with respect to a zero-level is read out of a magnetic disk by a head, the read analog signal is processed by an AGC circuit and a low pass filter, the proceed analog signal is converted into a digital signal by an A/D converter, and the digital signal is demodulated by a demodulator, a zero-level setting circuit for the A/D converter is comprised of: a reference voltage generator for the A/D converter; a zero-level error detector between the read signal and the reference voltage; an accumulator for accumulating the zero-level error from the zero-level error detector; and an equalizer for equalizing the zero-level of the A/D converter to the reference voltage in accordance to an output signal from the zero-level error accumulator. As a result, the conversion accuracy of the A/D converter is improved while employing a small number of bits.

Abstract: In a D.C. restoration circuit for a digital FM radio receiver, in which demodulated signals may be presented at the output of the demodulator as low-level differential signals superimposed on a variable D.C. level, the differential signal paths are capacitively coupled to the inputs of a comparator, and the voltage excursions at these inputs are clamped when the voltage between the inputs exceeds a predetermined value.

Abstract: A sample hold circuit comprises a first transistor having its base connected to an input terminal and its collector connected to a voltage supply terminal, series-connected first and second diodes having a cathode of the first diode connected to an emitter of the first transistor, a first constant current source having its one end connected to an anode of the second diode circuit and its other end connected to the voltage supply terminal, a first differential circuit including a first branch connected to the emitter of the first transistor and a second branch connected to the anode of the second diode, a third diode having its cathode connected to the anode of the second diode, a second transistor having its base connected to a connection node between the second diode and the third diode and its collector connected to the voltage supply terminal, a second differential circuit including a first branch connected to the voltage supply terminal and a second branch connected to an emitter of the second transistor,

Abstract: A BIMOS driver circuit and method in which a push-pull pair of PNP-NPN bipolar transistors replaces the middle CMOS inverter stages in a circuit for driving a capacitive load. The rise and fall times of the circuit are made symmetrical by feeding back driver circuit output to operate a feedback transistor which removes the base charge stored in a PNP transistor of the bipolar push-pull pair, and maintains low propagation delay.

Abstract: A differential amplifier and an NMOS transistor are provided corresponding to each load circuit. A positive input and a negative input of the differential amplifier are coupled to a first ground interconnection and a second ground interconnection, respectively. When the selected load circuit operates, the potential received by this load circuit rises by interconnection resistances of the first ground interconnection. However, the potential received by the de-selected load circuit is reduced due to the operation of its corresponding differential amplifier and transistor. As a result, a rise in the potential of the de-selected circuit caused by the operation of the selected circuit will be suppressed. The differential amplifier and transistor corresponding to the selected load circuit also operate to reduce the potential of the selected circuit, thereby to suppress the rise in such potential.

Abstract: An automatic offset control circuit comprises a differential output preamplifier having an offset adjustment function, further comprising an average detector, a peak detector, and a differential input amplifier. The average detector generates a reference voltage representing an average value of a positive output and a negative output of the preamplifier. The peak detector outputs a peak voltage representing a peak of the negative output of the preamplifier. The differential input amplifier compares the peak voltage with the reference voltage to output an offset adjustment signal to the preamplifier. The offset adjustment signal is obtained based on a difference between the reference voltage and the peak voltage. A bottom detector may be used instead of the peak detector, provided a bottom value is detected using the positive output of the preamplifier.

Abstract: A voltage clamping circuit is provided for clamping the input voltage to CMOS devices near the rail voltages so as to prevent forward biased junctions, minority carrier injection and crosstalk between voltage inputs. The voltage clamping circuit receives an input voltage and provides an output voltage within a rail-to-rail voltage range. The clamping circuit has a bias circuit with a PMOS device for providing a p-channel threshold drop to an upper rail voltage so as to generate an upper threshold bias voltage. The bias circuit also has an NMOS device for providing an n-channel threshold increase to a lower rail voltage so as to generate a lower threshold bias voltage. A first clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from rising above the upper rail voltage. A second clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from dropping below the lower rail voltage.

Abstract: A filter boost preattenuator provides controlled, rapid variable signal preattenuation at the input of a filter to optimally compensate for the absolute gain increase of the filter caused by increasing the high frequency boost level of the filter. The amplitude of the filter output exhibits very little change during boost variations that dynamically occur in applications such as data and servo signal recovery in disk drives. Using the present invention, disk space overhead needed to allow for readjustment of the automatic gain control system of a read/write channel is minimized. In the present invention, the feedforward signal provided from the variable gain boost circuit is applied to a feedback circuit and subtracted from the system input. The feedback forces a drop in the overall gain of the filter that increases with boost gain.

Abstract: A control circuit for controlling the power or bounce of an output driver circuit is disclosed. The control circuit can sense the output voltage and/or the bounce and then adjust the control node voltage of the output driver circuit accordingly. In addition, the output circuit can discharge the output node to a lower voltage level before turning on the output driver circuit.

Abstract: According to the present invention, an integrated regulator having an adjustable reset threshold is disclosed. The integrated regulator has the following elements contained within an integrated circuit device: a transistor, a voltage reference block, an internal resistive network, an operational amplifier which regulates the voltage output signal of the integrated regulator by regulating the base current of the transistor, and a comparator which senses and communicates to the user when the operational amplifier is unable to maintain the voltage output signal within an acceptable range of a desired value of the voltage output signal. External to the integrated circuit device is an external resistive network. When the reset output signal of the integrated regulator is equal to an active state, this is indicative that the operational amplifier has been unsuccessful in keeping the voltage output signal within the acceptable range of the desired value of the voltage output signal, i.e.

Abstract: A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit for driving the internal bus with a full CMOS-swing in one bus direction and with a reduced CMOS-swing in the other bus direction, a column address generation circuit for allowing sequentially addressed data to be accessed with the decoder delay being eliminated, and a circuit for re-synchronizing data from a source clock to a destination clock with reduced access latency penalty. Simultaneously writing data into multiple circuit modules significantly increases the write bandwidth of the memory. Also included are a dynamic base-address mapping into an address space, a read or write operation across multiple memory modules, a novel I/O bus format, and a protocol and test mode for testing redundant memory sub-arrays.

Abstract: An excitation stage having a predetermined number of semiconductor-based amplification modules parallel-connected at the input of a coupling device to couple the outputs of the amplification modules to the input of the transmission tube, as well as a diode-based limiter device positioned inside the coupling device to limit the pulses that short-circuit electrodes of the transmission tube appearing at the output of the coupling device.