Abstract: A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal.

Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.

Abstract: An arrangement for charge integration comprises an input (1) for the provision of a charge-dependent signal and an integrator (30) to integrate a signal present at its input. In addition, a coupling circuit (20) that can adopt at least two operating states is provided to couple the input (1) to the integrator (30) which has a temperature-dependent coupling characteristic. A correction circuit (10) that can be operated by a clock signal is coupled to the input (1) in order to transfer a quantity of charge, and has a temperature characteristic that is derived from the coupling characteristic of the coupling circuit (20).

Abstract: A neural recording system (100) and method (400) for neural encoding is provided. The system can include an ultra-low power neural encoder (120) for compressing spikes within a neural signal (110) to produce a pulse train (130) and wirelessly transmitting the pulse train to a spike sorter (140). Features of the neural signal can be encoded such that the timing between pulses and the number of pulses conveys features of the spike. The neural encoder can include an Integrate and Fire (IF) neuron 230 that performs spike detection and encodes at least one spike (112) of the neural signal. A leakiness aspect (232) and an adaptive aspect (337) can be included with the IF circuit for combining aspects of spike detection and spike sorting for suppressing noise, keeping power consumption low, and improving signal resolution.

Abstract: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

Abstract: In a signal detection method in which a correlated double sampling is performed, a signal-to-noise ratio of a detected signal is improved and the speed of signal detection is increased. When storing a baseline signal in the first holding circuit 32, low-pass filtering is performed by the first low-pass filter formed of the resistor R1, on-resistances of the switches S2, S4, and capacitor C1by switching ON the switches S2, S4. When storing a signal component in the second holding circuit 33, low-pass filtering is performed by the second low-pass filter formed of the resistor R2, on-resistance of the switch S5, and capacitor C2 by switching OFF the switch S3 and switching ON the switch S5. A time constant ?1 of the first low-pass filter, and a time constant ?2 of the second low-pass filter are set to values that satisfy the relationship of ?1<?2.

Abstract: A read circuit includes: an integration circuit section configured to perform an integral operation and whose input is connected to an integration node; and a bias circuit connected between a connection node to which a variable resistive element is connected and the integration node. The bias circuit includes: an integration transistor whose source and drain are respectively connected to the connection node and the integration node; an operational amplifier whose output is connected to a gate of the integration transistor, to whose first input a bias voltage is supplied, and whose second input is connected to the source of the integration transistor; and at least one diode element that is connected between the gate and source of the integration transistor and clips a gate-source voltage of the integration transistor.

Abstract: A read circuit includes: an integration circuit section configured to perform an integral operation and whose input is connected to an integration node; and a bias circuit connected between a connection node to which a variable resistive element is connected and the integration node. The bias circuit includes: an integration transistor whose source and drain are respectively connected to the connection node and the integration node; an operational amplifier whose output is connected to a gate of the integration transistor, to whose first input a bias voltage is supplied, and whose second input is connected to the source of the integration transistor; and a current switching circuit configured to provide or shut off a first current path. The first current path is a current path through which a current flowing between the drain and source of the integration transistor flows without passing through the connection node.

Abstract: An integrator is provided with protection against drift in the value of an integral during power save mode. An N-bit counter (12) is driven by the output of a comparator (11) to provide a digital count representation of the integral. The digital count is fed as an input to a current-steering digital-to-analog converter (14) which provides a current of corresponding analog magnitude to other circuitry, such as to an input stage of an error amplifier. The digital count is maintained during power save mode, preserving the integral value until resumption of normal operation.

Abstract: An ignitor comprising a circuit with a millisecond order time constant and with a minimum circuit size and area, which is capable of self-shutdown without leading to erroneous ignition upon detection of an abnormality. An ignitor 1 capable of self-shutdown upon detection of an abnormality comprises an abnormality detection circuit 12 whose rise output is applied to the gate of a self-shutdown MOSFET 33 via an integration circuit 33 comprised of a diode 8 and a capacitor 9. The gate voltage of IGBT 5a, which is a main-current switching device, can be decremented.

Abstract: An event time stamping system comprising a current source, an integrator comprising an input and an output, and configured to output a voltage proportional to the length of time the current source is coupled to the input, and one or more switches configured to couple the current source to the input of the integrator upon receipt of an event signal and configured to de-couple the current source from the input of the integrator upon receipt of a control trigger. The system further comprises a lock-out signal generator configured to generate a lock-out signal, and a controller coupled to the one or more switches, wherein the controller is configured to generate the control trigger based on the lock-out signal to ensure a minimum integration time.

Abstract: A circuit arrangement having a signal input configured to be supplied with a voltage signal; a first operational transconductance amplifier (OTA) having a voltage input that may be coupled to the signal input; at least one second OTA having a voltage input that may be coupled to the signal input; and at least one output capacitor which may be coupled to an output of the first OTA and to an output of the at least one second OTA, wherein an identical potential is set at the outputs of the first OTA and of the at least one second OTA.

Abstract: An integrating apparatus to lower the levels of audio outputs of an on-board audio system immediately upon cessation of a noise level such as when a vehicle comes to a stop. Audio signals from an audio source are amplified through attenuating means by an amplifying means to drive a loudspeaker. An output of a microphone for detecting a noise is inputted to each of two integrating circuits, which have different fall time constants. Outputs of the integrating circuits are applied to a selectively outputting means, which selectively derives an output having a lower level among the outputs of the integrating circuits, and which then supplies the output as a control signal to the attenuating means. When the level of noise is high such as when the vehicle is running, the control signal has a high level and the attenuating means reduces an attenuation. Thus, the output of the audio source may be heard without a drift of the audio signal level.

Abstract: A waveform shaping apparatus has a first integrating circuit 152, a second integrating circuit 153, and a first comparison circuit 154. The first and second integrated circuits 152 and 153 are connected in series with each other, and so operate that, when a voltage signal loner than a predetermined period and larger than a predetermined amplitude is fed to the first integrating circuit 152, the voltage signal is made higher than a first reference voltage and is then output to he second integrating circuit 153 and, when the voltage signal fed to the first integrating circuit 152 is shorter than the predetermined period, the voltage signal is made lower than the first reference voltage and is then outputted from the second integrating circuit 153. The first comparison circuit 154 compares a voltage contained in the voltage signal outputted from the second integrating circuit 153 with the first reference voltage, and outputs the comparison result.

Abstract: Methods and corresponding computer systems for characterizing signals and applications thereof are provided that use a functional depending on signal waveforms.

Abstract: Circuits (FIG. 1) that operate with power supplies (VDD) of less than 1 Volt are present. More particularly, circuits (FIG. 1) that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (M1A, M1B) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor (MOS) to bipolar junction transistors may implement the techniques presented herein.

Abstract: Correction of scintillation event data from a nuclear medicine imaging system for effects of pulse pile-up is carried out by separating event data packets into total energy and individual detector energy data packets, executing pile-up correction algorithms on each of the separated packets simultaneously using a pipeline processing architecture, and reassembling the corrected data packets into corrected scintillation event data packets. Pulse tail correction information for each individual detector is stored in a storage medium for a present event and immediately preceding event for which correction information exists, which allows individual detector correction information to be retrieved by using a look-up procedure, thereby enabling correction to be performed within a single processor cycle.

Abstract: Embodiments of the invention are generally directed to a high-speed differential energy difference integrator (EDI) for adaptive equalizers. In an embodiment, the EDI includes two differential full-wave rectifiers providing differential outputs that are cross-coupled to the inputs of an integration capacitor. In one embodiment, the active areas of the transistors of the differential full-wave rectifiers are substantially the same.

Abstract: A Gm/C tuning circuit. The Gm/C tuning circuit comprises an integrator, a transconductance amplifier, and a switched capacitor circuit. The integrator has a first input terminal, a second input terminal, and an output terminal providing a control voltage. The transconductance amplifier receives the control voltage and a first input voltage proportional to a reference voltage and has an output terminal coupled to the first input terminal the integrator. The switched capacitor circuit has an input receiving a second input voltage proportional to the reference voltage and an output coupled to the first input terminal of the integrator.

Abstract: A level detector includes a comparing circuit and an integrating circuit. The comparing circuit generates pulses each having its width corresponding to the length of a time period during which the strength of an input signal is higher than a reference value. Alternatively, the comparing circuit may generate pulses each having its width corresponding to the length of a time period during which the strength of the input signal is lower than the reference value. The comparing circuit successively outputs the pulses. The integrating circuit outputs a signal having its strength corresponding to an integration value obtained by temporally integrating the signal from the comparing circuit.

Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.

Abstract: Gain control for delta sigma analog-to-digital converter. A method is disclosed for driving the input of an integrator in a delta-sigma converter having an amplifier with a non-inverting input, an output and a positive input connected to a reference voltage and an integration capacitor connected between the non-inverting input and the output. An input voltage is sampled at a first rate onto an input sampling capacitor and then charge is dumped from the input sampling capacitor to the non-inverting input of the amplifier at a second time and at the first rate. A reference voltage is sampled onto a feedback sampling capacitor at substantially the first rate, and charge stored on the feedback sampling capacitor is dumped to the non-inverting input of the amplifier at a second rate different than the first rate.

Abstract: A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal.

Abstract: An integrated circuit (IC) resonator in which resonator parameters potentially affected by IC fabrication processes are correctable after fabrication. Resonance frequency tuning is effected by forming each feedback capacitor in a pair of integrator circuits to include a variable capacitance device, such as a varactor diode. A tuning signal is applied to the varactor diode to adjust the total capacitance value and, therefore, the resonance frequency. Similarly, the quality (Q) factor of the resonator is adjusted by providing a variable capacitance in an RC (resistance-capacitance) network coupling the output of one of the integrator circuits to the input of the other. The variable capacitance in the RC network permits adjustment of phase in the event that the integrator circuits do not provide a desired 180° total phase shift.

Abstract: An input interface circuit is provided which includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.

Abstract: An integrator circuit comprises an operational amplifier which has a transistor stage (1) with an input terminal (4) and an output terminal(3), a feedback capacitor (2) connected between the input terminal (4) and the output terminal (3), and a resistor (5) connected to the input terminal (4), and also has an additional circuit branch (20) comprising a second capacitor (22) and a second resistor (25) connected in series one with the other and connected between the output terminal (3) of the transistor stage (1) and voltage comprising the inverted input voltage to the integrator circuit. Preferably two additional circuit branches (320, 320?) are provided. One may be connected between the non-inverting or positive output terminal (33) of the transistor stage (1) and the inverting or negative input of the integrator. The other circuit may be connected between the negative output terminal (37) of the transistor stage (1) and the positive input of the integrator.

Abstract: An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Abstract: The invention relates to a method and an apparatus for producing a reference voltage that is applied to reference voltage inputs on receiver units in order to discriminate between the logic states of a data signal that is transmitted to a receiver end. A transmission device transmits, in addition to the data signal, a clock signal to the receiver end. The receiver end has, on the output side of a receiver unit that receives the clock signal, an integrator that integrates the clock signal and produces the reference voltage from the integrated value.

Abstract: A tunable current mode integrator for low-frequency continuous-time filters that requires a reduced amount of area when implemented in an integrated circuit (IC). The integrator includes input and output transistors, and cross-coupled current mirrors, integration capacitors, and operational transconductance amplifiers (OTAs) that form a feedback structure with the input transistors. Input currents are converted to small current swings within the OTAs, and are subsequently integrated by the capacitors. Resulting integrated voltages are converted to output currents by the output transistors.

Abstract: A complex switched-current bilinear integrator (100) is formed as a pair of cross coupled real bilinear integrators and has inputs (10, 11, 12, 13) and outputs (14, 15, 16, 17) for differential pairs of in-phase (1) and quadrature-phase (Q) signals and an arrangement of sample-and-hold circuits (20, 30, 40, 50) and coupled scaling circuits (70, 71, 80, 81). Dynamic element matching is used to reduce the effect of mismatch between scaling circuits by interchanging scaling circuits in different signal paths. In order to prevent cross-talk of signals between different signal paths, the change of a scaling circuit coupled to a sample-and-hold circuit is constrained to occur only at the beginning of a sampling operation by that sample-and-hold circuit.

Abstract: An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Abstract: An electronic integrator includes a compensation circuit which maintains an output of the integrator within a desired range. The compensation circuit includes a comparator which continuously compares the integrator output to a reference value, and a correction circuit which inputs a correction signal into the integrator when the reference value has been met or exceeded. The correction signal is preferably a fixed charge which lowers the voltage in an integrating capacitor by a predetermined amount, thereby ensuring that subsequent output of the integrator is less than the reference value. Through this compensation circuit, the integrator continuously operates without interruption, including without ever having to be reset. Further, the integrator is able to integrate both positive and negative input signals regardless of their magnitude.

Abstract: In a method and apparatus for controlling a dual-slope integrator circuit, a reset signal is provided to a reset input of the integrator circuit to maintain a reset state of an integrating capacitor for a predetermined reset time period in response to an original input signal. A delayed input signal is simultaneously generated by introducing a predetermined delay period into the original input signal, the delay period being longer than the reset time period. With reference to the original input signal and the delayed input signal, a trigger signal is provided to an integrator input of the integrator circuit for enabling charging operation of the integrating capacitor during a charging period that starts from the end of the reset time period and that terminates at a lagging edge of the delayed input signal.

Abstract: A leaky integrator is formed from a capacitor-free, non-linear delay resistor having a parasitic capacitance and a capacitor-free amplifier. The amplifier utilizes utilize the parasitic capacitance of the delay resistor to provide differing time constants for the rising and falling edges of an output signal produced in response to a pulsed input signal.

Abstract: An integration circuit includes an input node for receiving an input charge, an integrator having an input terminal coupled to the input node, an output terminal and a first charge storage device coupled between the input and output terminals, an intermediate node coupled between the input terminal and ground, a second charge storage device having a first terminal coupled to the intermediate node and a second terminal coupled to an output node of the integration circuit and an isolation device coupled between the integrator and the second charge storage device for selectively isolating the integrator from the second charge storage device. During a first phase of operation, the isolation device is activated and isolates the integrator from the second charge storage device, and the input charge received on the input terminal of the integrator is stored on the first charge storage device.

Abstract: A data receiver and data receiving method using signal integration and capable of reducing high-frequency noises generated upon high-speed data detection.

Abstract: A variable time constant circuit includes an inverting amplifier which has an amplifier input terminal and an amplifier output terminal connected to a signal output terminal and inverts a signal inputted to the amplifier input terminal, a first and a second resistor which are connected in series between the signal input terminal and the amplifier input terminal, a capacitor connected between the amplifier input terminal and the amplifier output terminal, a field effect transistor including a gate terminal connected to a junction point of the first and second resistors, a source terminal kept at a constant potential, and a drain terminal connected to the amplifier input terminal, the transistor flowing a current through the drain terminal according to a voltage between the gate terminal and the source terminal, and a control circuit which controls a voltage-current conversion ratio of the transistor according to a time constant control signal.

Abstract: A signal processing circuit outputs an output signal corresponding to a pulse width of an input pulse signal. This signal processing circuit comprises means for accumulating pulse widths of the input pulse signal for a predetermined period of time, and means for outputting the output signal corresponding to the accumulated pulse width. Each of these pulse widths has one of positive and negative polarities.

Abstract: An integrator with a reset mechanism comprises an integration capacitor and a replacement integration capacitor, wherein the integration capacitor is replaced with the replacement integration capacitor during a reset operation. A method of resetting an integrator comprises temporarily removing an integration capacitor and replacing the integration capacitor with a reset capacitor during a reset operation of the integrator. The method may further comprise temporarily removing the integration capacitor and replacing it with a reset capacitor multiple times during a single reset operation of the integrator.

Abstract: An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.

Abstract: A method and a device generate a reference voltage for discriminating between the logic states of a data signal received at a receiving end. A transmitting device transmits a continuous clock signal with a constant pulse period duration and a symmetrical sequence of low and high clock signal states in such a way that, at the receiver end, the clock signal has the same low and high voltage levels as the received data signal and it is subject to the same system-governed variations as the received data signal. An integrator at the receiver end receives and integrates the clock signal, and the integrated value becomes the reference voltage for the receiver unit.

Abstract: An integrator circuit comprises an operational amplifier having its inverting input coupled to an input resistor to which an input voltage is supplied, and its non-inverting input coupled to a reference potential. A capacitor and a first output resistor are coupled in series between the inverting input terminal and the output terminal, from which an output voltage is derived. A second output resistor is coupled between the reference potential and the connection of the capacitor and the first output resistor. The addition of the two output resistors makes it possible to easily realize a desired integration constant with the use of a larger fixed capacitor, thereby minimizing unwanted parasitic capacitor effects. The integration constant can be adjusted as necessary by making the output resistors variable.

Abstract: An electronic integrator includes a compensation circuit which maintains an output of the integrator within a desired range. The compensation circuit includes a comparator which continuously compares the integrator output to a reference value, and a correction circuit which inputs a correction signal into the integrator when the reference value has been met or exceeded. The correction signal is preferably a fixed charge which lowers the voltage in an integrating capacitor by a predetermined amount, thereby ensuring that subsequent output of the integrator is less than the reference value. Through this compensation circuit, the integrator continuously operates without interruption, including without ever having to be reset. Further, the integrator is able to integrate both positive and negative input signals regardless of their magnitude.

Abstract: A method of communicating between a memory and circuitry on an integrated circuit is disclosed. The method comprises converting a first input signal from the memory to a first differential output signal dependent upon the first input signal. The first input signal is a full swing signal. The first differential output signal is propagated to the circuitry using a pair of first signal lines. Finally, at the circuitry, the first differential output signal is converted into a first received signal, which is a full swing signal.

Abstract: A leaky integrator is formed from a capacitor-free, non-linear delay resistor having a parasitic capacitance and a capacitor-free amplifier. The amplifier utilizes utilize the parasitic capacitance of the delay resistor to provide differing time constants for the rising and falling edges of an output signal produced in response to a pulsed input signal.

Abstract: A multi-stage integrator achieves a relatively high small-signal gain, broad bandwidth, and very clean transient pulse response. Only simple inverters are used, making the design scalable to deep sub-micron with low supply voltages, a rail-to-rail output swing, and a relatively low output impedance and useful tolerance to capacitive loading. A high gain amplifier is coupled between an integrator input node and amplifier output node. A broadband transconductor is coupled between the integrator input node and integrator output node. A resistor connects the amplifier output node and the integrator output, while a capacitor is coupled from the integrator input to the amplifier output. The conductance of the resistor (the reciprocal of the resistance, or 1/R) is selected to be substantially equal to the transconductance gm of the transconductor. A method for achieving clean transient pulse response is also described.

Abstract: The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is integrated between a start time and an end time that are specified by a control signal. An integration period between the start time and the end time depends on the frequency of the data signal. The data item is assigned a logic data value based on the result of the integration. The input circuit has a comparator device, an integration device and a switching device. The data signal is first integrated in order to obtain an integration value. The comparator device compares the integration value with a prescribed threshold value. A logic data value is assigned to the data item based on the result of the comparison.

Abstract: A variable time constant integrator includes an amplifier configured to generate an output signal, a capacitor coupled to provide feedback to the amplifier, and a variable gain element coupled to the output of the amplifier and to the capacitor. The variable gain element is configured to provide the product of a gain and the output signal to the capacitor. The variable gain element is also configured to receive an indication of a new value of the gain and to responsively set the gain equal to the new value of the gain. Adjusting the gain of the variable gain element adjusts the integrator's time constant.

Abstract: An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.

Abstract: Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.