Abstract: Gamma cameras and positron (PET) cameras use scintillation detectors to detect radiation from the body. However, when the number of radiation particles that strike the detector is very high, the chance that signals from two or more individual particles will pile up in the detector (to produce one erroneous, larger signal) is high. This problem is common to all applications using scintillation detectors. The present invention discloses methods and apparatus to prevent and correct for this problem. Results from a circuit according to the present invention show at least a 10 fold improvement in the maximum detection-rate limit over the conventional method.

Abstract: In a circuit arrangement for discharging at least one circuit node, an input and at least one output connectible to the at least one circuit node are provided along with at least one controllable resistor, a capacitor and a diode. A first terminal of the controllable path of the controllable resistor is connected to the output. A second terminal of the controllable path of the controllable resistor is connected to the input. A terminal of the capacitor and a cathode of the diode are connected to a control terminal of the controllable resistor. An anode of the diode is connected to the input. The circuit arrangement requires a very small area in an integrated circuit and enables a very fast discharge of the circuit node.

Abstract: In integrators which integrate the analog photocurrent of a photodiode (PD), the amplification-bandwidth product is relatively small on account of the parallel parasitic capacitance (Cp) of the photodiode (PD). However, in a design with a switched capacitor (C1), the bandwidth and at the same time the DC amplification must be large, so as to assure the integrator function even at low frequencies. So as to fulfill both of these mutually contradictory requirements for large bandwidth and high DC amplification, a reference voltage (V1) is present at a voltage divider that includes a resistor (R2) and a circuit section (R1) connected in series thereto, as well as at the photodiode (PD). The connection point of the voltage divider is connected to the inverting input of the transconductance amplifier (V). In a preferred embodiment, the circuit section (R1) is realized as a switched capacitor (C1), and the resistance (R2) is realized as an MOS transistor (T1).

Abstract: A network line equalizer includes a transconductance-controlled, tunable single zero high-pass, filter that includes a single zero impedance circuit, and first and second MOS transistors that output differential currents based on differential input signals and the impedance of the single zero impedance circuit. The MOS transistors act as source followers to convert the differential input voltage signals to respective differential current signals. The single zero impedance circuit connects the first and second MOS transistors, and causes the first and second MOS transistors to output a corrected pair of differential signals based on the impedance. The impedance of the single zero IMPEDANCE circuit is implemented using CMOS transistors, enabling the impedance to be dynamically controlled by an external impedance controller.

Abstract: The present invention provides a long time constant integrator circuit as part of an integrated circuit. The integrator circuit is fully integrated on chip with no external capacitive or resistive components for enhancing the circuit's time constant. It achieves a −3 dB cut-off frequency of 1.6 Hz. The circuit is realisable on a very small area of silicon being formed by a bipolar process using npn transistors, resistive and capacitive elements. The integrator circuit comprises a transconductance stage as an input to an operational amplifier. The circuit design is fully differential and employs realisable resistors and capacitors.

Abstract: An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Abstract: A rectifying integrator of an input signal with full output dynamics, relative to a voltage reference intermediate with respect to the dynamics of the input signal, includes a first line of integration having at least one integrator for integrating that portion of the input signal that exceeds the voltage reference, and includes a hold capacitor coupled in cascade to the integrator. The rectifying integrator includes a second line of integration, identical to the first line of integration, for integrating that portion of the input signal that remains below the voltage reference. An adder output stage generates an output signal equal to the difference between the voltages existing on the hold capacitors of the first and second lines of integration.

Abstract: An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.

Abstract: Provided are integrator circuit topologies that enable continuous integration without reset of the integrator circuit. One such integrator circuit includes a first integrator and a second integrator, each of the two integrators having a non-inverting terminal. Each of the non-inverting terminals is connected to an input node to alternately receive an input current for continuous integrator circuit integration without integrator circuit reset. The inverting terminal of the second integrator can be connected to an inverting terminal of the first integrator. The non-inverting terminal of the second integrator can be connected to an output of the first integrator through a first capacitor, and an output of the second integrator can be connected to a non-inverting terminal of the first integrator through a second capacitor.

Abstract: An electrothermal integrator and audio frequency filter utilizing an electrothermal structure fabricated by way of a micro-machining process. An electrothermal structure is a structure in which there is thermal interaction between its electrical components. It is possible to implement an audio frequency filter by properly integrating electrothermal structures fabricated by micro-machining technology and electrical circuitry, because thermal response is generally slower than electrical response. It is possible to implement a variety of filters by way of forming a Gm-C integrator utilizing an electrothermal structure and using this basic block of Gm-C integrator in general circuitry to form filters.

Abstract: A high voltage output stage amplifier that maximizes the output voltage swing when the peak-to-peak output voltage signal is higher than the supply voltage used in the signal conditioning circuits of the amplifier. The amplifier allows the maximum peak-to-peak swing on the output stage by shifting the quiescent voltage of the output stage to the midpoint of the output supply voltage. The shift is accomplished by tapping an offset current at the input of the error integrating stage of the amplifier proportional to the difference in the two power supply voltages.

Abstract: A signal processing circuit outputs an output signal corresponding to a pulse width of an input pulse signal. This signal processing circuit comprises integrating means for integrating pulse widths of the input pulse signal for a predetermined period of time, and outputting means for outputting the output signal corresponding to the pulse widths integrated by the integrating means. Each of these pulse widths has one of positive and negative polarities.

Abstract: In a frequency-voltage conversion circuit, integrating means gives a predetermined slope for rising or falling of a rectangular pulse signal. First comparing means compares an output value of the integrating means with a threshold value, and produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal. Storing means stores and retains the threshold value. Smoothing means smooths the pulse signal line, and produces a voltage value corresponding to the frequency of the rectangular pulse signal. Second comparing means compares the voltage value with a reference voltage, and charges and discharges electric charge for the storing means on the basis of the comparison result.

Abstract: The invention relates to a computer tomograph provided with a charge-integrating read amplifier having a plurality of gain factors for a data acquisition system as well as a control circuit for the gain factor. In order to avoid noise in addition to the shot noise in computer tomographs of this kind and also to avoid degrading of the DQE (Detection Quantum Efficiency), according to the invention it is proposed that the control circuit automatically selects the gain factor in dependence on the expected integrated input signal of the next frame, the expectation being based on the maximum possible relative variation of the integrated input signal between two successive frames.

Abstract: A noise reduction circuit useful as a clock restoration circuit includes a DC removal circuit for removing a DC level from an input pulse train, an integrator for integrating the input pulse train after a DC level has been removed, a comparator for comparing the integrator output with a threshold value (Vmp) to detect for a missing pulse, a pulse generator inserting into the input pulse train an additional pulse delayed with respect to any missing pulse, and an output circuit for generating an output pulse train from the integrator output.

Abstract: A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a scounter.

Abstract: An exemplary electronic circuit of the present include first and second buffers 34 and 38, which are preferably unity gain buffers. A first switch 36 (e.g., a NMOS transistor or a CMOS transmission gate) is coupled between the output of the first buffer 34 and the first terminal of a capacitor 40. The input of the second buffer 38 is also coupled to the first terminal of the capacitor 40. A second switch 42 is coupled between the second terminal of the capacitor 40 and a first voltage node Va and a third switch 44 is coupled between the second terminal of the capacitor 40 and a second voltage node Vb. This circuit can be used as an integrator in a number of applications.

Abstract: An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Abstract: An integrator circuit having a relatively large RC time constant includes a resistive element implemented with a field effect transistor operated in a sub-threshold mode. The size of the field effect transistor is selected, in addition to the sub-threshold gate voltage, to achieve a desired resistance value in a small area and without using bipolar devices. A differential integrator circuit includes two field effect transistors operated in a sub-threshold mode, with a capacitor connected between the output terminals of the two field effect transistors. A bulk drive circuit can be optionally used to reduce high frequency in the bulk.

Abstract: An integrated circuit voltage ramp generator is presented. The circuit includes at least one operational amplifier having a non-inverting input terminal connected to a voltage reference, and having an output terminal coupled in a feedback relationship to an output terminal of the generator circuit. The ramp voltage generator further includes a first storage capacitance connected between the non-inverting input terminal of the operational amplifier and a ground reference, which is loaded by means of a second pumping capacitance connected in parallel to the first capacitance. The pumping and voltage generation is and controlled by a series of passgates coupled to clock signals.

Abstract: A switched input circuit structure of the type which includes an input terminal receiving an input voltage and an output terminal connected to an input capacitor. An operational amplifier is included having a non-inverting terminal connected to a ground reference terminal, an inverting input terminal, and an output terminal feedback connected to the inverting input terminal and held in a virtual ground condition by a parallel of first and second charge paths which are connected between the input terminal of the switched input circuit structure and the inverting input terminal of the operational amplifier and connected to the supply voltage reference and the ground reference, respectively.

Abstract: An integration circuit is DC-coupled with a photomultiplier to convert a current signal output from the photomultiplier, to a voltage signal. The voltage signal converted by the integration circuit is logarithmically compressed with a logarithmic conversion circuit. An offset compensation circuit is provided for reducing an offset voltage that could occur because of charge injection in the integral action of the integration circuit.

Abstract: A low-pass filter circuit includes: a first compound transistor device (22) and (24) coupled between an input node (30) and an output node (32); a first transistor (20) coupled to the input node (30), a gate of the first transistor (20) is coupled to a drain of the first transistor (20); a second compound transistor device (36) and (38) coupled between a gate of the first compound transistor device (22) and (24) and the gate of the first transistor (20); a second transistor (34) coupled to the first transistor (20) and having a gate coupled to a gate of the second compound transistor device (36) and (38), the gate of the second transistor (34) is coupled to a drain of the second transistor (34); a current source (26) coupled to the drain of the second transistor (34); a first capacitor (C1) coupled to the output node (32); and a second capacitor (C2) coupled to the gate of the first compound transistor device (22) and (24).

Abstract: A switched capacitor circuit is described that uses two switchable operational amplifiers that operate in parallel and in alternate clock phases. In a preferred embodiment of the invention, the two operational amplifiers may be implemented by a single two-stage operational amplifier having a common input stage and two switchable output pairs. The novel switched capacitor circuit may be used in any application that uses a conventional switched capacitor circuit, such as an integrator and a filter means.

Abstract: Gamma cameras and positron (PET) cameras use scintillation detectors to detect radiation from the body. However, when the number of radiation particles that strike the detector is very high, the chance that signals from two or more individual particles will pile up in the detector (to produce one erroneous, larger signal) is high. This problem is common to all applications using scintillation detectors. The present invention discloses methods and apparatus to prevent and correct for this problem. Results from a circuit according to the present invention show at least a 10 fold improvement in the maximum detection-rate limit over the conventional method.

Abstract: A tunable integrator circuit having a main amplifier with an input resistor R and a feedback capacitor C and a tuning amplifier having a variable gain k between the output of the main amplifier and the feedback capacitor. The circuit has an effective capacitance of kC. Thus the integrator can be tuned to compensate for temperature and processing variations of the RC product by adjusting the gain of the tuning amplifier. The tuning amplifier can also be used to multiply the effective capacitance of the filter, kC, by increasing the gain k of the tuning amplifier beyond that needed to compensate for RC variations, thus reducing the area required for on-chip capacitances while maintaining a constant resistance. The circuit can be used independently or in conjunction with a capacitor array.

Abstract: A system and method, wherein the dielectric absorption of a capacitor is cancelled by a compensating circuit. One embodiment uses a compensation circuit comprising a compensating capacitor with substantially identical characteristics as the capacitor to be compensated in an integrator circuit. The effects of the dielectric absorption of the capacitor in the integrator circuit are reduced or eliminated because the dielectric absorption of the compensating capacitor cancels the dielectric absorption of the capacitor in the integrator circuit. Another embodiment uses compensation circuitry to reduce or eliminate the effects of dielectric absorption in any particular capacitor. The compensation capacitor in the compensation circuitry has a higher rate of dielectric absorption and a lower capacitance value than the capacitor whose dielectric absorption effects are to be reduced or eliminated.

Abstract: A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a counter.

Abstract: A circuit is designed with a first transconductor circuit (903) with a first input terminal (901) coupled to receive a voltage signal, a second input terminal (1017) coupled to receive a control signal and an output terminal. The first transconductor circuit has a gain responsive to the control signal. A first integrator circuit (905) has an input terminal coupled to the first transconductor circuit output terminal and has an output terminal. A second transconductor circuit (909) has an input terminal coupled to the first integrator circuit output terminal and an output terminal. A second integrator circuit (911) has an input terminal coupled to the second transconductor circuit output terminal and has an output terminal.

Abstract: A perfect integrator emulator includes a first multiplier multiplying an input with a first constant, KNEW, and generating a scaled input, a summer summing the scaled input with a previously generated scaled output and generating an accumulated output, a delay adding a predetermined amount of delay to the accumulated output and generating a delayed output, a second multiplier multiplying the delayed output with a second constant, KOLD, and generating the scaled output. The constants KNEW and KOLD are chosen such that the accumulated output emulates a perfect integrator's relative weighting, and saturation protection is guaranteed.

Abstract: A perfect integrator emulator includes a first multiplier multiplying an input with a first constant, KNEW, and generating a scaled input, a summer summing the scaled input with a previously generated scaled output and generating an accumulated output, a delay adding a predetermined amount of delay to the accumulated output and generating a delayed output, a second multiplier multiplying the delayed output with a second constant, KOLD, and generating the scaled output. The constants KNEW and KOLD are chosen such that the accumulated output emulates a perfect integrator's relative weighting, and saturation protection is guaranteed.

Abstract: An offset correction circuit containing an integrator is provided between an output of a first DC amplifier and an input of a second DC amplifier, and the integrator corrects not only an offset error caused by an input signal in the first DC amplifier, but also an offset error caused by an input signal in the second DC amplifier. Thus, the effect of the offset error proportional to the integral value of the input signal strength, occurring depending on the temperature stability or power supply voltage variation rate resulting from the input signal in the two DC amplifiers can be canceled.

Abstract: A polyphase filter passes a desired frequency and attenuates an image frequency in many communication systems. The invention is an error correction circuit that compensates the polyphase filter for low open loop gain operational amplifiers. When multiple polyphase filters are used in communication circuits on a single integrated circuit (IC), the open loop gain of the operational amplifiers is limited by the IC's ability to dissipate power. The error correction circuit reduces the dependency of the polyphase filter performance on the low open loop gain of its operational amplifiers and hence, on temperature and IC process parameters.

Abstract: The present invention provides a peak and bottom detecting circuit including a current source for charging or discharging the capacitor, a switch for connecting the current source to the capacitor, a comparator for comparing a potential of a connection node between the switch and the capacitor, and a potential of an input signal with each other, and for turning the switch on/off in accordance with the result of the comparison, a buffer for buffering the potential of the connection node between the switch and the capacitor, and outputting an output signal, and a damper for comparing the potential of the output signal and the potential of the input signal and reducing the current allowed to flow from the current source as the potential difference becomes smaller.

Abstract: An integrator and a filter having offset compensated switched-opamp are implemented in the present invention. In the present invention, offset voltages caused by amplifiers used in a integrator or a filter can be compensated and such circuits can be operated under a low power voltage.

Abstract: An integrator input circuit is disclosed.

Abstract: A delay circuit includes a reference voltage generation circuit for generating a reference voltage which changes to a prescribed voltage level during the operation of a comparison circuit, an RC delay stage for integrating an input signal, a comparison circuit for comparing an output signal from the RC delay stage and the reference voltage of the reference voltage generation circuit, and a logic circuit for buffering the output signal of the comparison circuit. Since the reference voltage is pulled to a prescribed voltage level only during a comparison operation, the reference voltage may accurately be maintained at the prescribed voltage level only when necessary free from the influence of other circuits and noises. A delay circuit with reduced current consumption which is capable of changing an output signal with fixed delay time independently of the influence of fluctuations of the power supply voltage and the input logical threshold value of a logic circuit in a succeeding stage is provided.

Abstract: A network line equalizer includes a transconductance-controlled, tunable single zero high pass filter having a parasitic pole, and a single zero, single pole low pass filter, that eliminates the necessity of feedback loops or operational amplifiers. The tunable single zero high-pass filter includes a single zero impedance circuit, and first and second MOS transistors that output differential currents based on differential input signals and the impedance of the single zero impedance circuit. The MOS transistors act as source followers to convert the differential input voltage signals to respective differential current signals. The single zero impedance circuit connects the first and second MOS transistors, and causes the first and second MOS transistors to output a filtered pair of differential signals based on the impedance. The impedance of the single zero impedance circuit is implemented using CMOS transistors, enabling the impedance to be dynamically controlled by an external impedance controller.

Abstract: A tunable integrator circuit having a main amplifier with an input resistor R and a feedback capacitor C and a tuning amplifier having a variable gain k between the output of the main amplifier and the feedback capacitor. The circuit has an effective capacitance of kC. Thus the integrator can be tuned to compensate for temperature and processing variations of the RC product by adjusting the gain of the tuning amplifier. The tuning amplifier can also be used to multiply the effective capacitance of the filter, kC, by increasing the gain k of the tuning amplifier beyond that needed to compensate for RC variations, thus reducing the area required for on-chip capacitances while maintaining a constant resistance. The circuit can be used independently or in conjunction with a capacitor array.

Abstract: In systems embodying the invention, circuitry responsive to first and second, complementary, input signals controls the application of the input signals to a positive signal integrator and to a negative signal integrator. When the amplitude of the input signals is greater than a predetermined value, the one of the two input signals which is positive relative to the other is applied to the positive signal integrator and the other one of the two input signals is applied to the negative signal integrator. When the amplitude of the input signals is smaller than a predetermined level, the circuitry causes the periodic application of the first input signal to the positive signal integrator and the second input signal to the negative signal integrator during one time interval, and the periodic application of the first input signal to the negative signal integrator and the second input signal to the positive signal integrator during a second, subsequent, time interval of similar duration as the one time interval.

Abstract: A converter includes at least two series coupled integrators, a comparator and a feedback element. The converter provides digital domain scaling so that an output signal is a scaled version of an input signal based on a feedback factor of the feedback element.

Abstract: A network of localizers determines relative locations in three-dimensional space to within 1 cm by cooperatively measuring propagation times of pseudorandom sequences of electromagnetic impulses. Ranging transmissions may include encoded digital information to increase accuracy. The propagation time is determined from a correlator circuit which provides an analog pseudo-autocorrelation function sampled at discrete time bins. The correlator has a number of integrators, each integrator providing a signal proportional to the time integral of the product of the expected pulse sequence delayed by one of the discrete time bins, and the non-delayed received antenna signal. With the impulses organized as doublets the sampled correlator output can vary considerably in shape depending on where the autocorrelation function peak falls in relation to the nearest bin. Using pattern recognition the time of arrival of the received signal can be determined to within a time much smaller than the separation between bins.

Abstract: A switched capacitor filter for applying a filter processing including an integration processing to input analog signals of plural channels on a time shared basis includes an integration sections for sequentially implementing the integration processing for the respective channels on a time shared basis, integrated value storage sections for storing integrated value signals representing results of the integration processing for the respective channels, switches for causing, each time the integration processing for the respective channels is interrupted, an integrated value signal representing result of the integration processing for the particular channel at the time of interruption to be stored in the integrated value storage sections and initializing the result of the integration processing by the integration section and, each time the integration processing for the respective channels is implemented, supplying the integrated value signal for the particular channel from the integrated value storage sections

Abstract: A wide-band, high-order, programmable video filter is implemented using transimpedance-based active integrators. An input voltage which may for instance represent a composite video signal is converted to a current in a linear manner using resistors and provided to a current amplifier at low impedance virtual ground nodes. The current is multiplied by a gain factor .beta..sub.R within the current amplifier and supplied to integrating capacitors connected in a feedback configuration around a high input impedance differential amplifier to establish an integrated differential voltage output. The transimpedance-based active integrators may be interconnected to realize wide-band, high-order video filters suitable for use in accordance with CCIR 601 standards. Input voltage swings are not restricted by a transistor's limited range of linear operation or voltage swing limitations of internal nodes but rather may allowed to swing as long as the bias currents sustain input current excursions.

Abstract: A system for laying out a capacitor array (400) implements a programmable capacitor (33-39) whose operation is controlled with a binary control word. A programmable capacitance is produced by coupling binary weighted, switchable capacitors (101-107) between terminals (51, 52) of the programmable capacitor. The capacitor array includes two or more unit capacitors (101, 103) of unequal areas. The other capacitors in the array are derived by interconnecting multiple capacitors that match one of the unit capacitors. Die area is reduced while accuracy is maintained by controlling the larger unit capacitor with the least significant bit of the binary control word whenever possible and using the smaller unit capacitor only as a trim capacitor.

Abstract: A staircase adaptive voltage generator circuit comprising a first capacitor connected between a first voltage reference and an output operational amplifier, through first and second switches, respectively. The terminals of the capacitor are also connected to a second voltage reference through third and fourth switches, respectively. A second capacitor, in series with a fifth switch, is connected in parallel to the first capacitor.

Abstract: A circuit configuration for smoothing an input voltage includes two input terminals for receiving the input voltage. A negative-feedback amplifier has two inputs and an output. A capacitor is connected to one of the inputs of the amplifier. An output terminal is connected to the output of the amplifier. A converter element has a first terminal connected to one of the input terminals, a second terminal connected to the one input of the amplifier and to the capacitor, and a third terminal connected to the output of the amplifier.

Abstract: This invention relates to an integrating circuit and finds application in high time constant low bandwidth feedback loop arrangements, e.g. in phase locked loop circuits. A well-known form of integrator is the Miller integrator, as used in Phase Lock Loop circuits (PLL) which are frequently used in communication systems, and are employed, for example, in clock extraction circuits in optical fiber receivers. With the advent of Passive Optical Networks (PON) becoming a means of providing fiber to the home very accurate timing information is required, to allow the outstation optical transmitter to send data within its designated time slot. The timing source at the base station needs to have a narrow jitter bandwidth of no more than, typically, 0.1 Hz, which cannot be realized with known phase lock loop circuits. The present invention seeks to provide an improved integrator which allows the fabrication of such timing circuits using standard components.

Abstract: In a photodetector amplifier scheme, the invention compensates for variations in photodetector quiescent current by sampling the amplifier output and subtracting a controllable current from the input to the amplifier. When a chopper or other modulator is used on the optical signal, the samples are taken periodically during the chopping cycle. This sampled signal is processed by a combination of gain and low pass filtering. The result of this processing controls a current source which subtracts a significant fraction of the average quiescent current from the total detector current. In a typical application, the amplifier is of the resettable current integrator type. In this case, the invention makes it possible to use smaller integration capacitors resulting in larger signals than if the quiescent current were not reduced by the operation of the invention. The gain, frequency response, and range of compensated quiescent currents and can be altered by changing timing signals.

Abstract: Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.