Abstract: Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.

Abstract: Electrical devices in a vehicle engine compartment are controlled from the vehicle passenger compartment over a serial data bus that extends between a relay controller located in the engine compartment and a body control module located in the passenger compartment and which receives commands from various passenger compartment devices. A serial data link passing through the firewall couples the body control module to the relay controller.

Abstract: In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle.

Abstract: An external micro projector comprises a micro projector body. A magnetic block is disposed in the micro projector body. The magnetic block is used for magnetically adhering with a magnetic adhesion device in a smartphone. A Pogo Pin connector is disposed on the micro projector body. The Pogo Pin connector is used for being electrically connected to the smartphone.

Abstract: A display device according to an embodiment of the present invention includes: a pixel including a first subpixel and a second subpixel; a first signal line connected to the first subpixel and transmitting a first signal; a second signal line connected to the second subpixel and transmitting a second signal; a third signal line intersecting the first and the second signal lines, connected to at least one of the first and the second subpixels, and transmitting a third signal; and a fourth signal line intersecting the first and the second signal lines and transmitting a fourth signal, wherein the first subpixel and the second subpixel are supplied with data voltages having different magnitude, and the data voltages applied to the first and the second subpixels are originated from a single image information.

Abstract: Some of the embodiments of the present disclosure provide a system comprising a functional block; a plurality of power sources, each of the plurality of power sources being maintained at a corresponding voltage; and a switching module having a plurality of switches, the switching module configured to supply power from at least one of the plurality of power sources to the functional block, each of the plurality of switches being controlled by a corresponding switching signal having a voltage value that is one of (i) a ground voltage and (ii) a high max voltage, the high max voltage corresponding to a highest voltage among the voltages of the plurality of power sources. Other embodiments are also described and claimed.

Abstract: An implantable lead connector configured for long term implantation and to electrically interconnect multiple medical devices and to channel electrical signals between said interconnected devices and a target organ, comprising: a first port adapted to receive a first signal suitable to stimulate a target tissue, a second port adapted to receive a second signal suitable to stimulate a target tissue, and a third port configured to connect to a target organ, wherein at least one of said first and second ports is configured to connect to a signal generator not integrated with said connector.

Abstract: A superconducting multi-bit digital mixer, designed using rapid single flux quantum (RSFQ) logic, for multiplying two independent digital streams, at least one of these comprising a plurality of parallel bit lines, wherein the output is also a similar plurality of bit lines. In a preferred embodiment, one of the digital streams represents a local oscillator signal, and the other digital stream digital radio frequency input from an analog-to-digital converter. The multi-bit mixer comprises an array of bit-slices, with the local oscillator signal generated using shift registers. This multi-bit mixer is suitable for an integrated circuit with application to a broadband digital radio frequency receiver, a digital correlation receiver, or a digital radio frequency transmitter. A synchronous pulse distribution network is used to ensure proper operation at data rates of 20 GHz or above.

Abstract: An A/D converter includes: an A/D converter circuit that causes a dissipation current (Idis) having dependence on an input voltage (Vin); and a counteracting current generation circuit controlled based on an output digital value (Dout) provided from the A/D converter circuit to generate a counteracting current (Icnt) that is a dissipation current for reducing the dependence of the dissipation current (Idis) on the input voltage.

Abstract: Disclosed herein is a device that includes a first buffer circuit coupled between a first power supply line and a data terminal and a second buffer circuit coupled between a second power supply line and the data terminal. First and second internal data signals complementary to each other are supplied to a level shifter, thereby third and fourth internal data signals complementary to each other are generated by changing amplitude values of the first and second internal data signals. The first and the second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

Abstract: A high-frequency switch module includes a switch element, high-frequency circuits, and a GND circuit. The switch element includes an antenna port, switch ports, and an FET switch. The FET switch switches connection between the switch ports and the antenna port. The high-frequency circuits connect any of the switch ports to a signal processing circuit. In the GND circuit, the switch port, which is not connected to the high-frequency circuits, is directly connected to a GND electrode.

Abstract: A semiconductor integrated circuit may include a plurality of fuse boxes, each suitable for selectively outputting a first input signal and a reverse input signal obtained by inverting the first input signal; and a first output signal generator suitable for selectively receiving the first input signal and the reverse input signal from the fuse boxes, and generating a first output signal by performing a logical combination operation on the received input signals, a second input signal, and a third input signal.

Abstract: An integrated circuit design protecting device includes a switch device and a non-volatile memory. The switch device includes M input ports, N output ports, N multiplexers, and S selection nodes. Each multiplexer of the N multiplexers includes I input nodes, an output node, and at least one selection node. The I input nodes are coupled to I input ports of the M input ports. The output node is coupled to an output port of the N output ports. The non-volatile memory is coupled to the S selection nodes of the switch device for providing selection codes to the switch device.

Abstract: Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by the selection circuit, a buffer having a buffer input disabling circuit operated to additionally disable a buffer input circuit when it is also disabled by a buffer selection circuit and a buffer disabling circuit operated to disable a buffer when the buffer input circuit is disabled by the buffer selection circuit. Any one or more of these features may be implemented to improve isolation performance. The architecture may be operated by a one-hot coding scheme.

Abstract: A voltage select circuit includes a plurality of first transfer elements configured to transfer respective operating voltages to a first output terminal, a transfer select circuit unit configured to output a first voltage necessary to transfer an operating voltage, selected from among the operating voltages, to at least one first transfer element in response to a plurality of enable signals, and a control circuit configured to boost the first voltage to a second voltage in response to the plurality of enable signals.

Abstract: A semiconductor device includes: a plurality of target lines to be driven; a plurality of target line drivers configured to drive the corresponding target lines in a logic level corresponding to a plurality of target line selection signals; a plurality of booster enable units configured to generate a booster enable signal by sensing whether a group of target lines that is obtained by grouping the target lines by a predetermined number is enabled or not; and a plurality of self-boosters configured to boost corresponding target lines by sensing levels of the corresponding target lines in response to the booster enable signal.

Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.

Abstract: A signal processor includes: a plurality of frequency converters which perform frequency conversion of input signals to output converted signals; and an output section which combines the converted signals output from the plurality of frequency converters and outputs a composite signal, wherein the plurality of frequency converters are formed in a one-chip semiconductor chip, and the plurality of frequency converters perform frequency conversion into converted signals in different frequency bands.

Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.

Abstract: In a driver, a charging module electrically charges the on-off control terminal of the switching element for turning on the switching element, and a limiting module performs a task of limiting a voltage at the on-off control terminal of the switching element by a predetermined voltage to thereby limit an increase of a current flowing between the input and output terminals of the switching element. A determining module determines whether the voltage at the on-off control terminal of the switching element deviates from the predetermined voltage while the limiting module is performing the limiting task. A correcting module corrects the voltage at the on-off control terminal of the switching element to be close to the predetermined voltage when it is determined that the voltage at the on-off control terminal of the switching element deviates from the predetermined voltage.

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract: A radio frequency (RF) switch includes a common port, a first port, and a second port, a first semiconductor switching element disposed in a first RF pathway between the common port and the first port, a second semiconductor switching element disposed in a second RF pathway between the common port and the second port, a first pair of direct current (DC) blocking capacitors disposed to isolate the first semiconductor switching element in the first RF pathway, and a second pair of DC blocking capacitors disposed to isolate the second semiconductor switching element in the second RF pathway. The respective pairs of DC blocking capacitors allow for different bias voltages to be applied to the respective RF pathways. A charge-discharge circuit may also be employed to decrease transient switching time of the RF switch.

Abstract: A radio frequency (RF) switch includes a common port, a first port, and a second port, a first semiconductor switching element disposed in a first RF pathway between the common port and the first port, a second semiconductor switching element disposed in a second RF pathway between the common port and the second port, a first pair of direct current (DC) blocking capacitors disposed to isolate the first semiconductor switching element in the first RF pathway, and a second pair of DC blocking capacitors disposed to isolate the second semiconductor switching element in the second RF pathway. The respective pairs of DC blocking capacitors allow for different bias voltages to be applied to the respective RF pathways. A charge-discharge circuit may also be employed to decrease transient switching time of the RF switch.

Abstract: The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.

Abstract: A system and method for communicating information through a powerline medium including at least three conductors, where the transmitter transmits at least two signals onto the powerline medium and the receiver receives one or more signals from the powerline medium. The transmitter adjusts the power transmitted into the powerline medium in order to set the adjusted transmit power to a predetermined level, e.g., a level that ensures power radiated from the powerline medium does not exceed a regulatory limit. The process of adjusting the transmit power may take into account a functional relationship between the transmitted power and properties of the channel.

Abstract: The present invention relates to a detection circuit (100) capable to detect a rectified phase-cut or sinusoidal wave-form using its duty cycle or average value and in response, to select the respective dim mode amongst the linear phase-cut and step-dimming. The circuit (100) receives the rectified waveform with its duty cycle, which is derived through a comparator (22, 24) and converted into a DC signal. The latter which is controlled by the duty cycle is then compared to a reference level (40) through another comparator (20) that, in response, supplies a signal controlling a switching device (30). The switching device (30) will be thus automatically connected either to one set signal level when the DC signal is greater than the reference level (40), namely when the circuit (100) detects a rectified sinusoidal waveform, or to the same level as the DC signal when the DC signal is less than the reference level (40), namely when the circuit (100) detects a rectified phase-cut waveform.

Abstract: A multi-channel semiconductor device comprises a plurality of buffer groups each comprising at least one output buffer, a plurality of pad groups each comprising at least one output pad, and a channel switching portion that controls connection between the plurality of buffer groups and the plurality of pad groups. One of the pad groups outputs an output signal of one of the buffer groups in a first operation mode and sequentially outputs output signals of all of the buffer groups in a second operation mode.

Abstract: A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock.

Abstract: A multiplexer includes a filter channelizer having at least two output filters, each output filter being coupled with a respective hybrid coupler. The multiplexer channelizes an input radio frequency (RF) band of electromagnetic energy into a set of output ports. Each hybrid coupler includes an input port (port 1), two output ports and an isolated port (port 4). Each output filter is coupled to a first one of the two output ports of a respective hybrid coupler, a second one of the two output ports being connected to an open stub microstrip transmission line. The respective hybrid coupler is coupled in a daisy chain, by way of port 1 and port 4, with one or more of the input of the multiplexer, and at least one other hybrid coupler. Advantageously, each output channel may include no more than one filter and no more than one hybrid coupler.

Abstract: Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.

Abstract: In the field of electronic technologies, a power supply selector and a power supply selection method are provided. The power supply selector includes: a first selection module, configured to select a power supply from multiple candidate power supplies; a control module, coupled to the first selection module, and configured to use the power supply selected by the first selection module as a power supply, and compare voltages of the multiple candidate power supplies to generate a control signal of each candidate power supply; and a second selection module, coupled to the control module, and configured to select a power supply for output in the multiple candidate power supplies under the control of the control signal of each candidate power supply. The technical solution is used to select a power supply from multiple candidate power supplies.

Abstract: A multiplexer and a dynamic bias switch thereof are provided. The dynamic bias switch includes a switch transistor and a dynamic bulk bias (DBB) unit. A first terminal and a second terminal of the switch transistor are respectively coupled to a first terminal and a second terminal of the dynamic bias switch. A bulk of the switch transistor is coupled to the DBB unit. The DBB unit selectively couples the first terminal or the second terminal of the switch transistor to the bulk of the switch transistor.

Abstract: A semiconductor device includes a plurality of oscillation signal generation units configured to output a plurality of oscillation signals whose cycles are adjusted according to a PN ratio, which is a size ratio of a PMOS transistor to an NMOS transistor, and a selection unit configured to selectively output the oscillation signals outputted from the plurality of oscillation signal generation units in response to a test mode signal.

Abstract: A switching circuit comprises a control and bias stage configured for receiving a first input voltage signal, a second input voltage signal and a selection signal and for generating therefrom a first bulk bias signal substantially equal to the first input voltage signal or to the second input voltage signal depending on the selection signal. The switching circuit further comprises a switching stage connected to the control and bias stage, including a transistor having a bulk terminal, and configured for receiving the bulk bias signal and generating an output signal having the first input voltage signal when the selection signal indicates the selection of the first input voltage signal or having the second input voltage signal when the selection signal indicates the selection of the second input voltage signal. The bulk bias signal is electrically coupled to the bulk terminal of the transistor.

Abstract: An apparatus includes an integrated circuit, which includes an input terminal, a second terminal to communicate with circuitry external to the integrated circuit, a multiplexer, a level shifter and a processor. The multiplexer is adapted to selectively couple the input terminal, the level shifter and the second output terminal together.

Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.

Abstract: A phase mixer includes a first driver configured to drive a first input signal to a mixing node with a driving force determined by a first setting value, a second driver configured to drive a second input signal to the mixing node with a driving force determined by a second setting value, and a slew rate control unit configured to control a slew rate at the mixing node.

Abstract: A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

Abstract: An apparatus is provided. The apparatus comprises backend circuitry and pairs of redundant input circuits. Each pair of redundant input circuits is configured to form a differential pair of transistors, and each redundant input circuit includes a multiplexer and a set of transistors. The multiplexer is coupled to the backend circuitry, and each transistor from the set of transistors has a first passive electrode, a second passive electrode, and a control electrode. The first passive electrode of each transistor from the set of transistors is coupled to the multiplexer, and the control electrodes from the set of transistors are coupled together.

Abstract: A method for digitizing at least a portion of a selected analog input signal of a plurality of analog input signals by using a multiplexer having a plurality of channels is provided. Each channel for the multiplexer is associated with at least one of the analog input signals and is associated with a pair of select signals, and wherein each channel includes a cell having an input terminal, an output terminal, and a boosted NMOS switch. According to the method, a first select signal from each pair of select signals is asserted to decouple the input and output terminals for each cell. A boost capacitor is also charged during the non-sampling or conversion phase while the first select signal from each pair of select signals is asserted.

Abstract: A multiplexer is provided. The multiplexer includes an output coupled to a complementary driving unit and a plurality of switch circuits. Each switch circuit includes a channel unit and two switches. The two switches respectively conduct two input signals to a channel end of the channel unit during different switch conduction periods, and the channel unit conducts the channel end to an output end during a channel conduction period. The switch conduction period of the first switch in the first switch circuit equals the switch conduction period of the second switch circuit, the switch conduction period of the second switch in the second switch circuit equals the switch conduction period of the first switch circuit, and the first and second switches are coupled to the same input signal.

Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: A high-frequency switch module includes a switch IC. An impedance matching circuit is connected to the antenna port of the switch IC. The impedance matching circuit includes a high-pass filter and a low-pass filter. The high-pass filter is disposed on the side of the antenna port, and is a substantially L-shaped circuit including a capacitor and an inductor. The antenna port is connected to the ground by the inductor.

Abstract: A multiplexer (MUX) circuit with balanced select line loading is provided. The MUX circuit includes a plurality of 2:1 MUX units coupled together in a multistage cascading arrangement, along with a selection module coupled to the MUX units. The MUX units are arranged in an initial MUX stage, at least one intermediate MUX stage coupled to and following the initial MUX stage, and a final MUX stage coupled to and following the at least one intermediate MUX stage. Each MUX unit is controlled with a respective select bit input value provided by the selection module. The selection module controls the operation of the MUX units in the initial MUX stage with a first plurality of different select bits, controls the operation of the MUX units in the at least one intermediate MUX stage with a second plurality of different select bits, and controls the operation of the final MUX stage with a devoted select bit.

Abstract: A current-limited differential entry stage compares an input signal to a reference voltage generated by a current-limited transistor or diode configuration. Current limiters comprise a D-mode feedback transistor having a gate-source junction. The D-mode transistor is not conducting between the source and the drain if a gate-source voltage is more negative than a negative threshold voltage, and conducting between the source and the drain, otherwise a feedback connection connects the source of the D-mode feedback transistor to its gate via a component that generates a voltage drop.

Abstract: A voltage select circuit includes a plurality of first transfer elements configured to transfer respective operating voltages to a first output terminal, a transfer select circuit unit configured to output a first voltage necessary to transfer an operating voltage, selected from among the operating voltages, to at least one first transfer element in response to a plurality of enable signals, and a control circuit configured to boost the first voltage to a second voltage in response to the plurality of enable signals.

Abstract: A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured.

Abstract: A voltage signal multiplexer includes a control and bias stage to generate at least one control and bias signal as a function of first and second selection signals and first and second input voltage signals. The multiplexer further comprises a switching stage configured to receive the at least one first control and bias signal and to generate therefrom, on an output terminal, an output signal having the first input voltage signal in response to the first and the second selection signals indicating the selection of the first input voltage signal, and having the second input voltage signal in response to the first and the second selection signals indicating the selection of the second input voltage signal. The switching stage is also configured to place the output terminal in a high-impedance condition in response to the first and the second selection signals indicating the high-impedance condition.

Abstract: A semiconductor device of the present invention is provided with a terminal for connecting a plurality of buses to the outside of the semiconductor device, a bus interface circuit for treating the plurality of buses as the same bus within the semiconductor device and a controller connected to the bus interface circuit.