Converging With Plural Inputs And Single Output Patents (Class 327/407)
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Patent number: 8390614Abstract: The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.Type: GrantFiled: March 8, 2010Date of Patent: March 5, 2013Assignee: Himax Technologies LimitedInventors: Wen-Teng Fan, Shih-Chun Lin
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Patent number: 8379771Abstract: A data receiver identifies an alignment symbol in a parallel data stream including encoded symbols, generates a bit order indicator indicating a bit order of the alignment symbol identified in the parallel data stream, and generates a symbol stream including the encoded symbols. Further, the data receiver decodes symbols in the symbol stream and generates a bit polarity indicator indicating a bit polarity of the parallel data stream based on the decoded symbols. Additionally, the data receiver generates a formatted symbol stream having a predetermined bit order and a predetermined bit polarity, based on the symbol stream, the bit order indicator, and the bit polarity indicator. In some embodiments, the data receives a serial data stream and generates the parallel data stream by deserializing data in the serial data stream.Type: GrantFiled: September 7, 2010Date of Patent: February 19, 2013Assignee: Integrated Device Technology, Inc.Inventors: Alex C. Reed, IV, Shriram Kulkarni
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Patent number: 8373357Abstract: An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.Type: GrantFiled: January 20, 2010Date of Patent: February 12, 2013Assignee: Microchip Technology IncorporatedInventors: Zeke R. Lundstrum, Keith Curtis, Sean Steedman, Vivien Delport, Jerrold S. Zdenek
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Publication number: 20130034199Abstract: To provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit includes a plurality of transistors each including an oxide semiconductor. In accordance with operations of the pulse signal output circuit, the threshold voltage of the transistor including an oxide semiconductor is changed. A shift register including the pulse signal output circuit is formed. A pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.Type: ApplicationFiled: July 30, 2012Publication date: February 7, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Kouhei Toyotaka
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Publication number: 20130015902Abstract: Disclosed herein is a resistor-sharing switching circuit including: a first switching device and a second switching device; and a resistor whose first end is connected to a control signal input end to which a control signal for controlling bodies of the first switching device and the second switching device is applied and whose second end is connected to the bodies of the first switching device and the second switching device.Type: ApplicationFiled: May 24, 2012Publication date: January 17, 2013Inventors: Yu Sin Kim, Sung Hwan Park
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Patent number: 8339176Abstract: A system and method for providing an accurate current reference using a low-power current source is disclosed. A preferred embodiment comprises a system comprises a first section and a second section. The first section comprises a first simple current reference, an accurate current reference, and a circuit that generates a digital error signal based upon a comparison of an output of the first simple current reference and an output of the accurate current reference. The second section comprises a second simple current reference providing a second reference current, an adjustment circuit providing an adjustment current based upon the digital error signal, and a circuit biased with current equivalent to a summation of the second reference current and the adjustment current. The first simple current reference and the second simple current reference may be equivalent circuits.Type: GrantFiled: May 30, 2008Date of Patent: December 25, 2012Assignee: Infineon Technologies AGInventor: Paolo Del Croce
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Publication number: 20120313688Abstract: A nonvolatile multiplexer circuit comprising an electric circuitry for selecting an output signal from a plurality of input signals based on select signals, the electric circuitry comprises at least one input terminal, at least one select terminal, and at least one output terminal; a high voltage source and low voltage source electrically coupled to a first and second source terminal, respectively of the electrical circuitry; at least one nonvolatile memory element comprising two stable logic states and electrically coupled to the output terminal at its first end and to an intermediate voltage source at its second end, wherein a logic state of the nonvolatile memory element is controlled by a bidirectional electrical current running through the memory element, and wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.Type: ApplicationFiled: June 3, 2012Publication date: December 13, 2012Inventors: Alexander M. Shukh, Tom A. Agan
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Patent number: 8325129Abstract: A liquid crystal display device includes a back light assembly that emits light on a liquid crystal panel; and an inverter that controls brightness of the light emitted from the back light assembly according to a difference between video data of at least three frames that are sequentially inputted to the liquid crystal panel.Type: GrantFiled: July 24, 2007Date of Patent: December 4, 2012Assignee: LG Display Co., Ltd.Inventor: Dong Kyoung Oh
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Patent number: 8310886Abstract: Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (??) modulator to operate at a low frequency without generating false lock and glitch noise.Type: GrantFiled: June 28, 2010Date of Patent: November 13, 2012Assignees: Samsung Electronics Co., Ltd., Tsinghua UniversityInventors: Woogeun Rhee, Xueyi Yu, Sung Cheol Shin, Zhihua Wang
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Patent number: 8299839Abstract: A capacitively and conductively coupled multiplexer (C3mux) circuit is described. This C3mux circuit includes a set of nonlinear coupling capacitors, such as metal-oxide-semiconductor (MOS) transistors, that can multiplex multiple input signals while minimizing the parasitic capacitance penalty associated with the ‘off’ paths. In particular, the capacitance of a given MOS transistor depends on whether its channel is present or absent. Furthermore, this channel is formed based on whether the gate-to-source and drain voltages for the MOS transistor are greater than the MOS transistor's threshold voltage. Note that the capacitance of the MOS transistors in the C3mux circuit is low for the unselected inputs. Consequently, the parasitic loading and the delay increase slowly as a function of the number of inputs. Moreover, the conductive feedback can be used to maintain a DC level of the input signals.Type: GrantFiled: January 12, 2009Date of Patent: October 30, 2012Assignee: Oracle America, Inc.Inventors: Robert J. Drost, Alex Chow, Robert D. Hopkins
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Publication number: 20120262219Abstract: A crosspoint switch device has a plurality of input ports each connected to a respective voltage source and a plurality of output ports each connected to a respective voltage source. A switch array selectively provides signal paths between the input ports and the output ports. The voltage sources are separate from one another.Type: ApplicationFiled: April 2, 2012Publication date: October 18, 2012Applicant: Mindspeed Technologies, Inc.Inventors: Poupak Khodabandeh, Merrick Brownlee
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Patent number: 8283968Abstract: An analog switch including at least one first MOS transistor capable of transferring a signal from a first terminal to a second terminal; a connection circuit for bringing a substrate terminal of the first transistor to a voltage which is a function of the voltages of the first and second terminals; and a circuit for controlling a control voltage of the first transistor with the signal.Type: GrantFiled: February 24, 2010Date of Patent: October 9, 2012Assignee: STMicroelectronics (Grenoble) SASInventor: Serge Ramet
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Publication number: 20120249214Abstract: A driver circuit of a semiconductor apparatus includes a driver and a control unit configured to vary a voltage level of a power supply terminal of the driver in response to a standby mode signal.Type: ApplicationFiled: December 21, 2011Publication date: October 4, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Myung Hwan LEE, Shin Ho CHU
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Publication number: 20120235729Abstract: An embodiment of an integrated circuit includes first and second pads, a supply conductor, and a selection circuit. The first pad is coupled to the supply conductor, and the selection circuit is configurable to couple the second pad to the supply conductor. For example, in a low-pin-count integrated circuit, one may select the second pad to be an input/output pad under normal-power conditions, and to be a supply pad under high-power conditions to reduce the voltage drop along the supply conductor.Type: ApplicationFiled: March 15, 2012Publication date: September 20, 2012Applicant: STMICROELECTRONICS S.R.L.Inventors: Giuseppe CONTI, Lorenzo LEONE
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Patent number: 8258853Abstract: A power switch circuit includes a voltage selecting circuit, an auxiliary transistor and a control circuit. The control circuit includes an inverter, or a first inverter and a second inverter forming a latch. The power switch circuit is capable of tracing a higher supply voltage and outputting the voltage level of the higher supply voltage without a voltage drop, so the junction leakage can be eliminated and the drive capability of the power switch circuit is ensured.Type: GrantFiled: June 14, 2010Date of Patent: September 4, 2012Assignee: eMemory Technology Inc.Inventor: Wei-Ming Ku
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Publication number: 20120218024Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.Type: ApplicationFiled: May 3, 2012Publication date: August 30, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jimmy G. Foster, SR., Kyu-Hyoun Kim
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Patent number: 8248103Abstract: An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.Type: GrantFiled: March 9, 2011Date of Patent: August 21, 2012Assignee: Hynix Semiconductor Inc.Inventors: Chang-Kyu Choi, Kyung-Hoon Kim
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Patent number: 8243003Abstract: Disclosed is a level shift circuit including a first level shift circuit that is connected between a first power supply terminal and first and second output terminals and receives first and second input signals from the first and second input terminals, respectively, and sets one of the first and second output terminals to a first voltage level, based on the first and second input signals; a second level shift circuit that is connected between a second power supply terminal and the first and second output terminals, and sets the other of the first and second terminals to a second voltage level; and a circuit that performs control to disconnect a current path in the second level shifter between the second power supply terminal and one of the first and second output terminals that is driven to the second voltage level at a time point when the first and second input signals are supplied to the first and second input terminals for a predetermined period including the time point when the first and second input sigType: GrantFiled: December 18, 2008Date of Patent: August 14, 2012Assignee: Renesas Electronics CorporationInventor: Hiroshi Tsuchi
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Patent number: 8228115Abstract: A biasing circuit of an integrated circuit includes a well of the integrated circuit and a plurality of transistors disposed in the well. The transistors couple the well to three signals providing corresponding voltages. The transistors bias the well to an extreme one of the corresponding voltages for the three signals.Type: GrantFiled: June 22, 2009Date of Patent: July 24, 2012Assignee: Xilinx, Inc.Inventor: Edward Cullen
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Publication number: 20120154016Abstract: According to one embodiment, a semiconductor switch includes a plurality of first switch elements, a second switch element, and a controller. The plurality of first switch elements are connected between a common terminal and each of a plurality of radio frequency terminals including a first terminal and a second terminal. The second switch element is connected between the first terminal and a ground terminal. The controller is configured to output a control signal to turn on or off the plurality of first switch elements and the second switch element and perform a normal operation mode to connect the common terminal to any one of the plurality of radio frequency terminals and a test mode to connect the common terminal to the first terminal, the second terminal, and the ground terminal according to a terminal switching signal.Type: ApplicationFiled: September 16, 2011Publication date: June 21, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yugo Kunishi, Toshiki Seshita
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Publication number: 20120139608Abstract: A multiplexer is provided. The multiplexer includes an output coupled to a complementary driving unit and a plurality of switch circuits. Each switch circuit includes a channel unit and two switches. The two switches respectively conduct two input signals to a channel end of the channel unit during different switch conduction periods, and the channel unit conducts the channel end to an output end during a channel conduction period. The switch conduction period of the first switch in the first switch circuit equals the switch conduction period of the second switch circuit, the switch conduction period of the second switch in the second switch circuit equals the switch conduction period of the first switch circuit, and the first and second switches are coupled to the same input signal.Type: ApplicationFiled: July 11, 2011Publication date: June 7, 2012Applicant: MSTAR SEMICONDUCTOR, INC.Inventor: Shuo-Ting Kao
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Patent number: 8183715Abstract: A reverse current preventing circuit of an N channel type switching MOS transistor connected between a voltage input terminal and an output terminal to control a conduction state between the voltage input terminal and the output terminal, the circuit comprises: a first MOS transistor connected between a substrate of the switching MOS transistor and a ground point; and a second MOS transistor connected between the substrate of the switching MOS transistor and a point having a piece of predetermined constant potential higher than that of the ground point, wherein the piece of predetermined constant potential higher than that of the ground point is applied to the substrate of the switching MOS transistor while the switching MOS transistor is made to be in its on-state, and ground potential is applied to the substrate of the switching MOS transistor while the switching MOS transistor is made to be in its off-state.Type: GrantFiled: March 4, 2010Date of Patent: May 22, 2012Assignee: Mitsumi Electric Co., Ltd.Inventors: Daisuke Hanawa, Osamu Kawagoe, Tomiyuki Nagai, Hitoshi Tabuchi
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Patent number: 8183911Abstract: An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.Type: GrantFiled: October 19, 2009Date of Patent: May 22, 2012Assignee: STMicroelectronics International N.V.Inventors: Somnath Kundu, Pikul Sarkar, Nitin Gupta
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Publication number: 20120119815Abstract: A switching circuit of a semiconductor apparatus includes a first switching unit configured to substantially prevent a leakage current applied from an outside and simultaneously switch a first signal with a first high voltage bias level, and a second switching unit configured to switch a second signal with a second high voltage bias according to the first high voltage bias level. The first switching unit and the second switching unit are selectively switched by a first enable signal and a second enable signal, which are applied from an outside, to generate a global bias signal.Type: ApplicationFiled: August 25, 2011Publication date: May 17, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Won Beom Choi
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Patent number: 8164378Abstract: A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.Type: GrantFiled: May 6, 2008Date of Patent: April 24, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Stefano Pietri, Alfredo Olmos, Jehoda Refaeli, Jefferson Daniel de Barros Soldera
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Publication number: 20120081162Abstract: Disclosed is an apparatus and methodology for operating an automatic darkening filter (ADF) eye protection device. An operating voltage is alternately applied to a pair of control terminals of an ADF device circuit in a continuing sequence where a first polarity voltage is applied to the pair of terminals and then reversed. A delay period is provided between application of the alternating polarities. In some embodiments ground potential is applied to both terminals of the pair of terminals during the delay period.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: KIMBERLY-CLARK WORLDWIDE, INC.Inventors: DONALD WILLIAM GREINER, THOMAS JOE HAMILTON
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Patent number: 8129862Abstract: A scalable highest available voltage selector circuit determines the highest of n input voltages and connects the highest voltage to an output. The circuit has at least n circuit branches, each of which comprises n?1 “comparator” FETs connected between an input voltage and an output node, and a diode-connected FET connected between the output node and a current source. The junction of the diode-connected transistor and current source provides a control signal used by the other branches. Each of a branch's comparator FETs have their gates connected to a respective one of the other branches' control signals, such that they are driven on regeneratively when the applied input voltage is the highest of the n input voltages. Each branch also includes n?1 “shorting” FETs connected across the diode-connected transistor, arranged to be driven off when the applied input voltage is the highest, but which are otherwise driven on.Type: GrantFiled: October 23, 2009Date of Patent: March 6, 2012Assignee: Analog Devices, Inc.Inventor: Jonathan Mark Audy
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Publication number: 20120051148Abstract: A voltage signal multiplexer includes a control and bias stage to generate at least one control and bias signal as a function of first and second selection signals and first and second input voltage signals. The multiplexer further comprises a switching stage configured to receive the at least one first control and bias signal and to generate therefrom, on an output terminal, an output signal having the first input voltage signal in response to the first and the second selection signals indicating the selection of the first input voltage signal, and having the second input voltage signal in response to the first and the second selection signals indicating the selection of the second input voltage signal. The switching stage is also configured to place the output terminal in a high-impedance condition in response to the first and the second selection signals indicating the high-impedance condition.Type: ApplicationFiled: July 15, 2011Publication date: March 1, 2012Applicant: STMICROELECTRONICS S.R.L.Inventor: Carmelo Chiavetta
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Patent number: 8120418Abstract: A large-scale integrated circuit according to the present invention includes a plurality of functional blocks for independently performing a signal processing operation, and a selection controlling circuit for generating a first control signal to select one of the plurality of functional blocks, in which the selection controlling circuit includes a control signal generating circuit for generating a second control signal for stopping the operation of its circuit, and the selection controlling circuit generates the first and the second control signals by a command from a different control circuit.Type: GrantFiled: October 30, 2008Date of Patent: February 21, 2012Assignee: Sharp Kabushiki KaishaInventor: Yasuyuki Kii
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Patent number: 8120367Abstract: An analog input device including a scanning circuit including a first insulation transformer insulating an analog signal inputted from a thermocouple, a power supply section charging a test voltage used for disconnection detection of the thermocouple, a second insulation transformer in which the scanning circuit and the power supply section are connected in parallel, and a control circuit for outputting a pulse signal to be inputted to the second insulation transformer. The second insulation transformer insulates and transfers a drive pulse for switching the scanning circuit and a power supply pulse for feeding power to the power supply section. The control circuit carries out a timing control so that the drive pulse and the power supply pulse are not outputted at the same time. Accordingly, an insulation transformer for application of a test voltage is not required, and thus the total number of the components is reduced to a great extent and reductions in costs and size thereof are realized.Type: GrantFiled: December 14, 2006Date of Patent: February 21, 2012Assignee: Mitsubishi Electric CorporationInventors: Yoshihiro Akeboshi, Seiichi Saito, Tetsuya Nagakawa
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Patent number: 8115520Abstract: A driver circuit includes a main driver which receives an input signal and outputs a first signal corresponding to the input signal, a sub driver which receives the input signal and outputs a non-inverted signal and an inverted signal corresponding to the input signal, a differentiating circuit including resistors and a variable capacity condenser, which outputs signals by differentiating the non-inverted signal and the inverted signal, respectively, and an addition unit which outputs a high frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the non-inverted signal, or a low frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the inverted signal.Type: GrantFiled: August 20, 2009Date of Patent: February 14, 2012Assignee: Advantest Corp.Inventors: Naoki Matsumoto, Takashi Sekino
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Patent number: 8116321Abstract: A router, for routing at least one input signal to at least one output, comprises at least one input module and at least one output module. Each of the input and output modules includes at least one clock selector circuit for selecting from among a first and second clock signal, and an oscillator signal, as a common output clock signal for the at least first router, based in part on whether at least one of the first and second clock signals has toggled. The clock selector circuit provides redundancy as well as distribution of clock signals among elements within each module.Type: GrantFiled: June 1, 2005Date of Patent: February 14, 2012Assignee: Thomson LicensingInventors: Carl Christensen, David Lynn Bytheway, Lynn Howard Arbuckle, Randall Geovanny Redondo
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Publication number: 20120032726Abstract: A power supply selection/detection circuit to select one main power supply from a plurality of external power supplies includes a resistance element with one end connected to an external power supply and another end connected to the main power supply, a first voltage detector to receive a voltage of the external power supply and detect a voltage of the external power supply, a second voltage detector to detect a voltage between the ends of the resistance element, and a switch connected between the external power supply and a ground to short-circuit or open-circuit between the external power supply and the ground according to an output of the second voltage detector. The resistance element and the first voltage detector are disposed for each of the plurality of external power supplies, and the second voltage detector and the switch are disposed for at least one of the plurality of external power supplies.Type: ApplicationFiled: October 13, 2011Publication date: February 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Yoshitaka NISHIGATA
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Patent number: 8111094Abstract: A sample and hold circuit is disclosed that provides longer hold times. An analog multiplexer circuit is also disclosed that exhibits low switch leakage. The analog multiplexer circuit comprises a shared node, a plurality of input circuits, a control input for selecting one or more of the plurality of input circuits, and an amplifier coupled to the shared node. Each input circuit comprises an input node, a primary input switch for selectively coupling an input to the input node, and a secondary input switch for selectively coupling the input node to the shared node, wherein the secondary input switch comprises one or more transistor switches. The parasitic drain and source diodes of one or more transistor switches in secondary input switch in a selected input circuit are coupled to a voltage that is distinct from an input signal of the selected input circuit.Type: GrantFiled: July 1, 2010Date of Patent: February 7, 2012Assignee: LSI CorporationInventor: Jonathan H. Fischer
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Publication number: 20120019307Abstract: A method for synthesis of a hysteresis function of a plurality of inputs is described. The method includes receiving and processing of a plurality of input signals with at least a parameterized multivariable nonlinearity, the parameterized multivariable nonlinearity serving as a parameterized hysteron, to produce at least one output signal. The plurality of input signals is also processed by at least a controller function, the controller function comprising memory and producing at least one control signal responsive to at least one of the plurality of input signals, the at least once control signal for controlling the parameterized hysteron. The at least one control signal is used to control the parameterized hysteron so as to create a hysteretic response to at least one of the plurality of input signals.Type: ApplicationFiled: July 19, 2011Publication date: January 26, 2012Inventor: Lester F. LUDWIG
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Patent number: 8085082Abstract: According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate data output. In one embodiment, each intermediate multiplexer has a critical delay path comprising a first NAND gate and a second NAND gate. In one implementation a four-to-one intermediate multiplexer comprises a first two-input NAND gate and a second four-input NAND gate. In one embodiment, a 32-to-1 high speed multiplexer comprises four four-to-one intermediate multiplexers. According to one implementation of this embodiment, the 32-to-1 multiplexer has a critical delay path from any of the data inputs to the final data output comprising a first NAND gate, a second NAND gate, a NOR gate, and a third NAND gate.Type: GrantFiled: May 30, 2007Date of Patent: December 27, 2011Assignee: Broadcom CorporationInventor: Paul Penzes
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Patent number: 8060771Abstract: Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses has been achieved. The circuit suspends the clock output in either a high or a low state, instantaneously with the suspend signal. There is no restriction on either the suspend pulse width or position in relation to the input clock. The asynchronous logic implementation is using standard cell logic gates. The circuit functionality is not dependent on the manufacturing technology, i.e. CMOS, bipolar, BI-CMOS, GaAs, etc. implementations are all valid.Type: GrantFiled: June 30, 2008Date of Patent: November 15, 2011Assignee: Dialog Semiconductor GmbHInventor: Julian Tyrrell
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Patent number: 8050648Abstract: Digital mixers which permit mixing of asynchronous signals may be constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), an RSFQ D flip-flop, an RSFQ XOR circuit, and an RSFQ T flip-flop. A binary tree arrangement of T flip-flops can be used to provide in-phase and quadrature phase-divided replicas of a reference signal. The mixing elements can be either an XOR circuit, a dual port NDRO circuit functioning as a multiplexer or an RS type NDRO functioning as an AND gate. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.Type: GrantFiled: March 16, 2010Date of Patent: November 1, 2011Assignee: Hypres, Inc.Inventors: Alexander F. Kirichenko, Deepnarayan Gupta, Saad Sarwana
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Publication number: 20110234296Abstract: Embodiments of the present invention include a family of multi-way switches that can be configured to output an input signal to any combination of n output signal lines. Certain embodiments of the present invention employ a memristive junction between the input signal and each output signal line, the state of which is configured by one or more control signal lines. The memristive junction between the input signal line and each output signal can be switched between a stable, low-conductance state and a high-conductance state. A wide variety of different types of multi-way switches may be fabricated according to various embodiments of the present invention.Type: ApplicationFiled: January 30, 2009Publication date: September 29, 2011Applicant: Hewlett-Packard Development Company, L.P.Inventors: Marco Fiorentino, Wei Wu, John Paul Strachan
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Publication number: 20110234295Abstract: A high-frequency switch module includes a switch IC. An impedance matching circuit is connected to the antenna port of the switch IC. The impedance matching circuit includes a high-pass filter and a low-pass filter. The high-pass filter is disposed on the side of the antenna port, and is a substantially L-shaped circuit including a capacitor and an inductor. The antenna port is connected to the ground by the inductor.Type: ApplicationFiled: September 24, 2010Publication date: September 29, 2011Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Takanori UEJIMA, Hisanori MURASE
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Patent number: 7990296Abstract: Techniques are provided to serialize and delay parallel input data signals and are particularly useful for low power applications. In one example, a device includes a plurality of data input ports adapted to receive N parallel single-ended input data signals, and a clock input port adapted to receive a clock signal substantially synchronized with the parallel single-ended input data signals. The device also includes a cell adapted to serialize the parallel single-ended input data signals to provide N/2 first serial differential output data signals in response to the clock signal, delay the parallel single-ended input data signals, and serialize the delayed parallel single-ended input data signals to provide N/2 delayed second serial differential output data signals in response to the clock signal. The delayed second serial differential output data signals are delayed relative to the first serial differential output data signals. The device also includes a plurality of output ports.Type: GrantFiled: March 10, 2010Date of Patent: August 2, 2011Assignee: SMSC Holdings S.a.r.l.Inventors: Heng Wang, Hongming An, CongQing Xiong
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Publication number: 20110181307Abstract: In one embodiment of the present invention, a microscale or sub-microscale signal line, interconnected with one set of parallel nanowires of a nanowire crossbar, serves as a multiplexer. The multiplexer is used to detect the conductivity state of a nanowire junction within the nanowire crossbar. In one method embodiment of the present invention, a first signal is output to the two nanowires interconnected by the nanowire junction, while a second signal is output to the remaining nanowires of the nanowire crossbar. Then, the second signal is output to the two nanowires interconnected by the nanowire junction, while the first signal is output to the remaining nanowires of the nanowire crossbar. The resulting signal detected on the multiplexer is reflective of the conductivity state of the nanowire junction.Type: ApplicationFiled: March 5, 2009Publication date: July 28, 2011Inventor: Philip J. Kuekes
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Patent number: 7973588Abstract: An analog insulation multiplexer not causing magnetic saturation even if a small transformer is used and having a wide use temperature range. The analog insulation multiplexer includes: a first switching element for generating a drive control signal in accordance with an external signal; a drive insulation transformer for receiving the drive control signal on a primary side via a first resistor and for delivering an insulated drive control signal from a secondary side; a second switching element for chopping an analog signal input in accordance with the insulated drive control signal; and an analog signal insulation transformer for delivering an insulated chopped analog signal on a secondary side.Type: GrantFiled: April 10, 2007Date of Patent: July 5, 2011Assignee: Mitsubishi Electric CorporationInventor: Seiichi Saito
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Patent number: 7969224Abstract: A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.Type: GrantFiled: June 17, 2009Date of Patent: June 28, 2011Assignee: Honeywell International, Inc.Inventor: Paul M. Werking
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Patent number: 7965122Abstract: An interface system delivers an output signal having a first signal characteristic in response to first and second input signals having the first signal characteristic and a second, different signal characteristic. The interface system includes a signal input for receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from the first signal characteristic, a detector circuit for detecting whether the signal at the input is the first signal or the second signal, and a translator circuit for translating either of the first signal or the second signal into the output signal.Type: GrantFiled: March 10, 2010Date of Patent: June 21, 2011Assignee: Bayer Healthcare LLCInventor: Robert D. Schell
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Patent number: 7956661Abstract: The present invention provides a standard cell and a scan flip flop circuit capable of introducing a scan test also to a system LSI having an ACS circuit. One standard cell is configured by: a 3-input selection circuit for selecting one signal from three input signals; and a flip flop circuit. The 3-input selection circuit receives a control signal and a test signal at its control input part and its first input part, respectively. First and second signals are supplied to second and third input parts, and a selection signal is supplied to a selector input part. On the basis of the control signal and the selection signal, any of the signals input to the first to third input parts is output from the output part.Type: GrantFiled: January 29, 2009Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventor: Hirohisa Machida
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Patent number: 7952386Abstract: There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.Type: GrantFiled: July 8, 2009Date of Patent: May 31, 2011Assignee: Hynix Semiconductor Inc.Inventor: Beom-Ju Shin
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Patent number: 7948268Abstract: Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit. The transistor chain preferably delays transitions that would otherwise occur relatively quickly, to match the timing of transitions that occur relatively slowly. The timing of relatively slow transitions is left unaltered. The invention advantageously allows all selector input transitions to yield a data output transition with a substantially constant delay.Type: GrantFiled: September 15, 2010Date of Patent: May 24, 2011Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Eitan Rosen, Dan Lieberman
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Publication number: 20110102010Abstract: A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured.Type: ApplicationFiled: July 25, 2008Publication date: May 5, 2011Inventor: Dinakaran Chiadambaram
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Publication number: 20110089934Abstract: Apparatus and methods for providing a voltage signal indicative of the voltage being supplied by each phase of a multiphase voltage being supplied to a load. For each phase, a phase to neutral voltage is produced by providing a virtual ground. For each phase, a phase to phase voltage is produced by determining a difference between a pair of phase to neutral voltages. Either the phase to neutral voltages or the phase to phase voltages for each phase are output depending on the configuration of the multiphase voltage being supplied to the load.Type: ApplicationFiled: October 19, 2009Publication date: April 21, 2011Applicant: EATON CORPORATIONInventor: Michael Patrick KING