Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

Abstract: A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit.

Abstract: A switch fabric that carries analog differential signals is constructed from 2×2 switches. Each 2×2 switch has two differential inputs that are applied to two demultiplexers. Each 2×2 switch also has two differential outputs, each driven by an equalizing mux. Each demultiplexer has two amplifiers that drive intermediate differential signals to the two equalizing muxes. Each equalizing mux has two equalizers that receive the intermediate differential signals from the two demultiplexers. A select signal enables one equalizer but disables the other to select one of the two intermediate differential inputs. A combining amplifier receives differential outputs from both equalizers and generates a final differential output. R, C values in each equalizer can be adjusted to compensate for loading variations in the intermediate differential signals which can have different physical lengths in a switch fabric.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: An exemplary electronic device includes a power module having an anode and a cathode; an audio module having a first audio signal terminal, a second audio signal terminal and a ground terminal; and an audio socket having a first audio signal terminal, a second audio signal terminal connected to the second audio terminal of the audio module, and a ground terminal, wherein the first audio terminal of the audio socket is selectively connected to the anode of the power module and the first audio signal terminal of the audio module via a first switch, the ground terminal of the audio socket is selectively connected to the cathode of the power module and the ground terminal of the ground module of the audio module via a second switch. Therefore, users can charge the electronic device via the audio interface.

Abstract: Multiple supply voltage select circuit for use with reduced supply voltage levels and method for using same are described. A first and second set of P-channel transistors are used for voltage pull-up at a common node using two supply voltages, respectively. A P-channel transistor from each of the sets is gated by output of a respective level shifter. Both of the level shifters are biased with a higher of the two supply voltages. First and second inputs are respectively provided to the level shifters and to gates of other P-channel transistors of each of the sets.

Abstract: A plurality of circuit blocks are provided in a semiconductor device which collects and corrects impairment quantities of discretionary areas in a circuit group of various types having random couplings. The semiconductor device is provided with a detector, which is arranged in each circuit block and detects an electric signal of an element in the circuit block; a wiring wherein each detector output passes through; a plurality of switches for feeding the wiring with each detector output; and a buffer connected to the wiring and passes through a direct current voltage.

Abstract: Integrated circuit devices include operational circuits that are configured to operate from power supply voltages and from high voltages that are generated in the integrated circuit device from the power supply voltages. A circuit for measuring the high voltages is also provided in the integrated circuit. The circuit includes a common high voltage measurement pad and high voltage switch units connected to the common high voltage measurement pad. A respective high voltage switch unit is configured to transmit a corresponding one of the high voltages to the common high voltage measurement pad in response to a corresponding enable signal. The operational circuits may be non-volatile memory cells, such as flash memory cells. Related methods of measuring high voltages in an integrated circuit device are also described.

Abstract: Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (D1, and D1) and a clock signal (CLK), and generates differential RZ-mode outputs (R1 and R1). The second differential output unit receives NRZ input signals (D2 and D2) and an inverted clock signal ( CLK), and generates differential RZ-mode outputs (R2 and R2). The selection unit receives the RZ-mode output signals (R1, R1, R2, and R2) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.

Abstract: A first switch circuit includes first and second N-type MOSFETs. A second switch circuit includes third and fourth N-type MOSFETs. A control signal is input to a first inverter and a third inverter, the output of the first inverter input to a second inverter and the gate of the fourth MOSFET, the output of the second inverter input to the gate of the first MOSFET, the output of the third inverter input to a fourth inverter and the gate of the third MOSFET, the output of the fourth inverter input to the gate of the second MOSFET. A first input voltage is connected to the source of the second MOSFET and the sources of N-type MOSFETS in the third and fourth inverters. A second input voltage is connected the source of the fourth MOSFET and the sources of N-type MOSFETS in the first and second inverters.

Abstract: An improved LUT based multiplexer, including a first set of muxlets, each receiving a subset of input data lines at its inputs and one or more muxlet stages cascaded together to form a tree structure in which the roots are the first set of muxlets and the last stage of muxlet produces the final output.

Abstract: A MOSFET-based, multi signal-switching circuit controllably passes analog/audio signals and digital signals through a common terminal to a single connector. Analog/audio signals are coupled through a single N-channel MOSFET analog signal switch which, when turned-ON, minimizes distortion of the analog/audio signal and capacitive loading to an adjacent, MOS-based or CMOS-based digital data signal switch. A respective turn-OFF circuit maintains its associated switch MOSFET turned OFF.

Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.

Abstract: A dual mode comparator circuit is disclosed. The dual mode comparator includes a plurality of differential transistor pairs. Each differential transistor pair includes a plurality of inputs and outputs. The outputs of the differential transistor pairs are coupled to inputs of a multiplexor. The multiplexor includes at least one control input for selecting between the multiplexor inputs and provides the selected input to the multiplexor output. The dual mode comparator further includes a comparator back end that is coupled to the output of the multiplexor. The comparator back end may include a folded cascode and additional gain stages. The comparator back end provides the comparator output to the next stage. The dual mode comparator may be used in automatic testing equipment embodiments.

Abstract: An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.

Abstract: According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate data output. In one embodiment, each intermediate multiplexer has a critical delay path comprising a first NAND gate and a second NAND gate. In one implementation a four-to-one intermediate multiplexer comprises a first two-input NAND gate and a second four-input NAND gate. In one embodiment, a 32-to-1 high speed multiplexer comprises four four-to-one intermediate multiplexers. According to one implementation of this embodiment, the 32-to-1 multiplexer has a critical delay path from any of the data inputs to the final data output comprising a first NAND gate, a second NAND gate, a NOR gate, and a third NAND gate.

Abstract: A selection circuit includes a first switching unit that selects and outputs a first signal from among a plurality of analog signals input thereto; a second switching unit that outputs a second signal from a reference voltage supplied therein; and an amplifier that adds the first signal and the second signal.

Abstract: An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a regular input signal, a second signal input, and an output. The circuit further comprises a multiplexer with first and second inputs connected to the first and second signal inputs, respectively, for selectively switching either of the first and second signal inputs to the output under control of a selection signal. A gate circuit provides the selection signal to the multiplexer. The input of the gate circuit is driven by control circuitry. Clamping circuitry is provided that limits the voltage at the first input of the multiplexer. With such a circuit design, a relatively high voltage applied to the first signal input will switch the circuit to another operating mode, such as a test mode.

Abstract: A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

Abstract: There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuit 1a has a control signal terminal INCNT, a first power imputer terminal IG11, and a second power supply terminal IG12 as input terminals and has a first output terminal OG11 and a second output terminal OG12 as output terminals. The gate of a second P-type transistor P2 is connected to the first output terminal OG11 of the gate control circuit 1a and the gate of a second P-type transistor P2 is connected to the second output terminal OG12 of the gate control circuit 1a, wherein the first P-type transistor P1 and the second P-type transistor P2 are connected in series between a first power source VDD1 and a second power source VDD2 to form a switch section.

Abstract: The present invention provides methods and systems for multiplexing five channels, such as 10 Gb/s to 50 Gb/s, into a single data sequence using a 5:1 multiplexer using a ?th ratio duty cycle clock. The ?th ratio duty cycle clock is a clock with a period equal to the channel data rate, and a pulse width equal to the period of data rate five times higher. The ?th ratio duty clock is combined with a proper combination of delays and phase shifters to allow the use of AND gates and OR gates to combine the five channels in a proper sequence to create a serial five-times higher data sequence.

Abstract: A multiplexing device complies with Multimedia over Coax Alliance (MoCA) specifications, and includes a circuit board disposed in a casing, first and second adapters disposed on the circuit board and adapted to be connected between an input end and an output end, and a shielding component. The first adapter includes a first low pass filter connected in series to a first high pass filter. The second adapter includes a second low pass filter connected in series to a second high pass filter. The shielding component is disposed on the circuit board between the first and second low pass filters, and has a height greater than that of the first and second adapters such that electromagnetic energy emitted by the first and second adapters is blocked to reduce undesired coupling between signals in the first and second adapters.

Abstract: Techniques for adaptively scaling voltage for a processing core are described. In one scheme, the logic speed and the wire speed for the processing core are characterized, e.g., using a ring oscillator having multiple signal paths composed of different circuit components. A target clock frequency for the processing core is determined, e.g., based on computational requirements for the core. A replicated critical path is formed based on the characterized logic speed and wire speed and the target clock frequency. This replicated critical path emulates the actual critical path in the processing core and may include different types of circuit components such as logic cells with different threshold voltages, dynamic cells, bit line cells, wires, drivers with different threshold voltages and/or fan-outs, and so on. The supply voltage for the processing core and the replicated critical path is adjusted such that both achieve the desired performance.

Abstract: An embodiment of this invention provides a circuit and method for reducing the number of electronic components needed to calibrate circuits on an IC. A multiplexer is located on the IC where the outputs of a plurality of circuits located on the IC are each connected to a separate data input of the multiplexer. The control input of the multiplexer selects which data input of the multiplexer is connected to an external component. Each data input is individually connected to the component periodically.

Abstract: A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

Abstract: A test clock generating apparatus is provided in the invention. The test clock generating apparatus includes an at-speed clock generator and a multiplexer. The at-speed clock generator is for receiving a reference clock signal and a scan chain enable signal and outputting an at-speed clock signal. The frequency of the at-speed clock signal is substantially the same with that of the reference clock signal. The multiplexer is for receiving the at-speed clock signal and a scan chain clock signal and outputting a test clock signal according to the scan chain enable signal. The frequency of the reference clock signal is higher than that of the scan chain clock.

Abstract: Headset connector systems and headset engaging connector systems are provided. Headset connector systems can include two or more headset connector contact regions. Headset engaging connector systems can include two or more headset engaging contact regions to provide at least one of power and data. The headset connector system or the headset engaging connector system can include switching circuitry electrically coupled to the respective contact regions. The switching circuitry can be operative to determine an interface orientation between the headset connector contact regions and the headset engaging contact regions. The switching circuitry can also be operative to selectively route received signals based on the determined interface orientation. At least a portion of the headset connector system or the headset engaging connector system can be magnetically attractive.

Abstract: According to an aspect of the present invention, there is provided an output circuit including a first output unit supplying a first voltage, a second output unit supplying a second voltage, a switching unit selectively outputting, to an output end, the first voltage from the first output unit and the second voltage from the second output unit, a detection unit detecting a voltage of the output end, and a control unit controlling one of the first voltage and the second voltage on the basis of the voltage detected by the detection unit.

Abstract: An input circuit commonly uses input ports of a microcomputer for a plurality of contact input terminals such as switches provided on the way to the ground. Transistors (Q1) to (Q8) whose bases are connected with contact input terminals (IN1) to (IN8) are provided. Groups of transistors, such as odd-numbered transistors and even-numbered transistors, are made selectable or non-selectable together by a selection output from an I/O port (P01) or (P02) of a microcomputer (12), and collector currents of a plurality of transistors (Q1, Q2; Q3, Q4; Q5, Q6; Q7, Q8) which are not simultaneously selected are converted into voltages using common resistors (R1) to (R4). These voltages then are fed to I/O ports (P1) to (P4). Accordingly, even upon a rise of a contact input from a ground potential due to the ON resistance of switches (SW1) to (SW8), the states of the contacts can be judged precisely.

Abstract: The invention provides a current multiplexing circuit for time-domain multiplexing a plurality of current signals such as photocurrents that are received in a plurality of input terminals. The current signals are multiplexed using one or more analog low-resistance switches operational to connect each of the input terminals to an output switch terminal at a time in a selected sequence, while coupling the other input terminals and the output switch terminal to a reference potential such as ground. The current multiplexing circuit can be used in an optical power monitor with auto-calibration functionality for monitoring a plurality of optical signals.

Abstract: Input stages for use in multiplexing, and methods for using the same, are provided herein. An input stage includes an input terminal and an output terminal. A voltage input signal is accepted at the input terminal of the input stage. When the input stage is selected, a substantially unmodified version of the voltage input signal is presented at the output terminal of the input stage, when the input stage is selected. When the input stage is deselected, a rejection voltage signal is produced, where the rejection voltage signal is of substantially equal magnitude and opposite polarity to the corresponding voltage input signal in order to reject the voltage input signal and thereby present a substantially constant voltage at the output terminal of the input stage regardless of variations in the voltage input signal.

Abstract: Disclosed is a data receiver circuit including a differential pair having first and second transistors of a first conductivity type, which receives at first and second inputs thereof a binary signal by which data transfer is performed in a differential form, a load circuit composed of first and second diode-connected transistors of a second conductivity type, connected to the first and second inputs of the differential pair, respectively, an output circuit that charges and discharges an output terminal using currents corresponding to currents that flow through the first and second diode-connected transistors of the second conductivity type, respectively, and a current supply circuit with an output current thereof input to at least one of the first and second diode-connected transistors of the second conductivity type.

Abstract: A bandgap reference circuit, taking two or more power supplies as the input power supply for outputting a reference voltage, includes a first reference circuit, a second reference circuit, a power selection circuit and a switch circuit. The first and second reference circuits receive two respective power supplies for producing first and second voltages, respectively. As the power selection circuit takes the first power voltage level as the input voltage, the power selection circuit outputs a first control signal; while the power selection circuit takes the second power voltage level as the input voltage, the power selection circuit outputs a second control signal. The switch circuit is coupled to the power selection circuit, the first reference circuit and the second reference circuit. As the switch circuit receives the first control signal, it outputs the first voltage; while the switch circuit receives the second control signal, it outputs the second voltage.

Abstract: A power supply switching circuit includes a detection circuit which detects a reduction in a voltage level of the main power supply and outputs a detection signal; a first switch circuit which connects a main power supply to an internal power supply node before a reduction in voltage level is detected and disconnects the main power supply from the internal power supply node when the reduction in voltage level to the predetermined detection level is detected; and a second switch circuit which disconnects the subordinate power supply from the internal power supply node before a reduction in voltage level is detected, connects the subordinate power supply to the internal power supply node from when the reduction in voltage level is detected to when the data backup is completed and subsequently disconnects the subordinate power supply from the internal power supply node when the data backup is completed.

Abstract: A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.

Abstract: Methods and apparatus are provided for implementing efficient multiplexers on a programmable chip using a lookup table. A load logic input line associated with a lookup table having limited input lines is used to augment the number of input lines that can be handled by a particular lookup table. Load logic and a lookup table having four input lines can be used to implement a 3:1 multiplexer having five input lines.

Abstract: Methods and apparatus are provided for implementing efficient multiplexers on a programmable chip using a lookup table (LUT). A load logic input line associated with a LUT having limited input lines is used to augment the number of input lines that can be handled by a particular LUT. A reset logic input line associated with a LUT is further used to augment the number of input lines. Load logic, reset logic, and a LUT having four input lines can be used to implement a 4:1 multiplexer having seven input lines including four data and three control lines.

Abstract: A method and apparatus to convert parallel data to serial data. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel data from the data pipeline, and configured to output the parallel data serially.

Abstract: A selecting circuit having minimal signal distortion caused by non-linearity of semiconductor switching elements includes a plurality of circuit groups each comprising an input terminal (INa); serially connected resistors (R1a, R2a) having a first end connected to the input terminal; a semiconductor switching element (SW1a) having a first end connected to a node between the resistors; and semiconductor switching elements (SW2a, SW3a) having first ends connected to a second end of the resistors (R1a, R2a). The circuit further includes an operational amplifier (OP) having an inverting input terminal to which second ends of semiconductor switching elements (SW1a, SW1b, . . . , SW1n) in respective ones of the circuit groups are connected in common, and an output terminal to which second ends of semiconductor switching elements (SW2a, Sb 2b, . . .

Abstract: A multi-voltage multiplexer system includes multiple voltage inputs, each voltage input providing a different input voltage, and multiple control inputs operative to select one of the input voltages for output. Each of multiple transistors is connected to a different one of the voltage inputs and to a different one of the control inputs, and the transistors are connected to an output such that the selected input voltage is provided at the output. A bulk of each of the transistors is connected together to form a bulk network, and the bulk network is connected to the gate of each transistor such that the transistors connected to non-selected voltage inputs have gates set at approximately the maximum of the input voltages.

Abstract: An integrated circuit capable of detecting or generating a reference voltage suitable to a functionality of an electronic device is disclosed. The integrated circuit includes a plurality of reference voltage generating circuits, having characteristics different from one another, and a controller, which selects one of the plurality of reference voltage generating circuits according to the functionality of the electronic device.

Abstract: A selection circuit and method. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: A switch circuit comprising a plural of switch elements and a control circuit operative to simultaneously shut off all of the switch elements. When forming a switch device by the combination of plural switch circuits, no other additional switches connected in series in the subsequent stage is required for shutting off unintentional signals from other input terminals.

Abstract: A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

Abstract: A clock switching device capable of automatic switching to a clock distribution system for back-up without interrupting processing of the device, which includes an abnormality detection unit which detects lack of coincidence in a logical level between a current clock pulse and a one-cycle preceding clock pulse as abnormality in a waveform on the basis of a plurality of cock pulses, a phase adjustment unit for switching which adjusts a phase of other clock pulse to a phase of a clock pulse being output, and a switching unit which switches to and outputs other clock pulse whose phase is adjusted by the phase adjustment unit for switching based on detection of lack of coincidence in a logical level by said abnormality detection unit.

Abstract: A digitally controlled circuit is arranged to provide the combined functions of level shifting, multiplexing, and delay control functions. The circuit is compact, and uses lower power and lower overall noise susceptibility over other solutions. A programmable bias current is arranged to adjust the delay through the circuit. The bias current can be provided by a digitally controlled current source, a binary weighted current DAC, or other digitally controlled means. The multiplexing functions are provided by an input stage circuit that is current limited by the programmable bias current. An output stage is arranged to convert signals from the input stage to a desired voltage level.

Abstract: A power supply monitoring circuit that monitors and delivers the highest voltage power supply to an IC system includes a voltage comparator that receives two different power supply voltages, and outputs a first signal to the gate of a first switching transistor connected between a first power supply and an system power supply output node. The comparator output is also input to an inverter, the output of which comprises a second signal connected to the gate of a second switching transistor connected between a second power supply and the system power supply output node. When the first supply voltage exceeds the second supply voltage, the first transistor is switched on to connect the first supply to the system output node, and the second transistor is switched off; and vice versa. The comparator includes designed-in hysteresis to prevent simultaneous switching of the two transistors.

Abstract: The invention provides a signal coupling circuit and method for coupling an analog input signal to a processing circuit. The signal coupling circuit includes a number of first coupling units, a second coupling unit and a first multiplexer. The first coupling units are coupled to a first input terminal of the processing circuit, for respectively receiving a plurality of input signals. The first multiplexer is coupled between the first coupling units and the processing circuit for selecting one of the input signals and transmitting the selected input signal to the processing circuit. The second coupling unit is coupled to a second input terminal of the processing circuit, for receiving a common reference signal, wherein the processing circuit uses the common reference signal as reference for processing some or all of the input signals.