Abstract: A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.

Abstract: Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line.

Abstract: A signal processing device enables a high quality enhanced signal to be obtained, and includes: a transform unit which transforms a mixed signal in which a first signal and a second signal are mixed, into a phase component and an amplitude component or a power component in each frequency; a first control unit which rotates the phase component in a predetermined frequency; a second control unit which compensates the amplitude component or the power component in the predetermined frequency according to the amount of change of the amplitude component or the power component rotated by the first control unit; and a synthesizing unit which synthesizes the phase component rotated by the first control unit, and the amplitude component or the power component compensated by the second control unit.

Abstract: A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A differential circuit system is provided. The differential circuit system includes: a different circuit set including a plurality of differential circuits, a voltage regulator, and a current drainage circuit set. The differential circuits are electrically connected between a first node and a second node, and each differential circuit generates a current flowing from the first node to the second node. A high voltage is provided to the first node and a low voltage is provided to the second node. The first node receives an external voltage. According to the first voltage, the voltage regulator generates the low voltage. The low voltage is provided to the second node. The current drainage circuit set generates a drainage current in between the second node and a ground voltage. A superposed current flowing to the voltage regulator is difference of the summation of currents minus the conducting current.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A passive filter for connection between an AC source and a load, in either three-phases or in a single-phase arrangement. The filter includes, for each phase, a trap circuit having an inductor in series with a capacitor, the trap circuit having at least two terminals. A line reactor is connected between the AC source and the load, the line reactor having at least an input terminal, an output terminal and a tap terminal. A switch selectively connects at least one of the trap circuit terminals to a selected one of the line reactor terminals. The switch is capable of selecting which of the trap circuit terminals to connect to which of the line reactor terminals on the basis of a level of voltage distortion being experienced by the AC source, or on the basis of a calculated level of background voltage total harmonic distortion.

Abstract: A semiconductor device includes conducting lines of a first group and a second group arranged in parallel, a plurality of first internal elements respectively coupled to the conducting lines of the first group and the second group and a plurality of first contact pads arranged between and along the conducting lines of the first group and the second groups, wherein at least a part of the plurality of first contact pads are respectively coupled to control terminals of the plurality of first internal elements, and the part of the plurality of first internal elements receive a plurality of first control signals through corresponding control terminals, respectively.

Abstract: Generating updated coefficients for an adaptive equalizer involves generating phase tracking information using asynchronous detection strategy (ADS) based on resolved data, and equalized signals, and estimating a phase corrected error based on the equalized signals, the phase tracking information and the resolved data. An inhibit signal is generated to inhibit updating of the equalization coefficients, the inhibit signal representing a likelihood of the phase corrected error being accurate, determined according to the phase corrected error, and the equalized signals. The equalization coefficients for the equalizer are adapted based on the received signals, and on the phase corrected error, and the adapting is inhibited according to the inhibit signal. Compared to conventional ADS, the new combination with the inhibit signal can enable improved convergence of coefficient adaptation. This is particularly useful for coherent receivers for optical systems.

Abstract: A noise removal circuit is provided having a first holding circuit (20) and a second holding circuit (22) which holds a value of an input signal (IN) at a plurality of different timings in synchronization with rising and falling of an internal clock signal (ICL) generated within a semiconductor device, and which removes noise of the input signal (IN) according to the held value.

Abstract: A method of canceling nonlinear distortions in pulse width modulated signals includes receiving an input signal. A first signal that is the modulated input signal is generated. The first signal has quantized levels representing the input signal. A pulse width modulated (PWM) sequence that is representative of the first signal is generated. A second signal that is the PWM sequence mixed with a carrier signal is generated. An error signal is generated in response to the first signal and modeled from the second signal. The error signal is added to the input signal.

Abstract: A method of debouncing a variable frequency step signal is provided. The method includes the steps of: (a) determining a first period in oscillations of the variable frequency step signal and applying a first debounce time to debounce oscillations in the variable frequency step signal, (b) detecting a second period in the oscillations of the variable frequency step signal, (c) calculating a second debounce time as a fraction of the first period, (d) applying the second debounce time to debounce oscillations having the second period, and (e) repeating the steps (b)-(d) for debouncing successive oscillations of varying periods in the variable frequency step signal.

Abstract: A glitch filter is disclosed herein. The glitch filter includes a high glitch filter circuit, a low glitch filter and a control circuit. The high glitch filter circuit is configured for generating a pull-up control signal in accordance with the input signal. The low glitch filter circuit is configured for generating a pull-down control signal in accordance with the input signal. The control circuit is configured for determining the logic level of the output of the glitch filter in accordance with the pull-up control signal and the pull-down control signal. A filtering method for filtering glitches is disclosed herein as well.

Abstract: In an embodiment, an electrical-line-noise canceller includes a phase detector, a phase lock loop, a zero-crossing detector, and an adaptive filter. The phase detector is configured to receive a composite input signal including an input neural signal combined with electrical line noise and to detect a phase of the electrical line noise. The phase lock loop is coupled to the phase detector and is configured to lock to the phase of the electrical line noise. The zero-crossing detector is coupled to the phase lock loop and is configured to detect zero crossings of an output of the phase lock loop. The adaptive filter is coupled to the zero-crossing detector and is configured to remove the electrical line noise from the composite input signal and output a filtered neural signal that is substantially similar to the input neural signal.

Abstract: A clock monitoring circuit is disclosed. The clock monitoring circuit is configured to receive first and second clock signals generated in respective clock domains. The clock monitoring circuit includes a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal. The first counter outputs a count value indicating the number of counted clock cycles. The clock monitoring circuit also includes a threshold comparator circuit configured to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of an expected range.

Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.

Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: A system and method receive the output signal from a capacitance diaphragm gauge (CDG) and generate a noise reduced output signal. An input signal processing circuit receives an input signal from a signal source that drives the CDG. The input signal processing circuit generates a segment of N normalized digital samples of the input signal. An output signal processing circuit receives the output signal from the CDG and generates M segments of N digital samples of the CDG output signal and averages the corresponding samples in the M segments to generate a signal segment of N averaged samples. Each of the N averaged samples is multiplied by a corresponding one of the N normalized samples to generate N products. The N products are averaged to generate an average product, which is multiplied by a constant to generate a system output signal with reduced noise.

Abstract: An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.

Abstract: An optimized pseudo-random period pattern can reduce audible noise in a system that includes an inverter circuit configured to provide power to an electric machine. A system can include a PWM optimization module (POM) comprising the PPP. A carrier period for a carrier signal used to provide PWM inverter drive signals can be selected in accordance with the PPP. The PPP can be expressed as an array of 200-400 elements, each element a period belonging to a finite set of 2 or more predetermined periods. A period can be selected by index from the array, and the index incremented to progress through the PPP, which can be repeated upon its completion. The PPP can be optimized to reduce audible noise while mitigating inverter losses. Modeling techniques can determine the number of array elements, the number of possible periods, and the period values that optimize the PPP.

Abstract: A system and method receive the output signal from a capacitance diaphragm gauge (CDG) and generate a noise reduced output signal. An input signal processing circuit receives an input signal from a signal source that drives the CDG. The input signal processing circuit generates a segment of N normalized digital samples of the input signal. An output signal processing circuit receives the output signal from the CDG and generates M segments of N digital samples of the CDG output signal and averages the corresponding samples in the M segments to generate a signal segment of N averaged samples. Each of the N averaged samples is multiplied by a corresponding one of the N normalized samples to generate N products. The N products are averaged to generate an average product, which is multiplied by a constant to generate a system output signal with reduced noise.

Abstract: A noise reduction filter is inserted between the source and non-linear transmission line (NLTL) in a frequency multiplier to improve phase noise performance. The noise reduction filter is suitably coupled directly to the input of the NLTL. The noise reduction filter and the output BPF are suitably low complexity filters.

Abstract: Embodiments of the present invention may provide an improved apparatus and method for reducing distortion in analog circuits. A circuit in accordance with the present invention may include a main path comprising an analog circuit with an input impedance, a source impedance representing the impedance of an input network driving the analog circuit, and a cancellation path. The cancellation path may be in parallel to the main path and may generate a cancelling non-linear current to substantially cancel a non-linear current drawn to the input impedance, resulting in a decrease of non-liner current flowing through the source impedance.

Abstract: Method and circuits for cancelling reflected waves from a load are disclosed. An embodiment of the method includes transmitting a signal to the bad from a current source, wherein a transistor is connected in parallel with the current source at a node. The transistor is biased so that a reflected wave at the node will cause the drain to source voltage of the transistor to increase. The drain current of the first transistor increases by way of channel length modulation when the drain to source voltage increases, the increased drain current cancels the reflected wave.

Abstract: A concept is disclosed for outputting a file having a media data container and a metadata container, the concept including providing an error information related to a data sample and storing the error information together with a sample number related to the data sample in the metadata container.

Abstract: A receiver and a method for equalizing signals, the method includes: receiving input signals; sampling the input signals to provide oversampled samples; processing the oversampled samples to provide symbol spaced samples and to provide fractionally spaced samples that represent the oversampled samples; calculating taps of a fractionally spaced equalizer based on the symbol spaced samples; feeding the taps to the fractionally spaced equalizer; and filtering the fractionally spaced samples by the fractionally spaced equalizer to provide equalized samples.

Abstract: A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal.

Abstract: A clock generator is disclosed for use with an oscillator device. The clock generator may include a signal conditioning pre-filter and a comparator. The signal conditioner may have an input for a signal from the oscillator device, and may include a high pass filter component and a low pass filter component. The high pass filter component may pass amplitude and frequency components of the input oscillator signal but reject a common mode component of the oscillator signal. Instead, the high pass filter component further may generate its own common mode component locally over which the high frequency components are superimposed. The low pass filter component may generate a second output signal that represents the locally-generated common mode component of the first output signal. The clock generator may have a comparator as an input stage which is coupled to first and second outputs of the filter structure.

Abstract: This invention uses new switching regulator structures to split single magnetic loops into multiple magnetic loops, with linked opposing magnetic fields, to cause a cancelling effect, resulting in a much lower overall magnetic field. This results in lower EMI. In one embodiment, synchronously switched transistors are divided up into parallel topside transistors and parallel bottomside transistors. The topside transistors are positioned to oppose the bottomside transistors, and bypass capacitors are connected between the pairs to create a plurality of current loops. The components are arranged to form a mirror image of the various current loops so that the resulting magnetic fields are in opposite directions and substantially cancel each other out. Creating opposite current loops may also be achieved by forming the conductors and components in a figure 8 pattern with a cross-over point.

Abstract: A system and method for improving the prompt dose radiation response of mixed-signal integrated circuits is disclosed. An internal analog circuit inside a mixed-signal integrated circuit generates an internal analog reference voltage that has been used for various purposes in the integrated circuit. At least one external capacitor is added either internal or external to a device package of the integrated circuit. The external capacitor reduces any change in the internal reference voltage due to prompt dose radiation by stabilizing the internal reference voltage and thus improves prompt dose radiation response of mixed-signal integrated circuits. A much greater value of capacitance may be provided without increase in dielectric rupture suceptability or decrease in manufacturing yield which may be associated with added on-chip capacitance. This increased capacitance primarily reduce the amount of disturbance caused to the internal node during a prompt dose radiation event.

Abstract: Apparatus and systems are provided for a single amplifier filter capable of a high quality factor. A filter comprises an amplifier having an amplifier input and an amplifier output, wherein the amplifier is configured to produce an output signal at the amplifier output based on a signal at the amplifier input. A first resistive element is coupled between an input node and the amplifier input, a second resistive element is coupled between a first node and the amplifier input, and a third resistive element is coupled between the amplifier output and the first node. A first capacitive element is coupled between the amplifier output and the amplifier input. The filter comprises a second node for an inverse of the output signal, wherein a second capacitive element is coupled between the first node and the second node.

Abstract: An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied.

Abstract: A buffer circuit includes a first inverter circuit that inverts an input signal, a second inverter circuit that inverts the output signal of the first inverter circuit, an impedance element connected between the first inverter circuit and the second inverter circuit, a first conductivity type switching element that increases a potential of the output node of the second inverter circuit when the input signal exceeds a first threshold voltage, and a second conductivity type switching element that decreases a potential of the output node of the second inverter circuit when the input signal is lower than a second threshold voltage.

Abstract: A communication device according to an embodiment of the present invention includes a communication antenna that receives a transmission signal where a spectrum spread signal subjected to a spectrum spread is modulated; an intermediate frequency converting unit that converts the transmission signal received by the communication antenna into an intermediate frequency signal having a predetermined frequency; an analog to digital converting unit that discretizes the intermediate frequency signal and outputs a discretization signal; a noise removing unit that detects a noise other than a normal thermal noise included in the discretization signal and removes the detected noise from the discretization signal; and a demodulating unit that demodulates the spectrum spread signal, based on the discretization signal that is output from the noise removing unit.

Abstract: A device for electromagnetic noise reduction in a hybrid automotive vehicle includes at least one sensor that measures a conducted noise generated by at least one noise source, a reducer that reduces a radiated noise, referred to as modified, on a signal of interest made noisy by the modified radiated noise, where the reducer includes a determiner that determines the noise corrected signal of interest from a noisy signal of interest, where the determiner includes an estimator that estimates the modified radiated noise from the conducted noise, and a selector that selects a frequency for receiving a radiofrequency signal.

Abstract: This invention provides a common mode noise cancellation circuit for the unbalanced signals. The unbalanced signals come from a signal source with a first signal terminal and a second signal terminal having a first grounding potential. The common mode noise cancellation circuit comprises a grounding terminal and a subtractor. The grounding terminal with a second grounding potential is electrically coupled to the second signal terminal of the signal source through an impedance unit. The subtractor comprises a first receiving terminal, a second receiving terminal and a signal output terminal. The first receiving terminal and the second receiving terminal are electrically coupled to the first signal terminal and the second signal terminal respectively for receiving the unbalanced signals. The subtractor subtracts the noise coming from the first receiving terminal and the noise coming from the second receiving terminal to reduce the output noise of the signal output terminal.

Abstract: Structures and methods are provided for reducing or eliminating crosstalk in devices. Based on a predetermined compensation schemes, a compensation scheme is selected that minimizes the deviation of the non-aggressed victim signal caused by one or more aggressor signals. Instances of a compensation circuit corresponding to the selected compensation scheme are placed along a victim signal line at locations defined by the compensation scheme.

Abstract: An electronic product includes a case; a first board placed inside the case; and a second board having an Electromagnetic Band Gap (EBG) structure inserted therein. The second board is coupled to an inside of the case facing the first board so as to shield a noise radiated from the first board.

Abstract: Log-likelihood ratios produced by a decoder are incorporated into a soft symbol to soft bit estimation process and are used to perform improved channel estimation and impairment covariance estimation. In an example method, a plurality of soft bits and corresponding probability metrics for a series of received unknown symbols are generated. Estimates of the received unknown information symbols are then regenerated, as a function of the soft bits and corresponding probability metrics. An estimate of the average amplitude of the received unknown information symbols, or an estimate of the propagation channel response experienced by the received unknown information symbols, or both, are calculated, as a function of the regenerated symbol estimates. The results are applied to produce demodulated symbols for a second decoding iteration for the series of received unknown symbols.

Abstract: A system and method receive the output signal from a capacitance diaphragm gauge (CDG) and generate a noise reduced output signal. An input signal processing circuit receives an input signal from a signal source that drives the CDG. The input signal processing circuit generates a segment of N normalized digital samples of the input signal. An output signal processing circuit receives the output signal from the CDG and generates M segments of N digital samples of the CDG output signal and averages the corresponding samples in the M segments to generate a signal segment of N averaged samples. Each of the N averaged samples is multiplied by a corresponding one of the N normalized samples to generate N products. The N products are averaged to generate an average product, which is multiplied by a constant to generate a system output signal with reduced noise.

Abstract: A method includes obtaining an input signal and demodulating phase contamination in the input signal to generate a baseband signal. The method also includes modulating the input signal based on the baseband signal to generate an output signal, where the output signal has less phase contamination than the input signal. The phase contamination could be demodulated using a phase demodulator or a frequency modulation (FM) detector. A portion of the input signal could be down-converted to a lower frequency, and the phase contamination in the down-converted portion of the input signal could be demodulated. Additional phase contamination in the output signal can be demodulated and used to regulate a level of the baseband signal used during modulation of the input signal. The output signal could have less phase noise or period jitter than the input signal.

Abstract: A receiving apparatus includes a symbol timing detection unit, a Fourier transform unit, a first symbol timing correction unit, and an interpolation synthesis unit. The symbol timing detection unit is configured to detect a Fourier transform start position from a received transmitting signal of a symbol unit, the Fourier transform unit is configured to perform a Fourier transform using the detected Fourier transform start position. The first symbol timing correction unit is configured to calculate and correct an amount of change between the Fourier transform start position of a reference symbol and the detected Fourier transform start position, and the interpolation synthesis unit is configured to perform an interpolation synthesis of a plurality of delay profiles corresponding to a plurality of symbols including the reference symbol and a symbol in which the amount of change is corrected.

Abstract: Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.

Abstract: This invention provides a signal processing technique of suppressing various kinds of noise including unknown noise without storing a number of pieces of noise information in advance. To accomplish this, noise information is modified using modification information to obtain modified noise information. The noise in the noisy signal is suppressed using the modified noise information. The modification information is adapted and updated for the result of the step of suppressing.

Abstract: This invention provides a common mode noise cancellation circuit for the unbalanced signals. The unbalanced signals come from a signal source with a first signal terminal and a second signal terminal having a first grounding potential. The common mode noise cancellation circuit comprises a grounding terminal and a subtractor. The grounding terminal with a second grounding potential is electrically coupled to the second signal terminal of the signal source through an impedance unit. The subtractor comprises a first receiving terminal, a second receiving terminal and a signal output terminal. The first receiving terminal and the second receiving terminal are electrically coupled to the first signal terminal and the second signal terminal respectively for receiving the unbalanced signals. The subtractor subtracts the noise coming from the first receiving terminal and the noise coming from the second receiving terminal to reduce the output noise of the signal output terminal.

Abstract: A method and apparatus is provided for reducing interference in a communication system. A feedback-controlled biased inverting limiter is used to reduce interference power by trapping the interfering signal, while passing the wanted signal through to the output. The amplitude trap triples the frequency of a signal component of a particular amplitude, thus shifting it out of the communication band and into the stopband of the receiver or transponder filter. The feedback-controlled biased inverting limiter uses a hard limiter, window comparator, feedback loop, and an exclusive NOR gate to trap the interfering signal, while allowing the wanted signal to pass through to a receiver.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: A data processing method, an equalizer, and a receiver in a wireless communication system including a relay station are provided. The data processing method includes: receiving a base station signal from a base station; receiving a relay station signal from a relay station; determining a propagation delay between the base station signal and the relay station signal; generating an equalizing signal in which interference generated between the base station signal and the relay station signal is alleviated in consideration of the propagation delay; and recovering information bits transmitted by the base station from the equalizing signal. According to an exemplary embodiment of the present invention, it is possible to alleviate performance deterioration due to an interference problem generated in a relay system.

Abstract: A correction spectrum calculation unit 6 obtains a correction spectrum by smoothing an estimated noise spectrum in accordance with the degree of its variations, and a suppression quantity limiting coefficient calculation unit 7 decides a suppression quantity limiting coefficient from the correction spectrum. A suppression quantity calculation unit 9 obtains a suppression coefficient based on the suppression quantity limiting coefficient, and the spectrum suppression unit 10 carries out amplitude suppression of spectral components of an input signal.