Abstract: Methods and apparatus for properly biasing differential comparators are provided. Using a feedback relationship, a bias for a main stage that receives a first differential input of the comparator is produced. Separately, a feedback relationship produces a bias for a main stage that receives a second differential input. These biases, produced as a result of the feedback relationship between bias stages and stages that replicate the main stages, are applied to the main stages. The outputs of the differential comparator are differential outputs with improved common-mode rejection as a result of the feedback and replica biasing.

Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Abstract: A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V? input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

Abstract: An input circuit comprising a level-determining unit and an output unit is provided. In a first period controlled by a first enable signal, the level-determining unit receives an input signal at an input terminal of the input circuit and determines a voltage level of the input signal. The output unit is coupled to the input terminal. In the first period, the output unit outputs the input signal with the determined voltage level at an output terminal of the input circuit to serve as an output signal. In a second period following the first period, the output unit latches the determined voltage level of the input signal according to a second enable signal and outputs the input signal with the determined voltage level at the output terminal to serve as the output signal.

Abstract: A comparator comprises complementary (e.g. NMOS and PMOS) comparator cells having overlapping common mode input voltage ranges which together extend approximately from rail to rail. A digital logic arrangement, including edge detectors, gates, and a latch, is responsive to transitions at the outputs of the comparator cells to set the latch in response to the earliest rising edge and to reset the latch in response to the earliest falling edge. An output of the latch constitutes an output of the comparator. Consequently the comparator is edge-sensitive with a speed optimized for a wide common mode input voltage range. Additional logic gates can provide level-sensitive control of the latch.

Abstract: The invention relates to analog integrated electronic circuits using differential pairs. The proposal is for a method of automatic correction of offset voltage. The inputs (V1, V2) of the differential circuit are short circuited during a calibration phase distinct from the normal usage phase. A capacitor is charged through the difference of the output currents of the branches of the differential pair in this phase. The voltage at the terminals of the capacitor is compared with at least one threshold. During the normal usage phase following the calibration phase, the result of the comparison is kept in memory. In the normal usage phase, a correction is applied depending on the result kept in memory to a current source of a follower stage upstream of the differential pair.

Abstract: There is described a method for increasing an availability and a redundancy of an analog current output as well as an analog current output with increased availability and redundancy. To improve the availability and also the redundancy behavior of an analog current output a first set of current sources is switched to active to generate an output current, one current source respectively of the first set is checked cyclically for serviceability and the other current sources respectively generate the output current in equal parts. Where unserviceability is determined, the corresponding current source is disconnected and removed from the first set. If a malfunction occurs, such as a failure of a current source for example, the output current advantageously does not drop out completely due to the allocation of generation to a number of current sources.

Abstract: A method, algorithm, architecture, circuits, and/or systems for squelch detection in serial communications are disclosed. In one embodiment, a squelch detector can include: (i) a first comparator having first and second inputs configured to receive a differential signal, and a third input configured to receive a signal substantially derived from the differential signal, where the first comparator can provide a comparator output; and (ii) a second comparator that can receive the comparator output and a reference voltage, and may provide a logic level squelch indication. The third input signal may be a common reference signal that is approximately an average voltage of the differential signal, for example. The first comparator may comprise a three-input comparator and the second comparator may comprise a two-input hysteresis comparator, for example. Embodiments of the present invention can advantageously provide a reliable and simplified approach for squelch detection in serial communication applications.

Abstract: A comparator according to one embodiment includes first and second input terminals, first and second output terminals, first and second input inverters, first and second load inverters, and a bias control circuit to provide first and second bias voltages for application to inputs of the first and second load inverters, respectively.

Abstract: A comparator includes a differential pair of transistors providing a first amplification stage and receiving inverting and non-inverting input signals. An output transistor is coupled to the differential pair of transistors providing a second amplification stage and transitioning the output signal state when the non-inverting input signal is larger than the inverting input signal. The output node of one of the differential pair of transistors is connected to an input node of a current-tail transistor. The output node of the other differential transistor is connected to an input node of the output transistor. The other nodes of the differential pair of transistors are connected to each other and are coupled to an output node of the current-tail transistor. The output nodes of the differential pair of transistors and an output node of the output transistor are each coupled to a separate current generator that may include a complex impedance element.

Abstract: The potential comparator includes input wires 3 and 4 that input a differential signal output from a test object 2, a high-threshold side divided-voltage generating section 5 that acquires the differential signal from each of the input wires 3 and 4 and generates and outputs the first divided voltage and the second divided voltage that are a divided voltage based on a predetermined high threshold potential VOH and an electric potential of the acquired differential signal, a high-threshold side potential comparator 6 that derives a magnitude relation between the first and the second divided voltages output from the high-threshold side divided-voltage generating section 5.

Abstract: A comparator, comprising at least one current stage for providing a first current proportional to a difference between first and second comparator inputs, the first current being provided to an amplifier input; an amplifier for amplifying a current provided to the amplifier input and providing a comparator output; apparatus for introducing hysteresis, comprising at least one of a current source and a current sink, the current source being arranged to selectively source a source current to the amplifier input such that the comparator output changes from a first state to a second state when a difference between the first and second inputs rises above a first value, and the current sink being arranged to selectively sink a sink current from the amplifier input such that the comparator output changes from the second state to the first state when the difference between the first and second inputs falls below a second value; and apparatus for controlling at least one of the source current and the sink current to be

Abstract: A data transfer apparatus is composed of a transmitter and a receiver. The transmitter includes an output buffer developing a differential signal in response to a data signal, and an amplitude controller. The receiver includes an input buffer converting the differential signal into a single-end signal, and an amplitude detector developing a feedback signal in response to the single-end signal. The amplitude controller controls an amplitude of the differential signal in response to the feedback signal.

Abstract: A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The differential pair circuit may incorporate a self-biased load and a self-biased current source. The slicer also may include a matched output stage with inverters that provide a rail-to-rail output. Here, the inverters may incorporate components that are matched with components of the differential pair.

Abstract: A direct relationship exists between an integrated comparator's propagation delay and the input differential pair's bias current and overdrive voltage. A new method using a pulsed bias scheme for the input differential pair improves propagation delay by more than one order of magnitude without increasing significantly the average quiescent current, as long as the pulse width of the bias current is small relative to the system clock. A voltage limiter optimizes the comparator's transition time and a built-in hysteresis circuit minimizes spurious output transitions whenever the pulsed bias current pulse changes state. The bias current pulse and sampling of the comparator occur in predefined relation to the system clock.

Abstract: A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector includes a differential amplifier receiving the differential input signal and generating a corresponding pair of differential output signals. The voltage detector also includes a capacitor on which an output signal is generated. A first differential comparator generates a first signal whenever the differential voltage from the differential amplifier is greater than the voltage of the output signal. A second differential comparator generates a second signal whenever the negative of the differential voltage from the differential amplifier is greater than the voltage of the output signal. A current source applies current to the capacitor responsive to receiving either the first or second signal. The amplitude of the feedback voltage is thus equal to the absolute value of the peak differential amplitude of the input signal.

Abstract: A CMOS driving circuit, wherein an output buffer stage with a transistor switch is added to the final buffer stage of a conventional CMOS driving circuit to drive a power transistor. The output buffer stage has two input terminals for DC input voltage, and uses the high voltage of a voltage converting circuit in a multi-voltage system as one DC input voltage. The driving load capacity of the CMOS driving circuit is improved by converting the higher of the two DC input voltages to a modulated driving voltage and outputting it via an output terminal, so that the on-resistance of a power transistor connected with the output buffer stage is lowered, the power consumption of the power transistor is reduced, the output capacity is improved, and the area of the power transistor is lowered with the same output power.

Abstract: A double pole single throw (DPST) switch circuit including a first circuit portion corresponding to a first input port, a second circuit portion corresponding to a second input port, and an output port, wherein each of the first and second circuit portions include at least one first transistor providing a portion of an isolation channel, at least one second transistor providing a portion of a transmit channel, and at least one third transistor for providing a control bias for selecting either the transmit channel or the isolation channel.

Abstract: A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion.

Abstract: Methods and systems are provided for comparing currents. The method includes driving a first current through a first X leg of a first current conveyor circuit and a second current through a second X leg of a second current conveyor circuit. The method further includes draining a third current from a first X terminal of the first current conveyor circuit to produce a first positive transistor current and a first negative transistor current, and draining a fourth current from a second X terminal of the second current conveyor circuit to produce a second positive transistor current and a second negative transistor current. The method further includes summing the first positive transistor current and the second negative transistor current to produce a first current output, the first negative transistor current and the second positive transistor current to produce a second current output, and the first current output and the second current output to produce a summed current output.

Abstract: A method and apparatus for providing a low power low voltage differential signaling driver are disclosed. In an example, a low voltage differential signaling driver circuit is described, comprising a first current source to provide current to a first differential pair of PNP transistors, a pair of transresistance amplifiers driven by a corresponding pair of transconductance stages, a second current source to provide current to a second differential pair of PNP transistors, and an output port having a common mode output voltage and a differential output voltage based on a state of the first differential pair of PNP transistors and the second differential pair of PNP transistors.

Abstract: A circuit and method for comparing and providing a signal indicative of a difference in magnitude between a differential signal voltage and a differential reference voltage.

Abstract: In a conventional circuit to buffer differential clock signals at plural stages, the deteriorations of duty ratios caused by the variations of transistors constituting the circuit have not been compensated. Further, when it is attempted to increase the effect of compensating the duty ratios, the size of the circuit increases and the consumed electric current also increases accordingly. A semiconductor circuit according to the present invention includes: a differential input section to receive input differential signals; differential signal output terminals to output output differential signals in accordance with the voltages input into the differential input section; a low-pass filter to extract the DC components of signals output from the differential signal output terminals; and a load resistor section connected to the differential input section, wherein resistance values are determined on the basis of the DC components of the signals extracted with the low-pass filter.

Abstract: A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion.

Abstract: A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.

Abstract: A differential comparator is provided. The comparator receiving two differential signals and generating a comparison result represented by an output signal on one of two output terminals respectively on two current paths. The comparator comprises two pairs of latch transistors respectively disposed on the two current paths and two pairs of input transistors respectively disposed on the two current paths, wherein gates of the latch transistors on one of the current paths are commonly coupled to the output terminal between the latch transistors on the other current path, gates of the input transistors on one of the current paths respectively receives an input signal of one of the differential signals and a reference signal of the other differential signal and each of the input transistors is disposed between the output terminal and one of the latch transistors on the current path thereof.

Abstract: An imaging circuit using an asymmetric comparator to detect an oversaturated pixel is disclosed. The comparator employs a transistor differential pair which are fabricated to be slightly unbalanced. By varying the channel widths of the two transistors during fabrication, the voltage required to trigger the comparator can be raised or lowered as desired to set an oversaturation level which triggers the comparator.

Abstract: A comparator, comprising at least one current stage for providing a first current proportional to a difference between first and second comparator inputs, the first current being provided to an amplifier input; an amplifier for amplifying a current provided to the amplifier input and providing a comparator output; apparatus for introducing hysteresis, comprising at least one of a current source and a current sink, the current source being arranged to selectively source a source current to the amplifier input such that the comparator output changes from a first state to a second state when a difference between the first and second inputs rises above a first value, and the current sink being arranged to selectively sink a sink current from the amplifier input such that the comparator output changes from the second state to the first state when the difference between the first and second inputs falls below a second value; and apparatus for controlling at least one of the source current and the sink current to be

Abstract: The invention relates to a comparator with a constant duty cycle for high frequency data signals. Such comparators are often part of an integrated circuit and particularly useful in the mobile phone technology. To achieve the desired constant duty cycle for high frequency data signals, the comparator according to the invention comprises a differential amplifier (M1, M2) having differential inputs (IN 1, IN2) forming the comparator inputs and a first and second amplifier output (Vo, Vo?) forming the comparator outputs of a first comparator stage. Further, a first differential current amplifier (A11) is provided and connected with its inputs to the amplifier outputs (Vo, Vo?) and with its output to the first amplifier output (Vo). Finally, a second differential current amplifier (A12) is connected with its inputs to the amplifier outputs (Vo, Vo?) and with its output to the second amplifier output (Vo?).

Abstract: Briefly, in accordance with one or more embodiments, an offset compensated comparator is capable of being utilized for higher speed, lower voltage use. The comparator comprises a cross-coupled latch comprising n type devices and p type devices. The threshold mismatch between n type devices is captured on capacitors coupled to the gates of the n type devices to capture the mismatch between the devices. After the threshold mismatch is captured, the comparator can be used as a typical cross coupled latch.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

Abstract: A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V? input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.

Abstract: A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin?), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref?) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load.

Abstract: The invention discloses a low voltage differential signal (LVDS) receiver, which is realized in an integrated circuit. The LVDS receiver includes: an input stage circuit receiving a full-range common-mode voltage and converting it into a current signal; a current source circuit coupled to the input stage circuit to provide a current source; and a current mirror circuit coupled the input stage circuit and the current source circuit to provide several bias voltage signals for the current source circuit and output a voltage signal to a buffer.

Abstract: A dual mode comparator circuit is disclosed. The dual mode comparator includes a plurality of differential transistor pairs. Each differential transistor pair includes a plurality of inputs and outputs. The outputs of the differential transistor pairs are coupled to inputs of a multiplexor. The multiplexor includes at least one control input for selecting between the multiplexor inputs and provides the selected input to the multiplexor output. The dual mode comparator further includes a comparator back end that is coupled to the output of the multiplexor. The comparator back end may include a folded cascode and additional gain stages. The comparator back end provides the comparator output to the next stage. The dual mode comparator may be used in automatic testing equipment embodiments.

Abstract: An output buffer circuit includes: a differential circuit; and first and second load circuits coupled between the differential circuit and a high power supply voltage VDDH. Such a differential circuit includes first and second NMOS transistors having low-voltage gate dielectric layers susceptible to deterioration at operation above a maximum gate-body voltage VgbMAX (where VDDH>VgbMAX), respectively. Body electrodes & source electrodes are coupled to a common node. Gate electrodes are coupled to first and second differential input signals, respectively, such that voltages on drains of the first and second NMOS transistors represent results of a differential switching operation, respectively. More particularly, the drains of the first and second NMOS transistors are coupled to the first and second loads. The common node is coupled to a bias voltage such that Vgb of the first & second NMOS transistors is VgbMAX?Vgb.

Abstract: A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay device coupled to an input of the second driver and having an input coupled to the input signal node through a first inverter, wherein the first and second delay devices are clocked such that an input signal reaches the first driver simultaneously with an inverted input signal reaching the second driver.

Abstract: Disclosed is a connection arrangement for connecting end portions of differential pairs to pads. In the arrangement, first and second signal traces comprising the differential pair are formed in first and second layers, respectively, of a printed circuit board. Each of the signal traces has a run portion and an end portion. The end portions of the first and second signal traces are connected, respectively, to first and second pads. At the beginning of the end portions in a region of the printed circuit board on a first lateral side of the first pad both the first and second signal traces split into two branches. One branch each from the first and second signal traces traverses a path around a top side of the first pad and the remaining branches from the first and second signal traces traverse a path around the bottom side of the first pad. The branches of the first and second signal traces come together again in a region of the printed circuit board on a second lateral side of the first pad.

Abstract: A circuit for setting a reference voltage in a floating gate circuit is configured as a precise voltage comparator circuit with a built-in programmable voltage reference. Once the one or more floating gates in the floating gate circuit are set during the a SET operation, the floating gate circuit is configured during a READ mode as a comparator circuit with a built-in voltage reference.

Abstract: An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

Abstract: Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.

Abstract: The potential comparator includes input wires 3 and 4 that input a differential signal output from a test object 2, a high-threshold side divided-voltage generating section 5 that acquires the differential signal from each of the input wires 3 and 4 and generates and outputs the first divided voltage and the second divided voltage that are a divided voltage based on a predetermined high threshold potential VOH and an electric potential of the acquired differential signal, a high-threshold side potential comparator 6 that derives a magnitude relation between the first and the second divided voltages output from the high-threshold side divided-voltage generating section 5.

Abstract: A comparator circuit includes a differential amplifier circuit, a latch circuit, and a control signal generating circuit. The latch circuit includes a pair of cross-coupled inverting amplifiers that pull the output signals of the differential amplifier to the high and low logic levels, a control transistor that activates the latch circuit in synchronization with a clock signal, and an equalizing transistor that equalizes the output signals when the latch circuit is inactive. The equalizing transistor is switched on and off by a control signal generated from the clock signal by the control signal generating circuit. The high-level potential of the control signal is lower than the high-level potential of the clock signal. Switching noise at the control electrode of the equalizing transistor is therefore reduced, permitting high-speed operation.

Abstract: A signal transfer apparatus comprises a differential signal generating part which receives an input signal from a positive-electrode side input terminal and an input signal from a negative-electrode side input terminal, and outputs a differential signal obtained from the input signals from both the input terminals; a first selecting part which receives a selection signal from a selection signal input terminal, the input signal from the positive-electrode side input terminal, and the input signal from the negative-electrode side input terminal, and selects and outputs either the input signal from the negative-electrode side input terminal or the input signal from the positive-electrode side input terminal in accordance with a logic of the selection signal and a logic of either the input signal from the positive-electrode side input terminal or the input signal from the negative-electrode side input terminal; and a second selecting part which selects and outputs either an output of the differential signal gener

Abstract: A versatile, programmable, low-cost transmit line driver is provided. The line driver includes a digital-to-analog converter that receives a digital input and provides an analog output. The line driver is reconfigurable between the voltage mode of operation.

Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with programmable hysteresis. Such circuits include a comparator input circuit that receives two inputs to be compared. The comparator input circuit provides a first differential current output based at least in part on a difference between the first voltage input and the second voltage input. The aforementioned circuits further include a hysteresis control circuit that is operable to receive a single programmable voltage input, and to provide a second differential current output based at least in part on the comparator output and the single programmable voltage input. An output circuit is also included that sums the first differential current and the second differential current, and provides a comparator output based at least in part on the sum of the first differential current and the second differential current.