Abstract: Methods and apparatus for properly biasing differential comparators are provided. Using a feedback relationship, a bias for a main stage that receives a first differential input of the comparator is produced. Separately, a feedback relationship produces a bias for a main stage that receives a second differential input. These biases, produced as a result of the feedback relationship between bias stages and stages that replicate the main stages, are applied to the main stages. The outputs of the differential comparator are differential outputs with improved common-mode rejection as a result of the feedback and replica biasing.

Abstract: Current feedback amplifiers circuits that generate common mode (CM) and/or differential mode (DM) currents are provided herein. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: It is intended to provide a signal detection circuit and a signal detection method capable of preventing influences of variations in transistor characteristics, occurrence of yield degradations of the signal detection circuit and capable of detecting differential input signals at high speed. The signal detection circuit 4 comprises an amplifier section 1, a comparator section 2, and an output section 3. Differential input signals and differential reference voltages are differential-amplified by differential amplifiers 10, 11 of identical circuit structure provided in the amplifier section 1. The relationship of degree between differential input signals and differential reference voltages after differential amplification are compared in comparators 12 and 13 of the comparator section 2.

Abstract: A differential audio amplifier includes a differential input stage for producing an output voltage in response to a differential audio input signal. The differential input stage has a first bias voltage and a second basis voltage. A bias compensation module controls the first bias voltage to be substantially equal to the second bias voltage.

Abstract: A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.

Abstract: A signal detector includes, in part, first and second peak detectors, a comparator and an amplifier. The first peak detector generates a first signal in response to receiving an incoming signal. The second peak detector generates a second signal in response to receiving a threshold signal. The comparator generates an output signal representing the detected signal in response to the first and second signals. The amplifier amplifies the difference between the second signal and a reference voltage and, in response, generates a control signal that controls the gain of the first and second peak detectors. Each of the first and second peak detectors optionally include a differential amplifier and a pair of common-gate amplifiers each coupled to one of the output terminals of its associated differential amplifier. An RC network may be coupled to a common terminal of the first and second common gate amplifiers of each peak detector.

Abstract: An electric circuit for providing a selection signal being used to select a control value of a control variable which oscillates, at steady state, about a reference value about a first control value and a second control value with a first period duration comprises a first differential circuit which provides a first current being dependent on a difference between the first control value and the reference value. The electric circuit further comprises a second differential circuit which provides a second current being dependent on a difference between the reference value and the second value and a first node at which a differential current between the first current and the second current is formed. The differential current forms the selection signal indicating if the first control value or the second value is to be selected in order to minimize a difference between the reference signal and control variable.

Abstract: A comparator includes a differential pair of transistors providing a first amplification stage and receiving inverting and non-inverting input signals. An output transistor is coupled to the differential pair of transistors providing a second amplification stage and transitioning the output signal state when the non-inverting input signal is larger than the inverting input signal. The output node of one of the differential pair of transistors is connected to an input node of a current-tail transistor. The output node of the other differential transistor is connected to an input node of the output transistor. The other nodes of the differential pair of transistors are connected to each other and are coupled to an output node of the current-tail transistor. The output nodes of the differential pair of transistors and an output node of the output transistor are each coupled to a separate current generator that may include a complex impedance element.

Abstract: A comparator including an amplifier unit, a latch unit, and a switch unit is provided. The amplifier unit receives and gains an input signal pair respectively and then outputs an output signal pair. The latch unit is coupled to the amplifier unit. During a tracking period, the latch unit is not powered, and during a latching period, the latch unit is powered to latch the output signal pair and then output a logical signal pair accordingly. The switch unit is coupled between the amplifier unit and the latch unit. During the tracking period, the switch unit transfers the output signal pair to the latch unit, and during the latch period, the switch unit separates the amplifier unit from the latch unit, and thereby reducing the influences to the comparator caused by the kick back noise and the offset error.

Abstract: An integrated CMOS circuit with a differential open drain output driver comprises a plurality of differential output stages each having differential inputs and differential outputs, the differential outputs of the differential output stages being interconnected to provide a pair of differential open drain driver outputs, and the differential inputs of the differential output stages being driven by a pair of inverter chains each of which has an input receiving one of a pair of differential input signals and cascaded inverter stages each with an output connected to an input of one of the differential output stages.

Abstract: A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: A low-power multi-level pulse amplitude modulation (PAM) driver, and a semiconductor device having the same, in which the multi (M)-level PAM driver includes a load unit, first and second current sources, a pair of first input transistors, a pair of second input transistors, and a current source controller, where M is an integer greater than 3. The load unit is electrically connected to an output terminal, and the first and second current sources respectively supply a first amount of current and a second amount of current to the load unit. The pair of first input transistors electrically connects the first current source and the load unit in response to a first bit signal, and the pair of the second input transistors electrically connects the second current source and the load unit in response to a second bit signal. The current source controller activates or deactivates one of the first and second current sources in response to the first and second bit signals.

Abstract: Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism latches the result.

Abstract: A voltage comparator contains low voltage devices (e.g., bipolar or MOS transistors) and high voltage devices (e.g., DMOS transistors). The low voltage devices, which cannot sustain a voltage greater than a relatively small range of variation that is substantially less than the range of potential variation of the input voltage, are connected in a differential amplifier configuration to perform precision differential measurements on the input voltage. The high voltage devices are interconnected with the low voltage devices in a manner that enables operating levels of the low voltage devices to move up/down, or ‘slide’, with variations in the input voltage, so that the low voltage devices are effectively immune to high levels of the input voltage.

Abstract: A comparator has first and second current paths, each passing from an input through a transistor, through a current source to ground, the second current path also having a reference voltage drop element coupled in series with the second input. The gates of the transistors are coupled to form a current mirror. The reference voltage drop element enables higher voltages to be input and compared to higher thresholds above an internal supply voltage level without the need for dividing resistors to reduce the input voltage. Avoiding such resistors means the power dissipation and the silicon area used can be kept lower. ESD vulnerability is reduced since the inputs are not coupled to gates of MOS transistors. Overvoltage protection across the source and gate of the second transistor can be added.

Abstract: According to one embodiment, a comparator circuit includes: a plurality of comparator elements connected in parallel between at least one input signal line and at least one output signal line, each of the comparator elements comparing at least one input potential on the at least one input signal line and outputting comparison result to the at least one output signal line; and a switching device capable of setting each of the comparator elements to either an operation state to compare the at least one input potential or a non-operation state not to compare the at least one input potential, the switching device switching the number of comparator elements which are set to the operation state.

Abstract: A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining a second input of the circuit, a second gate connected to the output of the first DGMOSFET and an output connected to the second gate of the first DGMOSFET, the output of the second DGMOSFET being coupled to a second output of the circuit.

Abstract: A differential output circuit first and second transistors forming a differential pair and having control electrodes input with binary signals, a constant current circuit supplying a constant current to the first and second transistors, and a protection circuit protecting the first and second transistors from external noise. The protection circuit has transistors respectively coupled in parallel to the first and second transistors and input with a first power supply voltage, and transistors respectively coupled between a second power supply voltage and first and second output terminals of the differential output circuit.

Abstract: An apparatus comprising a first differential output driver to provide a single ended output voltage in response to an input voltage, a second differential output driver to provide a single ended output in response to the input voltage where the first output voltage and the second output voltage are representative of the positive and inverted input voltage. The apparatus also includes a feedback circuit to monitor the first and second output voltages and apply a bias voltage to at least one of the first and second output drivers to vary the point where the first and second output voltages cross-over as the input voltage changes from a first to a second level.

Abstract: A comparator circuit with reduced current consumption, and other circuits utilizing the same, are provided. The comparator circuit may achieve reduced current consumption by preventing current flow via a switching transistors responsive to the voltage level of the input signal.

Abstract: A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second complementary input signals. The first N-channel MISFET has a source connected to the first input, a gate receiving a power supply potential, and a drain connected to the first output. The second N-channel MISFET has a source connected to the second input, a gate receiving the power supply potential, and a drain connected to the second output. The first P-channel MISFET has a source receiving the power supply potential, a gate connected to the second input, and a drain connected to the first output. The second P-channel MISFET has a source receiving the power supply potential, a gate connected to the first input, and a drain connected to the second output.

Abstract: A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupled to an impedance matching network. The impedance matching network comprises a first terminal and a second terminal. Wherein, the first terminal is coupled to a gate of the transistor, and the second terminal is coupled to a drain of the transistor for providing an operation voltage to the transistor. When a gate of an N-type transistor and a gate of a P-type transistor are coupled with each other, and a drain of the N-type transistor and a drain of the P-type transistor are also coupled with each other, a common impedance matching network is shared with both the N-type transistor and the P-type transistor.

Abstract: A method and apparatus for driving a current switch with a differential drive signal monitors both the temperature of the switch and the current through the switch. The method and apparatus dynamically control the amplitude of the drive signal as a function of the switch temperature and the current through the switch. The result is a significant reduction in base drive amplitude without compromise to offset and linearity performance of the driver. The resulting dynamic performance of the switch is substantially improved.

Abstract: A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation unit for reducing variation width of the linear voltage according to the performance of the transistor, a saturation voltage generating unit for outputting a saturation voltage by using a second supply voltage, and a comparison unit for comparing an output of the first attenuation unit and the saturation voltage.

Abstract: Differential signals are supplied to gates of first and second transistors. One end and a gate of a third transistor are connected to a signal output node. One end and a gate of a fourth transistor are connected to the other end of the second transistor. A fifth transistor is connected between a power source and the other end of the third transistor. A sixth transistor is connected between a power source and the other end of the fourth transistor. A seventh transistor is inserted between the power source and the signal output node. An eighth transistor is inserted between the power source and the common connection node of the second and fourth transistor, and a gate of the eighth transistor is connected to the gate of the sixth transistor.

Abstract: A comparator includes a differential amplifier, and a hysteresis circuit. The differential amplifier amplifies a difference signal corresponding to a difference between input signals. The hysteresis circuit sets up a first transition threshold voltage and a second transition threshold voltage where the second transition threshold is different from the first transition threshold voltage. The hysteresis circuit generates a second signal that makes transition at the first transition threshold voltage when the difference signal changes in a first direction, and makes transition at the second transition threshold voltage when the difference signal changes in a second.

Abstract: A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.

Abstract: An input buffer circuit achieving rail-to-rail operation maintains a uniform common mode output voltage even though an input signal having any voltage level is inputted. The input buffer circuit has a differential amplifier structure receiving two differential input signals. A first input part has a first inverter circuit into which a first differential input signal is inputted, and a second input part has a second inverter circuit into which the second differential input signal is inputted. The first inverter circuit has a first output node connected to a diode structure having an operating current twice the operating current of the first inverter circuit, and outputs a first output signal. Rail-to-rail operation is achieved, and a common mode output voltage is provided uniformly, with reduced current consumption.

Abstract: An output driver is responsive to an input signal and a swing width control signal (TE). The output driver is configured to generate an output signal having a first swing width (e.g., less than rail-to-rail) when the swing width control signal designates a normal mode of operation and a second swing width (e.g., rail-to-rail) when the swing width control signal designates a test mode of operation.

Abstract: In general, the embodiments introduce a pre-charge state between an idle state (when no data in being transmitted) and an active state (when data is being transmitted). In the pre-charge state, both differential signals are pre-charged to the common mode voltage, which is also the crossover voltage. Similarly, an additional pre-charge state is inserted between the active state and the idle state when the signals transition from active to idle. Because both signals for each bit, including the first and last bits, are being driven from the same voltage level, the quality of the first and last bits are improved to be similar in quality to the middle bits.

Abstract: Current feedback amplifiers circuits that generate common mode (CM) and/or differential mode (DM) currents are provided herein. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: A slicer with large input common mode range is provided. The slicer includes an input stage coupled to receive an input signal, a current source for providing current for the input stage, a self-biased load coupled to the input stage to provide an initial output signal, and an inverter for inverting the initial output signal to provide a final output signal. The input stage includes a first circuit including a plurality of transistors and a complimentary circuit including a plurality of transistors. When a low common mode input voltage causes the transistors of the first circuit to turn off, the transistors of the complimentary circuit will take over to accomplish the same task as the first circuit.

Abstract: A method for comparing two signal with increased accuracy by using a reduced offset voltage comparator that has a offset zero mode and amplify mode. Additional comparators are used to indicate when the two signal are close in value. When the signal are close the reduced offset voltage comparator operation is changed from offset zero mode to amplify mode and the two signal are compared.

Abstract: A method for dynamically adapting the biasing current for a fast switching CMOS comparator is achieved. The difference of the two input signals of said comparator controls the comparator's biasing current, where the biasing current is high only when the difference is low and the comparator's switching is likely to happen and where the biasing current is kept low at other times. In a current mirroring circuit, the voltage difference at the comparator inputs controls the mirroring ratio. The biasing current reaches its maximum when the input voltage difference approaches zero. Once the input voltage difference crosses zero and continues to change in the same direction as before, that is after the polarity of the voltage difference changed, the control mechanism alternates the connection of the comparator input signals to the current controlling elements, in order to now reduce the current with a further increase of the voltage difference.

Abstract: A differential output driver capable for selectively switching from an emphasis mode, a non-emphasis mode, and an idle state uses one pull-up device and two pull-down devices per output lead. The pull-up device is preferably always activated, and one or the other or both or neither of the pull-down devices are selectively activated to provide a desired behavior. Neither pull-down device is strong enough to singularly overcome the pull-up device and fully pull down an output lead to an emphasis logic low level. One of the pull-down devices is singularly strong enough to bring an output lead to a non-emphasis logic low level, which is higher than an emphasis logic low level. The other pull-down device is singularly strong enough to pull an output line from an emphasis logic high level to a non-emphasis logic high level. Working together, however, both devices can pull-down an output lead to an emphasis logic low level.

Abstract: A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings.

Abstract: An amplitude limiting value can be set to an intended value of a designer and the dependence of the amplitude limiting value on the temperature can be avoided.

Abstract: A system and method is provided for extending the range of a common mode voltage of a differential comparator. In one embodiment, a differential comparator comprises an input stage with a negative voltage reference node, a first differential input coupled to a first differential pair transistor and operative to receive a first input signal, and a second differential input coupled to a second differential pair transistor and operative to receive a second input signal. The first input signal and the second input signal form a differential input signal. The differential comparator further comprises a common mode sensing circuit interconnected between the first differential input, the second differential input, and the negative voltage reference node. The common mode sensing circuit is operative to sense a common mode voltage of the differential input signal and set a voltage potential at the negative voltage reference node substantially equal to the sensed common mode voltage.

Abstract: A line driver (3) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors (14, 15) for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors (16, 17), each with the differential pair transistors (14, 15) forming a cascode circuit, onto the data transmission line (8, 9) connected to the line driver (3).

Abstract: A below-ground sensor interface amplifier is powered by no negative supply voltage, but the amplifier nevertheless senses an input voltage signal below ground potential. The amplifier outputs an output voltage signal that varies proportionately to the input voltage. For an input voltage beginning below ground potential and increasing past ground potential, the amplifier outputs an output voltage that remains between ground potential and a supply voltage. The output voltage increases proportionately to the increase of the input voltage. As the input voltage increases, a gate voltage on a first transistor begins to increase starting at the input voltage at which a second transistor is forced to turn on. The amplifier senses input voltages more than one threshold voltage below ground potential without using a below-ground supply voltage. The gain of the amplifier, as well as the lower limit and the size of the amplifier's voltage operating range are programmable.

Abstract: A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states.

Abstract: A voltage-controlled oscillator design is disclosed that provides greater tuning range than a prior art differential amplifier design using “varactor” diodes. The design employs CMOS capacitors to replace varactor diodes. The CMOS capacitors are formed from PMOS transistors in which the drain of the transistor is electrically connected to the source of the same transistor, so that voltage-dependant capacitors are formed between the gate-to-source terminals and the gate-to-drain terminals of the PMOS transistor. Secondly, the monolithic inductors employed in the prior art are replaced by “active” inductors: the combination of a resistor connected in series with the gate of an NMOS transistor, where the potential at the drain of the NMOS transistor is held below that of the second terminal of the resistor by at least the threshold, or turn-on voltage, of the transistor. The resistor/transistor combination acts inductively at the frequency of oscillation of interest.

Abstract: A comparator uses two resonant tunneling diodes (RTDs) in series with resistors of the latch element of the comparator. By inserting two RTD diodes in series with resistors, the negative resistance of the first and the second RTD diodes reduces the effective RC time constants of the resistors and latch, leading to a faster regeneration during a latching mode of the comparator than achieved with alternative designs.

Abstract: A signal detecting circuit includes first and second differential amplifiers and a differential exclusive-OR circuit. The first differential amplifier is configured to amplify a differential input signal and to output first positive and inversion phase output signals. The second differential amplifier is configured to amplify the differential input signal and to output second positive and inversion phase output signals. A common mode voltage of the second positive and inversion phase signals is shifted. The differential exclusive-OR circuit is configured to compare the first positive phase output signal and the second inversion phase output signal, and the second positive phase output signal and the first inversion phase output signal, and to output an exclusive logical summation of the comparing results as a positive phase exclusive-OR output signal.

Abstract: The low AC impedance input stage circuit for fast startup applications includes: a first transistor coupled between a first input node and a first output node; a second transistor coupled between a second input node and a second output node, and having a control node coupled to a control node of the first transistor; a third transistor coupled to the first input node and having a control node coupled to the control node of the first transistor; a fourth transistor coupled to the second input node and having a control node coupled to the control node of the third transistor; a first blocking device coupled between the third transistor and a first current source; a second blocking device coupled between the fourth transistor and the first current source; and a bias device coupled between the first current source and the control node of the first transistor.

Abstract: A method of comparing signals includes obtaining first and second signals to be compared and first and second offset cancellation signals, combining the first offset cancellation signal with the first signal to be compared to form a first combined signal and combining the second offset cancellation signal with the second signal to be compared to form a second combined signal, comparing the combined first signal with the combined second signal, and producing an output indicating which of the combined first signal or the combined second signal is greater.

Abstract: An operational amplifier has a bias circuit, a differential amplifier, an output stage, and a feed forward circuit. The bias circuit provides a reference. The differential amplifier is coupled to a pair of input terminals and provides a differential output based on the first and second inputs. The output stage responds to the reference and to the differential output so as to supply a current to an output terminal. The feed forward circuit responds to the differential output in order to increase and decrease current to the output terminal. As a result, the feed forward circuit extends the dynamic range of the operational amplifier.