Abstract: A differential amplifier is configured to receive an input signal whose magnitude is referenced between a reference voltage and a first power supply magnitude. A differential current conducted by the differential amplifier induces current to be conducted by a first current mirror, which in turn induces current to be conducted by a second current mirror. The current conducted by the second current mirror produces an output signal that is referenced between the reference voltage and a second power supply magnitude.

Abstract: Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.

Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.

Abstract: The present invention provides a Differential Signaling line driver including a pre-emphasis circuit, which boosts the output drive current without any delay whenever there is a transition in the input signal to the driver, using the input signal itself to provide the pre-emphasis through a current steering circuit that switches the direction of drive currents to provide a differential output signal. A delayed signal is then used to disable the pre-emphasis after a short period.

Abstract: An input voltage is applied to an inverting input terminal of a comparator having no hysteresis. A first constant voltage is divided by resistors to create a reference voltage. The reference voltage is applied to a non-inverting input terminal of the comparator through a resistor. Only while an output voltage of the comparator is a low level, a predetermined constant current is supplied to a supply point of the reference voltage and a constant current of the same magnitude is absorbed from the non-inverting input terminal of the comparator.

Abstract: An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to accelerate the discharge of parasitic capacitances during a switching operation.

Abstract: A programmable, equalizing buffer is provided having feedback transistors used to vary the transfer function of the equalizing buffer, such that a low pass response of a transmission channel is substantially equalized. A zero in the buffer's transfer function is established by a conductive state of transistors caused by signal feedback. Multiple transistors establish increased flexibility for establishing the location of the zero, while a cascade of buffer stages provides a second order transfer function effective to cancel second order channel effects.

Abstract: A comparator circuit that operates over a wide range of input voltage from Vss to Vdd is offered. This comparator circuit includes a first comparator receiving a pair of differential input signals from input terminals, a second comparator to which a pair of differential outputs of the first comparator is inputted, a current source that provides the pair of differential outputs of the first comparator with a very low current that flows to a ground and a third comparator that receives the pair of differential input signals from the input terminals. A differential output of the second comparator and a differential output of the third comparator are combined to make an output signal. The output signal is received by to an inverter. The first comparator is a P-type comparator while the second and the third comparators are N-type comparators.

Abstract: Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: A voltage monitor circuit for biasing a well region of a CMOS circuit includes a self-biased comparator which compares first (INP) and second (INN) input signals. The comparator includes first (MN1) and second (MN2) N-channel transistors with grounded sources, a drain of the first N-channel transistor and a gate of the second N-channel transistor being coupled to a first output (OUTN), and a drain of the second N-channel transistor and a gate of the first N-channel transistor being coupled to a second output (OUTP). First (MP1) and second (MP2) P-channel transistors are operated to couple the second or first input signal to the second or first output, respectively, by controlling the gate-to-source voltage of the first or second P-channel transistor according to the polarity of a voltage difference between the first and second input signals.

Abstract: A stable, low power consumption signal detecting circuit may include: a delay circuit, which receives a base clock signal and generates multiple versions thereof having time delay relationships thereto, respectively; dual amplifiers, which detect valid ones of input signals by comparing the input signals with reference voltage signals in response to the multiple versions of the base clock signal, respectively; a combining unit, which generates a combination signal in response to output signals of the dual amplifiers; and a sampling circuit, which samples the combination signal according to the base clock signal and generates an output signal.

Abstract: Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: A high gain, highly linear mixer includes an input section, mixing section, at least one tuning component, and at least one stand by current source. The input section is operably coupled to receive an input voltage signal and perform a linear transconductance thereon to produce an input current signal. The mixing section is operably coupled to mix a local oscillation with the input current to produce a mixed current signal. The tuning component is operably coupled to the mixing section and to convert the mixed current signal into a mixed voltage signal that function as the output of the mixer. The standby current source is operably coupled to the mixing section and provides a standby current to the mixing section.

Abstract: An improved signal detector system implementable in a high-speed SerDes receiver core that is able to detect valid signals from noise signals with a much tighter tolerance. The signal detector system improves upon the prior art designs by implementing modifications including: (1) the use of two peaking amplifiers for both (differential) input signals and reference to track and cancel gain variation; and, (2) the reduction of current mirroring stages to cut down current mapping error.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: A half-latch that includes negative feedback circuitry is provided. The negative feedback circuitry causes the steady-state gain of the half-latch to remain high so that the overdrive voltage needed to change the state of the half-latch is significantly reduced. Additionally, the negative feedback is bypassed by capacitors at high frequencies so that the speed of the half-latch is substantially unaffected by the negative feedback.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: The differential input receiver provides constant symmetrical hysteresis over a wide input signal range. The differential input receiver includes a pair of complementary differential comparators having common input terminals, a pair of series connected complementary current mirrors each having source terminals driven by the output terminals of the corresponding differential comparator, a pair of transistors connected in series across each differential pair transistor in each differential comparator to form a potential divider across it, and a pair of series connected inverting buffers connected to a common output of the differential comparators to provide the final output. The individual buffer outputs are fed back to the control terminals of the series connected transistors in a manner that provides positive feedback thereby providing equal rise-time, fall-delay and transition times in the output signal.

Abstract: Methods and systems for increasing gain for an electric circuit may include receiving an input differential signal at a first configured pair of transistors and a second configured pair of transistors. The first and second configured pair of transistors may be inductively loaded. The first configured pair of transistors may be self-biased via the inductive loading. DC current may be generated via the second configured pair of transistors. The first and/or the second configured pair of transistors may be configured as input transconductors. A pair of inductors may be configured for the inductive loading and the configured pair of inductors may be tapped for the self-biasing. If the first configured pair of transistors comprises NMOS transistors, then the second configured pair of transistors may comprise PMOS transistors.

Abstract: A method of reducing electromagnetic interference in a clock generating circuit includes providing a first clock signal pair consisting of a first positive clock and a first negative clock, the first positive clock being substantially 180 degrees out of phase with the first negative clock. The method also includes providing a second clock signal pair consisting of a second positive clock and a second negative clock, the second positive clock being substantially 180 degrees out of phase with the second negative clock. The first positive clock is 180 degrees out of phase with the second positive clock and the first negative clock is 180 degrees out of phase with the second negative clock.

Abstract: An output circuit is provided for outputting, based on a first drive signal, an output signal with an amplitude smaller than a source voltage, comprising: a first type MOS transistor whose gate is impressed with a first drive signal and whose drain outputs a signal; a second type MOS transistor whose gate is impressed with a second drive signal and whose drain outputs a signal; and feedback circuits generating the second drive signal by feeding an output signal obtained by synthesizing the signal outputted by the first type MOS transistor and the signal outputted by the second type MOS transistor back to the gate of the second type MOS transistor.

Abstract: The present invention discloses a skew detection device which can detect a skew of a transistor changed due to a driving voltage, a size and a process variable. The skew detection device includes a first potential level generator for outputting a first voltage, a second potential level generator for outputting a second voltage, a first level shifter for receiving the first voltage and outputting a first shift voltage, a second level shifter for receiving the second voltage and outputting a second shift voltage, and a comparator for comparing the first shift voltage with the second shift voltage. The first voltage is determined according to a drain-source current of a first MOS transistor operated in a linear region, and the second voltage is determined according to a drain-source current of a second MOS transistor operated in a saturation region.

Abstract: Circuitry is provided for converting differential digital data to single-ended digital data. Differential data signals have complementary pairs of signals that are referenced to each other. Single-ended signals are referenced to ground. The circuitry can be used on an integrated circuit to convert incoming differential data from a high-speed communications link to single-ended data for processing by internal logic on the integrated circuit. The operation of the circuitry can be stabilized using load circuitry that reduces temperature effects and jitter in the single-ended data.

Abstract: Disclosed herewith is a semiconductor integrated circuit provided with a differential input circuit that can transmit data signals fast to an internal circuit free from distortion of their waveforms without increasing the subject chip in size. The differential input circuit is provided with a pair of first differential input transistors used to amplify mainly the low frequency components of those input signals and having gate terminals connected to a pair of input terminals that receive inputs of differential signals respectively, as well as a pair of second differential input transistors used mainly to amplify high frequency components of those input signals and having control terminals connected to a pair of input terminals that receive inputs of differential signals respectively through capacitance elements. The pairs of first and second differential transistors are connected to each other through a differential connection point (common source).

Abstract: A method and structure for comparing an input signal to a reference signal using a comparator comprises a circuit for setting a trip point of a rising edge of an input signal according to a value of an external voltage reference; and at least two transistors, in the circuit, for setting a trip point of a falling edge of an input signal, according to a width-to-length ratio of the at least two transistors. Moreover, the at least two transistors comprises a first transistor of length (Lx) and a width of (Wx); and a second transistor of length (Ly) and a width of (Wy), wherein the width-to-length ratio equals (WxLy)/(WyLx). The trip point of a falling edge of an input signal increases (decreases) by increasing (decreasing) the width-to-length ratio.

Abstract: An isolation resistor is inserted in series between a current source and the emitters of bipolar switching transistors in a differential amplifier. The switching transistors may also be MOSFETs. The in-rush current through the resistor, due to a parasitic or added capacitance, creates a certain increased voltage drop across the resistor, reducing dv/dt and thus reducing the transient in-rush current into the capacitor. This results in reduced waveform distortion. Such an isolation resistor between a current carrying terminal of a switching bipolar transistor and a current source may be used in various applications, including an emitter follower.

Abstract: The present invention comprises a pair of circuits (171, 172) within the first stage (100) of an AC signal pre-amplifier. The present invention reduces the current mismatch at the base of the first stage transistors (141, 142, 143, 144) resulting in faster switching times by reducing input stage offset and, hence improving input dynamic range.

Abstract: The intermediate node of a first terminator is connected between a first pair of signal lines transmitting a first differential signal, with one side of a third differential signal as a common voltage. The intermediate node of a second terminator is connected between a second pair of signal lines transmitting a second differential signal, with the other side of the third differential signal as a common voltage. The two intermediate nodes are connected by an intermediate connection. The intermediate node of the first terminator and the intermediate node of the second terminator act as a virtual ground of the third differential signal, enabling matching of the impedance of the terminators related to the third differential signal and the impedance of the signal lines related to the third differential signal. It is thus possible to prevent the reflection of the third differential signal.

Abstract: Programmable differential capacitance is implemented in equalization circuits. The programmable differential capacitance improves the common mode rejection ratio of circuits processing differential signals of various frequencies and voltage swings. Multiple capacitance devices provide the programmable capacitance, which provides an equalization circuit with different, selectable (i.e., programmable) values of capacitance for boosting the transition speed and strength of differential signals processed by the equalization circuit.

Abstract: A pre-driver circuit for use in high speed signaling systems is disclosed. In one particular exemplary embodiment, the pre-driver circuit may comprise an input transistor, an active load, a passive load, and a current source. The input transistor has a gate terminal, a current sinking terminal, and a current sourcing terminal. The active load has a control input coupled to the gate terminal of the input transistor, a current sourcing terminal coupled to the current sinking terminal of the input transistor, and a current sinking terminal. The passive load has a first terminal coupled to the current sinking terminal of the active load and a second terminal coupled to the current sourcing terminal of the active load. The current source is coupled to the current sourcing terminal of the input transistor.

Abstract: According to one embodiment, a locally regulated circuit regulates current flows (IREG and IRG) through the operation of a current mirror (334, 332, 326). The regulated current flows are used to self-generate a common mode voltage (V422) at node (322) and to produce the required bias signals through input stage (302 and 308) and output stage (314 and 316) in response to data input signals (D and D-complement). Cancellation of common mode voltage variation is further enhanced by generating a supplemental current in response to an error signal generated by comparing a desired common mode voltage (VCM) to the actual common mode voltage at node (322). The supplemental current conducted by either of loads (310 and 312) serves to regulate the common mode voltage at node (322).

Abstract: A fast, high-swing driver circuit for driving an electro-optical modulator includes an output stage comprising first and second transistors arranged as a differential pair. The collector of the first transistor is coupled to ground, and its base provides the stage's input. The collector of the second transistor is coupled via an impedance to a supply voltage, and provides the stage's output. A reference voltage is provided to the second transistor's base, which is also AC-coupled to ground. A bias generator provides the second transistor's base voltage, and a second differential pair converts a differential input signal to a single-ended output that drives the output stage's input—preferably via a pair of cascaded emitter-follower stages that serve to present a low impedance. A complete electro-optical modulator driver is formed with the addition of a bias-T network at the output stage's output.

Abstract: A frequency converter includes a transistor pair having a first transistor and a second transistor respectively having collector terminals commonly connected to each other and emitter terminals commonly connected to each other, the commonly-connected collector terminals of the transistor pair being connected to a power supply terminal by way of a first resistor, a third transistor having a collector terminal connected to the power supply terminal by way of a second resistor and an emitter terminal connected to the commonly-connected emitter terminals of the transistor pair, a third resistor having an end connected to the commonly-connected emitter terminals of the transistor pair, and another end grounded by way of a constant current source, and an output terminal connected to the commonly-connected collector terminals of the transistor pair.

Abstract: A differential amplifier for providing common-mode rejection while providing differential-mode amplification includes an active differential amplification element electrically coupled to a first input signal, a second input signal and an output signal. The active differential amplification element is also electrically coupled to a first voltage and to a different second voltage. A passive bias element is electrically coupled to the active differential amplification element. The passive bias element is capable of biasing the active differential amplification element so that the active differential amplification element operates in a saturation mode. The active differential amplification element thereby generates the output signal so that the output signal corresponds to a voltage difference between the first input signal and the second input signal.

Abstract: The differential comparator circuit for receiving an input voltage within a pre-determined range, amplifying the input voltage, and outputting an output voltage is provided. The circuit includes: a first differential comparator for receiving the input voltage within a first range portion of the range, amplifying the input voltage within the first range portion, and outputting the output voltage, a detecting circuit electrically connected to the first differential comparator, wherein a trigger signal is produced by the detecting circuit when the first differential comparator is shut down and is detected by the detecting circuit, and a second differential comparator electrically connected to the detecting circuit for receiving the input voltage within a second range portion of the range, amplifying the input voltage within the second range portion, and outputting the output voltage in response to the trigger signal.

Abstract: A sense amplifier having a synchronous reset capability or an asynchronous reset capability, which is readily implemented and has high speed, is provided. The sense amplifier includes a first sense-amplifying unit which sense-amplifies an input signal in response to a clock signal and generates an output signal, and a second sense-amplifying unit which sense-amplifies a complementary signal of the input signal in response to the clock signal and generates a complementary signal of the output signal. The sense amplifier further includes a first controller which is connected to the first sense-amplifying unit and sets the output signal in response to a reset signal and an inverted signal of the reset signal, and a second controller which is connected to the second sense-amplifying unit and resets the complementary signal of the output signal in response to the reset signal and the inverted signal of the reset signal.

Abstract: An integrated circuit comparator includes a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

Abstract: A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second complementary input signals. The first N-channel MISFET has a source connected to the first input, a gate receiving a power supply potential, and a drain connected to the first output. The second N-channel MISFET has a source connected to the second input, a gate receiving the power supply potential, and a drain connected to the second output. The first P-channel MISFET has a source receiving the power supply potential, a gate connected to the second input, and a drain connected to the first output. The second P-channel MISFET has a source receiving the power supply potential, a gate connected to the first input, and a drain connected to the second output.

Abstract: In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.

Abstract: Pre-emphasis is given to differential output signals emanating from a pair of output nodes by initially (after an input data signal transition) connecting at least two current circuits to only one of the nodes. After a time delay, one of the current circuits is switched to connect only to the node to which the current circuits were not previously connected if there has been no further transition in the input data signal during the time delay. If only single-ended (i.e., non-differential) output is desired, only one of the output nodes is used as an output signal source. More than two current circuits may be used, and their switching from one node to the other may be performed progressively to provide pre-emphasis having any of many different characteristics.

Abstract: A semiconductor integrated circuit includes first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range, third and fourth field-effect transistors which are controlled by the on/off states of the first and second filed-effect transistors, a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors, and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal.

Abstract: A hysteresis circuit for use in a comparator having a first and a second transistors as an input stage and a constant current source. The hysteresis circuit comprises a first resistor disposed between a source of the first transistor and the constant current source and a second resistor disposed between a source of the second transistor and the constant current source, and comprises a first and a second current generating means. The first current generating means supplies a current to the source of the first transistor and derives a current out from the source of the second transistor if an output signal of the comparator is a first logic value, while the second current generating means supplies a current to the source of the second transistor and derives a current out from the source of the first transistor if the output signal of the comparator is a second logic value.

Abstract: A method and apparatus for interface signaling using single-ended and differential data signals improves performance of an interface. A differential pair of data signals and at least one single-ended data signal are transmitted over the interface. The differential pair of data signals is received by a differential receiver and the single-ended data signals are received by a receiver that uses the differential pair of data signals to improve the detection of the single-ended data signal. A novel receiver having a differential input and a single-ended input combines the differential pair of data signals with a single-ended data signal to detect the single-ended data signal providing improved common-mode rejection and reducing the error rate of the single-ended signal. Multiple single-ended signals may be associated with one differential signal, providing a scalable architecture grouping a number of single-ended signals with each differential pair of signals.

Abstract: A sensor signal output circuit includes a first differential amplifier, a first load resistor, a first transistor, a second transistor and a limiter section. The limiter section includes at least a second differential amplifier, which includes an input end coupled to output terminal and an other input end coupled to second reference voltage setting part, a second load resistor for a second differential amplifier, and a third transistor, which includes a gate connected to an output end of the second differential amplifier and a source connected to a gate of the second transistor.

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

Abstract: A comparator and method for detecting a signal using a reference derived from a differential data signal pair improves performance of an interface. A differential pair of data signals and at least one single-ended data signal are transmitted over the interface. The differential pair of data signals is received by a differential receiver and the single-ended data signals are received by a receiver that uses the differential pair of data signals to improve the detection of the single-ended data signal. A novel comparator circuit provides the comparison, using a voltage or current level of the single-ended signal to determine states of the differential data signal pair.

Abstract: A differential receiver circuit on an integrated circuit consumes substantially no standby power, has constant propagation delay regardless of the input common mode bias, has acceptable common mode rejection and includes first and second pass circuits and buffers to receive differential input signals. The first pass circuit provides a true output signal based on a differential between the “true” buffered signal and the complimentary buffered signal. The second pass circuit provides a “complementary” output signal based on a differential between the complimentary buffered signal and the “true” buffered signal. The differential receiver circuit rejects common mode biases that may be present on the received differential signals without varying propagation delay times.

Abstract: The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage includes a third p-type MOSFET for transmitting a signal, and a fourth n-type MOSFET of the current source circuit. The differential amplifier further includes fifth and sixth n-type MOSFETs respectively series-connected to the first and second n-type MOSFETs. The output stage further includes a seventh n-type MOSFET series-connected to the fourth n-type MOSFET. The gates of the fifth, sixth, and seventh n-type MOSFETs are connected to voltage bias circuits. The fifth, sixth, and seventh n-type MOSFETs suppress variations in voltage at an output node caused by poor saturation characteristics of the first, second, and fourth main n-type MOSFETs.