Abstract: The coupled switching transistors of the digital current switch are connected to a controlled current source. Load resistors of the current switch are formed as controlled resistors. The L-level produced by a reference current branch is compared with a predetermined level by means of a regulating device which includes the reference current branch and a compensator, and the controlled resistor or the controlled current source are adjusted such that the L-level is equal to the predetermined level.

Abstract: Data transmission circuitry 200 is disclosed which includes a transmission line 201, driver circuitry 202, and receiver circuitry 206. Driver circuitry 202 is coupled to transmission line 201 and sets transmission line 201 to a low transmission voltage level during transmission of information of a first logic state and sets transmission line 201 to a higher transmission voltage during transmission of information of a second logic state. Receiver circuitry 206 compares the voltage on transmission line 201 with a static reference voltage which is a predetermined fraction of the higher transmission voltage and in response latches an output to a corresponding logic state. Receiver circuitry 206 latches the output in an output high logic state to an output voltage which is a multiple of the higher transmission voltage.

Abstract: A low power integrated current source (ICS) for monitoring the voltage at an input terminal includes a current source and a network of current mirror circuits coupled to the current source, to the input terminal and to an output terminal. The circuit monitors the input voltage by comparing the input current with a reference current determined by the current source. The current mirror network responds to a predetermined voltage (current) at the input terminal to switch the output voltage at the output terminal from a first voltage level to a second voltage level. The ICS voltage monitor circuit limits the maximum value of the input current as the input voltage increases beyond a given voltage level thereby limiting the power dissipation. The trip voltage can be reset by merely changing the reference current supplied by the current source or by changing the value of an input resistor whose purpose is to convert the input voltage into an input current.

Abstract: A voltage level triggered ESD protection circuit is immune to standard signal transitions up to approximately 5.5 volts, does not consume any DC current either in the powered up or powered down states, and is interfaceable to a live bus when the system it is connected to is powered down. The trigger circuit is reliably immune to tripping from applied fast bus transitions on a powered-down integrated circuit. The trigger signal is generated in response to sensing both a voltage transition and to reaching a voltage set point such as 7 volts, rather than merely triggering off the voltage transition.

Abstract: A signal detector circuit in a data receiver including a programmable hysteresis circuit for setting and detecting the presence of both a threshold minimum data signal level and a reset signal level higher than the minimum signal level.

Abstract: A semiconductor integrated circuit comprises an input signal terminal to which an input signal is supplied from an outer unit, a plurality of input voltage sensing circuits each having a different circuit threshold value and connected to the input signal terminal, for sensing whether a voltage of the input signal is higher or lower than a predetermined normal level, a power supply voltage sensing circuit for sensing whether a power supply voltage applied from another outer unit is a normal power supply voltage or a voltage different from the normal power supply voltage, a selection circuit for selecting a corresponding one from a plurality of the input voltage sensing circuits in accordance with an output of the power supply sensing circuit, and an internal circuit to which an output of a selected one of the input voltage sensing circuits is connected.

Abstract: A high resolution digital phase detector adapted to receive a threshold value and a sequence of digital samples of a substantially linear portion of an analog video signal. A first output signal is provided when a digital sample is detected as having crossed the threshold value. An interpolation is done between the value of the digital sample to first cross the threshold value and the immediately preceding digital sample on the opposite side of the threshold value. In such manner, the time of the crossing within the sample interval is resolved to a subpixel level. A second output signal represents a fractional phase error between the actual crossing and a desired crossing point within the sample interval. The first and second signals are added in a phase locked loop to adjust the output of a voltage controlled oscillator to be synchronized to the incoming analog video signal in both integer and subpixel phase.

Abstract: A stage of both input and output configurable for operation with low and high voltages, comprises:first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, the first terminal of the second transistor (M2), and a drive circuit means, the second terminal and control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to the drive circuit means, the first and second terminals and control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, the circuit node (A), and the drive circuit means;at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); andan input circuit (3) having a first input terminal connected to

Abstract: A data slice circuit is provided for slicing the caption data or the likes included in a television signal at an optimum voltage. A product between a clock-run signal sliced by a comparator at a tentative reference voltage and a clock signal which is 16 times the clock-run signal is stored in a shift register as 16 bit information, and out of them, only the 8 bits around its center are taken in a duty-factor check block, thereby judging the suitability of the slice level. Based on the result obtained, the value of the counter is increased or decreased, and it is taken as a renewed reference voltage through a pulse width conversion circuit and an integration circuit. Also with data sliced by a renewed reference voltage, the check is executed similarly, and a slicing action at an optimum level is achieved.

Abstract: A circuit which is particularly useful as a chip initialization signal generating circuit for initializing the circuits of a semiconductor memory device includes a time delay circuit for generating a second signal a predetermined time after a first signal, e.g., a power supply voltage, is applied thereto, a first inverter for generating a third signal having a first logic level when the second signal is below a trip point level of the first inverter, and a second logic level when the second signal is above the trip point level, and, a trip point level raising circuit coupled to the first inverter for raising the trip point level.

Abstract: The present invention provides an integrator 5 with switched hysteresis for inductive proximity switches comprising a reference current source IREF connected between a reference voltage supply rail and a first side of a current mirror, a second side of the current mirror being connected to a proximity switch rectifier, the first side of the current mirror being connected to a capacitor CINT and to one input of a two input comparator, the other input of the comparator being held at a threshold level, wherein a fixed hysteresis current source IHYST is provided in parallel with the current reference source IREF, the fixed hysteresis current source IHYST producing a switchable current which is a fixed proportion of the current of the current reference source IREF, the fixed hysteresis current source IHYST being switched on (off) when a target is detected and off (on) when no target is detected. This invention provides for reduction of effects detrimental to the speed of operation of the switch.

Abstract: A signal processing device for selectively producing as an output signal either a signal corresponding to an input signal r a signal which may be a fixed voltage level for muting purposes or a mixed signal. A current switch composed of pairs of differential transistors switches Among a plurality of current paths in accordance with a difference between the voltage levels of a pair of input signals varying in level in phase opposition to each other, or in accordance with a difference between the voltage levels of a reference voltage and a signal phase input signal. A load circuit composed of a plurality of resistors is connected in series with one of the current paths. A current bypass forming circuit which forms a current bypass of a constant current at a desired timing corresponding to a pulse signal with respect to the current path forming the load circuit effects the generation of an output signal not corresponding to the input signal, that is, a fixed voltage for muting the mixed signal.

Abstract: Current output terminals of first and second current mirror circuits are connected. An input terminal of a third current mirror circuit is connected to a node of the current output terminals of the first and second current mirror circuits. A load circuit is connected between a current output terminal of the third current mirror circuit and a first voltage. An output terminal is connected to the load circuit. First and second currents to be compared with each other are supplied to current input terminal of the first and second current mirror circuits.

Abstract: A circuit for the detection of an open load for a power MOS transistor is designed to operate in a switching mode. The MOS transistor is partitioned into two transistors disposed in parallel. The second transistor has a resistance in the conductive state higher than the first transistor. The circuit includes circuitry for enabling only the second transistor when the current is within a low value range, and circuitry for detecting an open load when the circuit is operating within the low current range.

Abstract: An integrated comparator circuit includes two complementary MOSFETs having main current paths being connected together in a series circuit at a connecting point. An inverter stage has two complementary MOSFETs with gate terminals connected to the connecting point. First, second and third terminals are provided. The first and second terminals are for an operating voltage, and the second and third terminals are for a voltage to be compared. The series circuit is connected between the first and third terminals, and the inverter stage is connected between the first and second terminals. One of the MOSFETs of the series circuit connected to the first terminal and one of the MOSFETs of the inverter stage connected to the first terminal are of the same channel type. The other of the MOSFETs of the series circuit connected to the third terminal and the other of the MOSFETs of the inverter stage connected the second terminal are of the same channel type.

Abstract: The present invention is a closed loop peak detection circuit comprising switching means, comparing means, control means, two current sources, and a holding capacitor. The switching means selectively provides one of a plurality of input signals to the comparing means. The control means is coupled to the comparing means. The control means receives first and second control signals for selecting one of three modes: reset, peak detect, and hold. First and second current sources are coupled to the control means. A capacitor is coupled to the first and second current sources for generating an output signal. The output signal is feedback coupled to the comparing means. The comparing means determines when one of the plurality of input signals exceeds the output signal. The control means enables and disables the current sources in response to the comparing means and to the first and second control signals.

Abstract: A comparator circuit having a signal input and at least one signal output having an ON-state and an OFF-state, wherein the ON-state represents an input signal lying above a pre-given switching level V.sub.s and the OFF-state represents an input signal lying below the switching level V.sub.s. The comparator circuit has two comparators, the signal inputs of which are each acted upon by the input signal, wherein both the comparators are wired together in such a way that a switching on of the first comparator produces a signal corresponding to the ON-state of the comparator circuit and the switching off of the second comparator produces a signal corresponding to the OFF-state of the comparator circuit.

Abstract: A zero-power sense amplifier for implementing a wide or multiple input NOR gate for receiving a product term of a group of array cells in a programmable logic device (PLD). In a sleep mode, or low power mode, the zero-power sense amplifier latches its previous state while drawing negligible power rather than returning to one particular state, such as a low state, as in previous devices, enabling recovery time to be reduced after entering an awake mode. The zero power sense amplifier further reduces recovery time upon powering up from a sleep mode by maintaining the product term voltage close to a threshold input voltage during sleep mode while still drawing negligible power.

Abstract: The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.

Abstract: Pressure detector circuits are disclosed in which a pressure sensor is connected to an amplifier having an output signal. A three state comparator compares the output signal with a first reference voltage to provide a comparison output which is fed back in a feedback path to another input of the amplifier through a low-pass filter. A first controllable circuit source connected in series with the first reference resistor are connected in the feedback path to detect an open or short circuit condition of the pressure sensor. Another controllable current source connected in series with a second reference resistor and a voltage divider are also provided in the feedback path which in combination with the first current source detect breaks and short circuit conditions of the pressure sensor. A switch connected is parallel to a high value resistor having a resistance higher than that of a low value resistor in the low-pass filter is also provided in the feedback path.

Abstract: An apparatus for setting a threshold voltage for determining bit positions of digital data stored on an optical recording device utilizing pulse width modulation. The optical recording device reads a pattern from an optical medium. The read pattern has a fixed, known duty cycle. A feedback circuit processes the pattern according to an initial threshold voltage. The feedback signal is then input to a comparator. The comparator compares the feedback signal against the pattern. Based on this comparison, the amount of current input to and output from a compensation circuit is adjusted. Thereupon, the compensation circuit sets the threshold voltage accordingly.

Abstract: A power-on reset circuit is provided which holds an integrated circuit device in a reset mode until at least two conditions are satisfied: supply voltage Vcc must be above a specified value and sense amplifiers in the device must be able to operate properly. Delay circuits and Schmitt trigger circuits also improve the stability of the signal which releases the device from its reset mode.

Abstract: A method for tracking a received signal comprises the steps of setting (635) a counter (130) to a first value indicative of a first signal voltage, determining a center threshold of the received signal, and determining a number of center transitions of the received signal within a predetermined time period. The method further comprises the step of automatically decrementing (685, 695) the counter (130) to a second value indicative of a second signal voltage in response to expiration of a predetermined amount of time, wherein the second value differs from the first value by a predetermined amount determined by the number of center transitions of the received signal within the predetermined time period.

Abstract: A comparator circuit includes a first amplifier stage whose input can be selectively connected to an input voltage and to a reference voltage. A second amplifier stage is connected to the output of the first amplifier and a final stage is connected to the output of the second amplifier stage, at which a rectangular signal is output. The rectangular signal represents times in which the input signal is higher or lower than the reference signal. Both amplifier stages include a first input capacitance having one plate connected to the input of that stage. The other plate of the capacitance is connected to the gate of a transistor and a control switch. Low power dissipation is realized in the circuit by including a follower cascaded with an inverter. This structure allows the same operation as the prior art but offers a better design flexibility since all design parameters are free to be rearranged to achieve the required performance.

Abstract: A power-on reset circuit includes a differentiator circuit, a sample-hold circuit and a reset signal generating circuit. The differentiator circuit differentiates a clock signal from an oscillator after a power supply is applied to a power supply terminal. The sample-hold circuit samples a power component only from the output of the differentiator circuit. When the power component exceeds a threshold voltage of the reset signal generating circuit, the reset signal generating circuit generates and provides a reset signal for a logic circuit during a certain period.

Abstract: Two edge detectors (12, 13) at the input (10.1) and the output (10.2) of a delay line (10) of the edge detector arrangement (11) generate detection signals of identical shape at the detected signal edges of a signal traveling over the delay line. The delay time of the delay line is selected so that the two detection signals partly overlap in time. A subtraction arrangement (16) generates, from the two detection signals, a difference signal that contains, in the overlap region, a zero crossing that can be detected by a zero crossing detector (17). At the time of this zero crossing, the zero crossing detector generates the switching edge of an edge detection signal that controls, for example, a signal switcher (9).

Abstract: A power supply voltage level detecting circuit includes a reference voltage generating circuit for generating a constant reference voltage independent of a power supply voltage, a to-be-compared voltage generating circuit for generating a voltage to be compared changing dependent upon the power supply voltage, a current mirror type differentially amplifying circuit for amplifying differentially the reference voltage and the voltage to be compared, and a determining circuit for generating a level detecting signal indicating whether or not the power supply voltage has attained a predetermined level in accordance with an output of the differentially amplifying circuit. The to-be-compared voltage generating circuit generates the voltage to be compared by dropping the power supply voltage using the resistance division or the forward voltage drop of diode.

Abstract: A system provides a uniform delay in crossovers in opposite directions of a variable input voltage relative to a reference voltage. A comparator is included for producing first and second comparison voltages in accordance with the relative magnitudes of the input and reference voltages. A clamping circuit provides first and second clamping voltages. A control circuit produces first and second control voltages dependent upon the individual occurrences of the first and second comparison voltages. The first control voltage is greater by a particular magnitude than the first clamping voltage. The second control voltage is less than the second clamping voltage by the particular magnitude.