Abstract: A voltage controlled oscillator that is a differential ring oscillator type voltage controlled oscillator that, by connecting in cascade differential delay elements to which differential clock signals of a mutually reverse phase are input and controlling the current that flows to the differential delay elements by a bias voltage, controls a delay amount of this differential clock signal, having a phase detection portion that outputs a detection signal by comparing an output voltage of the differential output of any differential delay element and a reference voltage that is set to a voltage that detects an abnormal operation, and a cross-coupled circuit that is provided at each of the differential delay elements and, when the detection signal is input, amplifies the potential difference between the pair of differential output terminals.

Abstract: A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer?1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1 =Fref1/(x?1).

Abstract: In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider. The TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals has a higher frequency and which has a lower frequency. Therefore, for each oscillation frequency band, the frequency comparison is completed in one cycle of the reference signal, allowing an oscillation frequency band selection circuit to detect an optimum oscillation frequency band corresponding to a predetermined PLL output frequency in a short time.

Abstract: The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.

Abstract: A method and apparatus for detecting capacitive devices are disclosed. A circuit including two circuit paths is connected to an oscillator voltage source. Connecting a test capacitive device to a path of the circuit modifies the electric potential waveform at a point along the path. Passing the first circuit path through a reference comparator and the second circuit path through a phase-shifting comparator produces two output signals that are phase-shifted with respect to each other when the test capacitive device is functional. Analysis of the output signals allows detection or measurement of the test capacitive device.

Abstract: The oscillating signal generator utilizes a rising edge phase difference and a falling edge phase difference of the input signal and a feedback signal to generate a rising control signal and a falling control signal, and generates an output signal according to the rising control signal and the falling control signal; wherein the feedback signal corresponds to the output signal.

Abstract: A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P1, P2, P3, and P4 which may be represented on a phase plane being divided into four quadrants. A relative phase between a data signal transition edge and a clock phase may be represented by a phasor on the phase plane. The clock phase and frequency may be adjusted by determining the instantaneous location of the phasor and the direction of phasor rotation in the phase plane.

Abstract: A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

Abstract: A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.

Abstract: A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an input signal and a feedback signal. The digital loop filter generates a first control signal according to the first detection signal. The decision circuit generates a divisor value according to the first control signal. The fractional-N PLL generates an oscillation signal according to the divisor value and a reference signal. The frequency divider divides the oscillation signal to produce the feedback signal. The fractional-N PLL includes a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.

Abstract: A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes an input terminal and an output terminal, a loop filter, a digital phase detector, and an analog phase detector. The digital phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output coupled to the loop filter, the digital phase detector is configured to operate at a first phase comparison frequency. The analog phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output alternating current (AC) coupled to the loop filter, the analog phase detector is configured to operate at a second phase comparison frequency. The first phase comparison frequency is different from the second phase comparison frequency.

Abstract: Various embodiments are disclosed relating to techniques to reduce spurs in wireless transceivers. In an example embodiment, a first fractional-N divide ratio for a first frequency synthesizer may be set based on a selected channel. A second fractional-N divide ratio for a second frequency synthesizer may be set to a fixed value independent of the selected channel. The second fractional-N divide ratio may be set to a value that is sufficiently distant from an integer value so as to decrease the likelihood of at least some type(s) of spurs.

Abstract: This disclosure relates to a phase locked loop and a frequency locked loop.

Abstract: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

Abstract: Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the first control current or the second control current; a voltage control oscillator for generating a first oscillating signal or a second oscillating signal according to the control signal; a first frequency divider for generating a first feed back clock signal; a second frequency divider for generating a second feed back clock signal; and a control circuit for switching the first loop or the second loop to generate the control signal. The frequency of the second reference clock signal is higher than which of the first reference clock signal. The control circuit turns on the second loop first and then turns on the first loop.

Abstract: A phase synchronization circuit and an electronic apparatus equipped with the phase synchronization circuit are provided. The phase synchronization circuit includes an oscillation unit, a phase comparison unit, a loop unit, a drive unit, an oscillation control signal unit, and a gain characteristic information obtaining unit. In the phase synchronization unit, a compensation signal is generated based on the gain characteristic information obtained by the gain characteristic information obtaining unit at the time of the usual phase synchronizing operation, and the drive unit is controlled by the compensation signal so that a product of the input signal-oscillation frequency conversion gain at the time of actual operation and the drive signal with which the drive unit drives the loop filter unit is constant.

Abstract: A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divided signal. The low pass filter is coupled to the harmonic locked phase/frequency detector. The voltage controlled oscillator is coupled to the low pass filter and provides an output signal. The frequency divider is coupled between the voltage controlled oscillator and the harmonic locked phase/frequency detector. Frequency of the divided signal is a harmonic frequency of the reference signal.

Abstract: An oscillator controller has a phase frequency detector that compares a reference signal and a frequency-divided signal and outputs a phase difference signal; a charge pump; a loop filter that filters the phase error signal output from the charge pump and outputs an oscillation frequency controlling voltage; a voltage-controlled oscillator; a first counter that counts the number of waves of the reference signal to a desired number and outputs a first flag signal; a second counter that counts the number of waves of the frequency-divided signal to the desired number and outputs a second flag signal; a first comparator that compares the first flag signal and the second flag signal and outputs a frequency comparison signal; and a control circuit that controls the voltage-controlled oscillator, the first counter, the second counter and the frequency divider by outputting signals thereto.

Abstract: A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.

Abstract: In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.

Abstract: A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device operates to reduce the frequency of outputting up-index or down-index; thereby shaping probability distribution to reduce degradation due to mismatching of the CPLF device.

Abstract: The invention represents a parallel and distributed approach to clock recovery based on multiple mutually phase shifted sample clock signals (åS) defining a set of orthogonal clock phases. The phase shifted clock signals are used for obtaining an input data sample representation (åU). Input data transition detection is accomplished by determining, for each one of the above clock phases, whether input data samples within a detection window associated with the respective clock phase include an input data transition vector (I). A corresponding clock selection control signal vector (I) is generated based on the input data transition vector (I) to determine a clock selection master. In order to dynamically extract an output clock signal, to control signal vector (I) is then logically combined with a representation (åS?), preferably a rotated version, of the sample clock vector (åS).

Abstract: A PLL system for generating an output signal according to a first reference signal is disclosed. The PLL system includes a clock generator to generate the output signal according to a phase difference between the first reference signal and the frequency-divided signal; and a phase-shift detector for detecting a position difference between the physical address and an updated logical address of the recording data to generate a phase adjusting signal. The PLL system also includes an adder for updating a detected logical address with a random value to output the updated logical address to the position difference detector; and a phase-controllable frequency divider for generating the frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the frequency-divided signal.

Abstract: A phase locked loop (PLL) circuit automatically corrects the offset of the analog (especially active type) loop filter to improve the stability and precision of the locked clock or frequency signals. In addition to the general PLL circuit configuration having active type loop filter (30), the PLL circuit also has a frequency comparing circuit (42), a DAC controller (44) and a DAC (digital-to-analog converter) (46). In an offset measurement mode, the outputs of phase error detecting circuit (12, 14) and frequency error detecting circuit (18, 20) are cut, respectively, to establish locking in offset measurement locked loop (42, 44, 45, 30, 40). In this case, offset correction code (EDs) are identified and held. In normal mode, DAC controller (44) has offset correction code (ED) input to DAC (46), and DAC (46) sends offset correction signal (EAs) to loop filter (30).

Abstract: A fractional frequency synthesizer, applied to a phase-locked loop, includes a phase detector, a loop filter, a controllable oscillator, a first frequency divider, and a sigma-delta modulator (SDM). The phase detector generates a phase difference signal according to a reference signal and a feedback signal. The loop filter filters the phase difference signal to generate a filtered signal. The controllable oscillator generates the frequency signal according to the filtered signal. The first frequency divider generates the feedback signal by dividing a frequency of the frequency signal according to a dividing factor. The SDM determines the dividing factor according to a control signal.

Abstract: A system and a method for self calibrating a voltage-controlled oscillator (VCO). In the system, a mode controller generates a control signal for each of an automatic band selection mode, an automatic gain tuning mode, and a phase-locking mode, from a frequency comparison result between a reference clock signal and a divided clock signal which is generated by dividing a frequency of an oscillation signal, and thereby controls the VCO, so that the VCO may generate the oscillation signal which is automatically phase-locked in a target frequency with an optimal state.

Abstract: A frequency synthesizer includes a phase locked loop (PLL) for generating a desired frequency. The PLL includes two loop filters. A characterization circuit is included, which is configured to receive a digital word for characterizing the PLL and provide a pre-charge value for pre-charging one of the loop filters to generate the desired frequency. A successive approximation analog to digital (A/D) converter is coupled between the loop filters and the characterization circuit, for providing both (a) the digital word to the characterization circuit, and (b) the pre-charge value to the selected loop filter. The digital word includes n-bits ranging in values from a most significant bit (MSB) to a least significant bit (LSB), and the pre-charge value is formed by the n-bits. The successive approximation A/D converter includes a successive approximation register (SAR) for forming the digital word, and a digital to analog (D/A) converter for forming the pre-charge value.

Abstract: A scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.

Abstract: A PLL is provided, comprising a first divider, a PFD, a loop filter, a VCO, a second divider and a controller. The first divider receives a reference signal and divides the reference signal by R to obtain a divided signal. The PFD compares the divided signal and a feedback signal to generate a compared The VCO selects one of a plurality of operating curves for oscillation based on a selection signal, and generates an oscillation signal based on an operating voltage generated by signal the loop filter. The second divider divides the oscillation signal by N to obtain the feedback signal. The controller operates in an initial mode to recursively determine the selection signal by calculating differences of the feedback signal and the divided signal. When the selection signal converges to stable, the PLL switches to a normal mode to operate on the corresponding operating curve.

Abstract: A phase-locked loop including a phase-voltage conversion unit, a calibration unit, and an oscillation feedback unit is provided. The phase-voltage conversion unit receives a reference signal having a first frequency and a first phase, and a first feedback signal having a second frequency and a second phase, and produces a first adjusting signal based on the first frequency, the second frequency, and a phase difference between the first phase and the second phase. The calibration unit receives the reference signal and the first feedback signal, and produces a second adjusting signal based on a frequency difference between the first frequency and the second frequency through a binary search operation. The oscillation feedback unit receives the first adjusting signal and the second adjusting signal, and has a controllable capacitor array controlled by the second adjusting signal for producing a second feedback signal having a third phase locked to the first phase.

Abstract: To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal.

Abstract: There is disclosed a self-calibrating resistor-capacitor (RC) oscillator in which a resistor has a resistance value varied minimally by temperature change and process variation, a capacitor has a capacitance value selected adequately according to needs, and the resistor and capacitor are configurable as a one-chip by a complementary metal-oxide semiconductor (CMOS) process. The self-calibrating RC oscillator comprises a resistor part including a first resistor having a resistance value reduced with increase in temperature and a second resistor connected in series with the first resistor and having a resistance value increasing with increase in temperature.

Abstract: A clock and data recovery circuit has a voltage controlled oscillator that provides a clocking signal synchronized to a received serialized data. A multiple phase generator converts the clocking signal to a plurality of multiple phased clocking signals. A data capture device acquires the serialized data with each of the plurality of multiple phased clocking signals to create multiple phased data signals. A phase detector determines if the clocking signal is in phase with the recovered serialized data and providing a lead signal and a lag signal indicating whether the clocking signal is in phase with the recovered serialized data. A frequency initializing device assists acquisition of lock of the voltage controlled oscillator to a reference clock signal. A recovered data selector selects which of the multiple phased data signals are to be transferred to external circuitry for further processing.

Abstract: A loop system capable of auto-calibrating an oscillating frequency range includes a frequency error detector, a voltage controlled oscillator (VCO), a voltage input unit, and a switch. The frequency error detector includes a rotational frequency detector, a state machine, and an up-down counter. The rotational frequency detector is used for comparing the reference frequency and the feedback frequency. The state machine is used for determining an auto-calibration state. The up-down counter is used for generating the second control signal or the coarse-lock-state signal. The VCO is used for selecting to operate at one of a plurality of frequency operating curves so as to generate an oscillating signal. The voltage input unit is used for providing a fixed voltage to the VCO. The switch is used for switching the VCO to couple to the voltage input unit or to couple to a fine frequency tuner.

Abstract: A frequency modulated output of a Digital Locked Loop (DLL) is implemented with a Johnson Counter outputting a sample clock and a synchronized digital code at a multiple of the sample clock. The digital code drives a digital-to-analog converter to generate a frequency modulated control signal. The control signal is summed with the center frequency control from the digital locked loop digital filter to provide a frequency modulated center frequency control signal to the DLL oscillator.

Abstract: A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.

Abstract: The present invention provides a tunable oscillator. A voltage-to-current converter receives as input a voltage from a phase-locked loop and outputs a first current. A current-controlled oscillator receives the first current and outputs a frequency responsive to the voltage. A second current is input into the current-controlled oscillator to adjust the gain of the current-controlled oscillator. A third current is input into the voltage-to-current converter to adjust the first current and the gain of the voltage-to-current converter. The second and third current values are set using a two-stage pre-calibration method. During the pre-calibration, a control circuit adjusts and then sets the second and third currents so that the output frequency spans a lock-in frequency range required by the phase-locked-loop over a voltage range spanning voltage tolerance of a loop capacitor of the phase-locked-loop.

Abstract: A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes an input terminal and an output terminal, a loop filter, a digital phase detector, and an analog phase detector. The digital phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output coupled to the loop filter, the digital phase detector configured to operate at a first phase comparison frequency. The analog phase detector included a first input coupled to the input terminal, a second input coupled to the output terminal, and an output alternating current (AC) coupled to the loop filter, the analog phase detector configured to operate at a second phase comparison frequency. The first phase comparison frequency is different from the second phase comparison frequency.

Abstract: A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit, selected configuration information based, at least in part, on a selected frequency of a reference clock signal and a selected PLL bandwidth. The method includes generating an output clock signal, by the PLL circuit, based, at least in part, on the reference clock signal and the selected configuration information. The method includes storing in a storage circuit, a plurality of sets of configuration information corresponding to a range of frequencies of the reference clock signal and a range of PLL bandwidths. The selected configuration information is accessed from the plurality of sets of configuration information according to the selected frequency and the selected bandwidth.

Abstract: A circuit arrangement includes a phase locked loop, having a phase detector on whose output side a phase signal can be tapped off and whose output side is coupled to a charge pump. Furthermore, the phase locked loop includes an oscillator whose input side is coupled to the charge pump and which is coupled at one output for emission of an oscillator signal to a first input of the phase detector. The circuit arrangement further includes a counter whose input side is supplied with an input signal which can be derived from the phase signal, and which is coupled to the output of the oscillator. The counter emits an output signal from the counter as a function of a value which represents a pulse length of the phase signal.

Abstract: A phase locked loop circuit includes an oscillator, a dividing circuit coupled to the oscillator having a controllable dividing factor, and a rangefinder circuit coupled to the dividing circuit. The rangefinder circuit is configured to control the dividing factor in response to an operating characteristic of the phase-locked loop circuit.

Abstract: Phase-locked loop fast lock circuit and method are described. The apparatus including a voltage controlled oscillator, a control loop filter having a capacitor and at least one resistor, and first and second control elements coupled with the control loop filter. The first control element may include a charge pump coupled to a node between the resistor and the capacitor of the control loop filter, and a frequency detector coupled to the charge pump.

Abstract: A charge supplying apparatus in a frequency synthesizer includes first and second charge supply units. The first charge supply unit is activated for generating a first voltage coupled to a loop filter, and the second charge supply unit is activated for generating a second voltage coupled to the loop filter. A control unit has a mode determining unit that activates one of the first and second charge supply units from comparing a reference frequency with an output frequency. The mode determining unit also generates at least one control signal for adjusting the first voltage by binary increments for decreasing a difference between the reference and output frequencies.

Abstract: This disclosure is directed to a communications device having a comparator that receives a signal associated with an output and produces a signal associated with a difference between a reference signal and the output signal. A loop filter is coupled to the comparator and accepts the difference signal. An oscillator is coupled to the loop filter and accepts the loop filter signal. It produces a signal with a frequency-characteristic in response. The oscillator can operate at a plurality of segments. A segment selection circuit is coupled to the oscillator. It determines which segment will be selected based upon a signal associated with an expected frequency characteristic, and outputs a signal associated with the particular segment. In response, the oscillator can then change its operational state to the particular segment. An amplification circuit is coupled to the oscillator, and produces an output signal with the particular frequency characteristic.

Abstract: A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.

Abstract: A spectrum analyzer corrects for internal frequency errors in a reference oscillator using a timing control signal. The reference oscillator provides a reference signal at a reference frequency. An error detection circuit determines an error in the reference frequency using the timing control signal and produces an error correction signal for use by a frequency conversion device in adjusting an output frequency thereof to compensate for the frequency error in the reference frequency.

Abstract: An integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.

Abstract: A method for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

Abstract: An apparatus for generating an output signal having a particular frequency includes an oscillator, a first tuning module, and a second tuning module. The oscillator generates an output signal associated with an output frequency. When coupled to the oscillator, the first tuning module is capable of inducing, within a first amount of time, a change in the output frequency of a particular magnitude. When coupled to the oscillator, the second tuning module is capable of inducing, within a second amount of time, a change in the output frequency of the same magnitude. The second amount of time is greater than the first amount of time. The selector couples a selected one of the first tuning module and the second tuning module to the oscillator based on a difference between a frequency-divided version of the output signal and a reference signal.

Abstract: A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator, a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter.