Abstract: A phase control loop circuit for tuning to a reference frequency signal having a phase lock loop (PLL) circuit being responsive to a reference frequency signal having a reference frequency, said PLL circuit including a voltage control oscillator (VCO) for generating a VCO output, said PLL circuit for generating a PLL output, said phase control loop circuit processing said VCO output to generate an output frequency signal having an output frequency, in accordance with an embodiment of the present invention.

Abstract: This invention describes a method for a component/system level design of an adaptive radio receiver in electronic communication devices (e.g., mobile phones) by providing an automatic digital tuning of a voltage controlled oscillator of a phase locked loop (PLL) instead of a prior-art pre-calibration. A normal PLL for frequency locking is used which does not need any additional pre-calibration blocks to account for different temperatures or any other extreme conditions. If the current switch setting does not allow the locking, i.e., the VCO output signal frequency is still far away from a reference frequency, the PLL “coarse” tuning will cause the switch condition to change and bring the frequency within a reasonable range using an additional phase detector PD2 loop.

Abstract: A low phase noise YIG oscillator based phase locked loop couples an output frequency to a delay line discriminator to provide a phase noise feedback signal to a wideband tuning port of the YIG oscillator. A delay line in the delay line oscillator may be implemented with either a resonant circuit or a bandpass filter of sufficient bandwidth so that the output frequency and phase noise sidebands are not attenuated. The resonant circuit may be implemented as a YIG sphere integrated into the YIG oscillator in the same magnetic path as the YIG sphere in the oscillator circuitry.

Abstract: A voltage-controlled oscillator (VCO) enabling proper gain adjustment with a simple configuration. The VCO includes a first current source for generating a first control current in accordance with the first control voltage and a second current source for generating a second control current in accordance with the second control voltage. A control voltage generation circuit synthesizes the first and second control currents to generate an oscillation control voltage in accordance with the synthesized current. A ring oscillator generates an oscillation signal with a frequency corresponding to the oscillation control voltage. The first current source varies a changing amount of the first control current relative to a change in the first control voltage. The second current source varies a changing amount of the second control current relative to a change in the second control voltage.

Abstract: A PLL circuit is arranged to provide a wide capture range, and to lock the leading edge of the feedback signal with the center of the reference clock pulse. The PLL circuit includes a charge pump circuit, a loop filter circuit, a VCO circuit, a PFD circuit, a phase detector circuit, a frequency comparator circuit, and a multiplexer circuit. The frequency comparator circuit is configured to compare the frequency of the reference clock with the frequency of the feedback signal, and to provide a status signal based on the comparison. The comparison is a determination of whether the frequencies of the reference clock and the feedback signal are within a tolerance window. Further, the multiplexer circuit selects either the PFD output or the phase detector output based on the comparison. The PFD is employed to bring the frequencies of the feedback signal and the reference clock signal within the tolerance window.

Abstract: An automatic frequency controller restores symbols carried on a received signal by a data converter, and uses an in-phase and a quadrature component obtained by phase measurement from the symbol restored by the data converter to calculate first and second phase errors. The first and second phase errors are summed together by an adder to produce a phase error of a waveform more moderate than the first phase error to decrease and increase error correction in the ranges of smaller and larger phase errors, respectively, to elongate a period of positive amplitude to expand the desired range of polarity of the phase error. A multiplier multiplies the result from the summation with a coefficient to normalize it. An integrator integrates the normalized data to produce a control signal for use in restoring the symbols.

Abstract: A clock generator for reproducing data recorded onto an optical disk, and more particularly, an apparatus for stably generating a clock signal synchronized with an input signal and a method of generating a clock signal. The apparatus generating a clock signal includes a voltage controlled oscillator, a phase compensator, a frequency compensator, and an adder. The voltage controlled oscillator generates a clock signal of a frequency that varies with a control voltage signal. The phase compensator receives an input signal and the clock signal, detects a phase difference between the input signal and the clock signal, and generates a first control voltage corresponding to the phase difference. The frequency compensator receives the input signal and the clock signal, detects a frequency difference between the input signal and the clock signal, and generates a second control voltage corresponding to the frequency difference.

Abstract: A clock synchronization circuit (200, FIG. 2) includes a signal selector (202), phase detector (204), and delay line (206). The signal selector compares an external clock signal (220) and a feedback signal (222) to evaluate the jitter present in the external clock signal. When the jitter falls within an acceptable range, the circuit operates in DLL mode. In DLL mode, the external clock signal is provided to the delay line, and the delayed external signal is output (224) from the circuit. If the jitter falls outside the acceptable range and the circuit is locked, the circuit is switched to PLL mode. In PLL mode, a clock signal based on the feedback signal is provided to the delay line, and the delayed feedback signal is output from the circuit. The PLL mode is only allowed to operate briefly before switching the circuit back into DLL mode.

Abstract: A clock distribution system including a first and second phase detector. The first phase detector outputs a phase lead of an output clock signal. The second phase detector outputs a phase lag of a returned clock signal. Circuitry is included that propagates the output clock signal onto a transmission line based on the average the output of the first phase detector and the second phase detector.

Abstract: Some embodiments provide a charge pump to output a first control signal and a second control signal based on a frequency of an oscillating signal and a reference frequency, a switch capacitor circuit to generate a first output capacitance based on the first control signal, a main loop circuit to generate an output signal based on the second control signal, and an oscillating circuit to generate the oscillating signal, the frequency of the oscillating signal based at least on the first output capacitance and the output signal.

Abstract: A self-biased phase locked loop (PLL) circuit includes a charge pump to generate a control voltage, a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage, discharge circuitry coupled to the charge pump to discharge the control voltage, and frequency detection circuitry coupled to the controlled oscillator and the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.

Abstract: A method for generating a signal with a frequency equal to a product of a reference frequency and a real number includes providing an output signal from an oscillator, and performing a first integer division of a frequency of the output signal by a first integer divider to obtain a first intermediate signal. A first measurement signal representative of a time difference between the first intermediate signal and a reference signal having the reference frequency is determined. The method further includes generating a first comparison signal derived from the first measurement signal, and generating a second comparison signal dependent on a period of the reference signal, on integer and decimal parts of the real number and on the first integer divider. The first and second comparison signals are compared to obtain an error signal representative of a time difference between a period of a current output signal and the period of the reference signal.

Abstract: A phase-locked loop (PLL) employs a phase detector (PD) generating an up/down signal based on the phase error between a data signal and a clock signal input to the phase detector. The PD senses excess jitter and extends the loop bandwidth to accommodate such excess jitter. Phase error is derived by sampling of the clock signal and at least one phase-shifted version of the clock signal by the data signal, and a retimed data is generated by the PD by sampling of the data signal by the clock signal. The sampled clocks are employed to generate a modified control signal with greater resolution in detecting the phase error, which, in turn, increases the loop bandwidth.

Abstract: Embodiments of the present invention provide a method of centering an operating band of a voltage controlled oscillator around a desired operating frequency. In one embodiment, an adjustable feedback divider provides for driving an output signal to the top and bottom of the operating band. An adjustable period divider and counter provide a plurality of count values for use in determining a mid-point of the operating band. A capacitance bank provides for selectively adjusting a capacitance of the voltage controlled oscillator, thereby adjusting the operating band.

Abstract: Two first delay signals Q30 and Q34 are generated such that edges thereof are delayed by a first delay time Td1 in relation to the rising edge of a clock signal CLK. Two second delay signals Q32 and Q36 are also generated such that edges thereof are delayed by a second delay time Td2 in relation to the trailing edge of the clock signal CLK. A pulse signal Sout is generated as a result of logic operations performed on the first delay signals Q30 and Q34 and the second delayed signals Q32 and Q36.

Abstract: A PLL circuit for comparing with a phase comparator 1a phase between an input signal and one of multiphase pulse signals CK0DIV to CKNDIV used as a channel clock generated by an output of a controlled oscillator 5, and controlling an oscillation of the controlled oscillator 5 according to a phase difference signal, comprises a frequency fixing circuit 9 for outputting an activating signal PCSTART for the control when the input signal is nearly equivalent to a frequency of the channel clock and has entered into a capture range of the phase comparator and a selection circuit 7 for selecting as the channel clock a multiphase pulse signal of a closest phase to a generating point of the input signal after generation of the activating signal, and the selection circuit 7 decides whether the input signal is advanced or delayed with respect to the channel clock after having selected a multiphase pulse signal as the channel clock and generates either an advance signal or delay signal according to the advance/delay of t

Abstract: A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

Abstract: A PLL frequency synthesizer tunable in small step sizes that comprises: 1) a first PLL circuit comprising: i) a first feedforward frequency divider that receives an F(in) frequency and generates an F1 frequency, where F1=F(in)/P, ii) a first PLL core that receives the F1 frequency and generates an F2 frequency, where F2=(P+&Dgr;p)F1, and iii) a first feedback frequency divider that receives the F2 frequency and generates a first feedback signal having frequency F2/(P+&Dgr;p); and 2) a second PLL circuit comprising: i) a second feedforward frequency divider that receives the F2 frequency and generates an F3 frequency, where F3=F2/(N+&Dgr;n), ii) a second PLL core that receives the F3 frequency and generates an F(out) frequency, where F(out)=(N)F3, and iii) a second feedback frequency divider that receives the F(out) frequency and generates a second feedback signal having frequency F(out)/(N).

Abstract: A phase-locked loop (PLL) includes at least first and second loops, and loop selection circuitry coupled to the first and second loops, the loop selection circuitry being responsive to at least one loop select signal to control transition from an operating mode of one of the first and second loops to an operating mode of the other of the first and second loops. In an illustrative embodiment, the PLL comprises a dual-loop PLL with the first and second loops corresponding to respective frequency and phase loops, and the loop selection circuitry is configured such that the loop select signal as applied to a control input of a current-generating component of the first loop represents a delayed and inverted version of the loop select signal as applied to a control input of a current-generating component of the second loop.

Abstract: A phase comparison circuit for generating control voltages for a number of varactors of a phase locked loop (PLL) circuit has been disclosed. According to a particular embodiment, a number of phase difference detection circuits (101, 102 and 103) can be successively activated in response to a set of activation signals to generate output voltage signals (Vtunei). Output voltage signals (Vtunei) can vary according to an elapsed period time, and thus represent a phase difference. Each phase difference detection circuit (101, 102 and 103) can activate a trigger signal (Trg) when an internal voltage signal equals a predetermined value. A main signal (SIG) can be input as an activation signal to a first stage phase difference detection circuit (101). A trigger signal from a first stage phase difference detection circuit (101) can be input as an activation signal to a subsequent stage phase difference detection circuit (102).

Abstract: In a phase locked loop (PLL) circuit having a function of automatically adjusting the free-running frequency of a voltage controlled oscillator (VCO), the number of pulses of a pulse signal output from the VCO in a period in which a comparison signal output from a phase comparator is at a predetermined level is counted, and a microcomputer updates digital data based on the counted value. The digital data is converted into an analog signal by a digital-to-analog converter. A combiner combines the analog signal with a signal obtained by smoothing the comparison signal of the phase comparator by a low-pass filter so as to generate a frequency control signal of the VCO.

Abstract: A delay-locked loop includes a ring oscillator that generates a plurality of tap clock signals, with one tap clock signal being designated an oscillator clock signal. Each tap clock signal has a respective delay relative to the oscillator clock signal. The oscillator clock signal clocks a coarse delay counter to develop a coarse delay count that determines a coarse delay of a delayed clock signal. A fine delay of the delayed clock signal is determined by selecting one of the tap clock signals of the ring oscillator. The phase between an in put clock signal and the delayed clock signal is determined and the coarse and fine delays adjusted in response to this phase to synchronize the delayed and input clock signals. The delay-locked loop may also monitor rising and falling edges of the input clock signal and develop corresponding rising-edge and falling-edge fine delays to synchronize rising and failing edges of the input clock signal.

Abstract: A frequency acquisition system for a tunable oscillator is provided that generally includes a frequency-locked loop circuit including a detector system, responsive to the frequency of an output signal of a tunable oscillator and the frequency of a reference signal, to provide a digital output signal representative of a difference in frequency between the output signal and the reference signal, a register circuit for storing a value representative of the present control state of the tunable oscillator; and an accumulator circuit responsive to a value representative of the present control state of the tunable oscillator and to the digital output signal for providing an updated value for adjusting the frequency of the tunable oscillator towards the frequency of the reference signal.

Abstract: A phase locked loop includes a difference detector, a loop filter, a controlled oscillation module, and a frequency translation module. The difference detector is operably coupled to determine a difference signal based on phase and/or frequency differences between a feedback oscillation and a reference oscillation. The loop filter is operably coupled to generate a control signal from the difference signal. The controlled oscillation module is operably coupled to produce, in accordance with an adjustable operating parameter, an output oscillation based on the controlled signal. The adjustable operating parameter is set based on desired operating conditions of the phase locked loop such that false locking of the phase locked loop is substantially avoided. The frequency translation module is operably coupled to produce the feedback oscillation from the output oscillation based on a frequency translation rate.

Abstract: In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first and second phase comparator, each with at least three inputs and an output are preset to a predetermined logical value by a first control circuit. A first signal is connected to an input of the first and second phase comparators. A second signal is connected to a second input of the second phase comparator and to the input of a programmable dead zone delay circuit. The output of the programmable dead zone delay circuit is connected to a second input of the first phase comparator. A preset value, determined by the first control circuit, is presented on the outputs of the first and second phase comparators. Until metastability is resolved, these outputs retain a valid fail-safe default.

Abstract: A phase-locked loop system and method are provided. The system may include an error detector configured to receive a reference signal, and a voltage-controlled oscillator subsystem coupled to the error detector. The voltage-controlled oscillator subsystem is typically configured to produce a primary output signal that tends toward a predefined frequency relationship with the reference signal, and to produce a feedback signal that is routed in a feedback loop back to the error detector. The voltage-controlled oscillator subsystem typically includes a multiple output voltage-controlled oscillator having a plurality of VCO outputs. The voltage-controlled oscillator subsystem is typically configured to form the feedback signal from a plurality of the VCO outputs.

Abstract: A phase-locked loop includes a signal reshaper connected between a phase detector and a charge pump. The signal reshaper can be controlled by a controller to reshape the phase error signal based on the difference between the frequency of an output signal, output from a low pass filter, and a target frequency. The signal reshaper outputs a reshaped or unreshaped phase error signal to the charge pump. The unreshaped phase error signal causes the phase-locked loop to lock the frequency of a feedback signal to the frequency of an input signal. The reshaped phase error signal causes the charge pump to output a charge pump signal that synchronizes the frequency of the output signal with the target frequency.

Abstract: The present invention relates to a PLL circuit and a voltage controlled oscillator wherein a clock signal jitter caused when the supply voltage fluctuates of which is small can be supplied, and the voltage controlled oscillator is provided with a MOS transistor to one end of which a first power source (Vss) is connected and to the gate electrode of which a control signal for controlling the oscillation frequency is input, an oscillator connected between the other end of the MOS transistor and a second power source (Vdd) and a capacitative element connected to the oscillator in parallel and is further provided with additive control means for minutely controlling the oscillation frequency.

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator.

Abstract: A Rapid Single-Flux-Quantum (“RSFQ”) encoder output interface device is provided. The RSFQ output interface device includes a variable phase multi-junction voltage controlled oscillator (VCO) that provides multiple clock signals having similar frequencies based on a DC bias current setting. The multiple clock signals are phase shifted from one other based on a flux bias current setting. The clock signals are then mixed together according to logic states of a data stream to provide an encoded output data stream. The encoded output data stream can be in a phase shifted keying (PSK) format. The PSK format can be provided in binary, quadrature or other PSK formats. The Single-Flux-Quantum (SFQ) voltage pulses of the encoded output data stream are converted to a voltage level appropriate for transmitting over a wire.

Abstract: A phase-locked loop circuit has a DLL circuit in a stage preceding an analog PLL circuit. The DLL circuit detects a phase difference between a reference clock signal and a feedback signal, changes the detected phase difference to a phase difference increased so as to be greater than a steady state phase error which the analog PLL circuit has, and supplies the resultant phase difference to the analog PLL circuit. While the phase difference between the reference clock signal and the feedback signal is being detected by the DLL circuit, the analog PLL circuit operates to reduce the increased phase difference to the steady state phase error. As a result, the phase difference between the reference clock signal and the feedback signal is reduced to a sensitivity limit of a phase comparator in the DLL circuit.

Abstract: The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO.

Abstract: A method and apparatus are hereby presented for the purpose of supplying local oscillator frequencies used for upconversion and downconversion of electronic signals for transmitters or receivers. The apparatus contains a voltage controlled oscillator for generating the signal used for upconversion or downconversion, a reference signal, a second oscillator or source locked to the reference signal which is used in a heterodyne loop for the purpose of enabling any arbitrary frequency to be generated, a sampling phase detector which is part of the heterodyne loop, and dividers for dividing the reference signal as well as the heterodyne output of the sampling phase detector. The purpose of the heterodyne loop is twofold. By reducing the frequency by means of heterodyne action the divider ratio can be kept small, thus reducing the phase noise. Also, the heterodyne technique permits the synthesis of any arbitrary frequency, through the choice of the appropriate heterodyne frequency.

Abstract: A recording clock generation circuit includes a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal; a first filter for smoothing an output from the first phase comparator; a VCO circuit for oscillating in accordance with the output smoothed by the first filter; a frequency divider for dividing a frequency of an output from the VCO circuit; a phase adjusting circuit for adjusting a phase of an output from the frequency divider; and a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.

Abstract: In a PLL device with a plurality of phase comparators, when one phase comparator has reached a locked state, this phase comparator is allowed to keep on delivering an output, while outputs of the other phase comparators are disabled. Accordingly, power consumption can be reduced. Furthermore, an error current output from a charge pump (109) connected to the phase comparators to output an error signal is reduced when lock approaches. Accordingly, lock failure can be avoided. Furthermore, a time constant of a low-pass filter (220) that receives the output of the charge pumps connected to the phase comparators is altered following alteration of the number of the phase comparators (212 to 219) that deliver their outputs. Accordingly, power consumption can be reduced, and also stability and converging speed are improved. Using distribution means (318) instead of frequency dividers provided for the phase comparators individually makes LSI implementation easy.

Abstract: An oscillation frequency of a VCXO is controlled based on a phase difference between a reference phase signal outputted from a reference phase generation circuit and a feedback phase signal outputted from a feedback phase generation circuit, an oscillation frequency of a VCO is controlled based on a phase difference between an output clock of the VCXO and an audio clock obtained from a divider circuit, and a clock outputted from the VCO is determined as a restored audio clock.

Abstract: A low-jitter phase-locked loop (PLL) circuit includes a reference signal generator and a PLL. The reference signal generator is configured to quadruple a frequency of a first reference signal to produce a second reference signal. The PLL includes a filter coupled in series with a voltage controlled oscillator (VCO), and a frequency phase detector configured to generate a first error signal based on a frequency difference between the second reference signal and a first divided VCO output signal. The PLL further includes a phase detector configured to generate a second error signal based on a phase difference between the second reference signal and a second divided VCO output signal at each rising and falling transition of the second reference signal.

Abstract: A phase locked loop system for use with a synchronous dynamic random access memory (SDRAM) or a multi-rate high speed serial transmission buffer is disclosed. The invention includes a phased lock loop having a control voltage for controlling a voltage-controlled oscillator (VCO) that is adjusted, based upon whether the control voltage is within a specific voltage range and whether the VCO frequency is within a specific frequency range. If the control voltage is greater than a voltage maximum and the frequency is not beyond a frequency maximum, the VCO sensitivity is increased. If the control voltage is less than a voltage minimum and the frequency is not below a frequency minimum, the VCO sensitivity is decreased. This ensures that any signal noise or jitter does not have a proportionately large portion of the signal, and therefore minimizes its effect.

Abstract: A clock and data regenerator for different data rates including a control loop which is controlled by a phase discriminator (PD) and two frequency discriminators. The first frequency discriminator enlarges the catchment range of the control loop. The second frequency discriminator determines the ratio of the bit rates of the clock signal and of the data signal. The second frequency discriminator sets the loop frequency divider appropriately, and supplies a control voltage for setting the oscillator until the first frequency discriminator can carry out this function.

Abstract: A frequency detector is configured to provide reliable acquisition by a clock recovery and data regeneration circuit. A preferred frequency detector utilizes the output characteristics of a phase detector to determine a frequency difference between the recovered clock signal and the incoming data signal. The frequency detector then outputs a signal representing the frequency difference to a control device, preferably to a voltage-controlled oscillator (VCO). Upon receiving the frequency difference signal, the control device, preferably operating within a controlled-feedback loop, will begin to adjust the underlying clock frequency to approximate the incoming data frequency.

Abstract: The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO.

Abstract: A system and method have been provided for determining a frequency tolerance between a generated clock and an input data rate. The invention analyzes beatnotes, externally generated through a comparison of clock and input data rates, and an overflow count of the clock. The occurrence of overflow counts, without intervening beatnotes, indicates that the clock and data rate are close in frequency. The occurrence of beatnotes without intervening overflow counts indicates that the clock and data rates are not close in frequency. Hysteresis is built into the system, preventing the system from indicating an out-of-lock condition when the beatnotes immediate follow the an overflow count, or when the system monitors occasional beatnotes.

Abstract: A system and method for clock recovery from an input data stream recovers the clock signal in a manner that preserves the signal strength of the input signal. The measure of signal strength, referred to herein as the “signal strength indicator” is in turn used to normalize the output of a phase detector in a phaselocked loop (PLL), and the normalized signal is used as an input to the PLL oscillator to recover the clock signal from the input data signal. In this manner, the phaselocked loop is used to perform narrow band filtering, while baseband amplifiers are used to compensate for reference signal power variations. In one aspect, the present invention is directed to a clock recovery system for recovering a clock signal from an input data signal. The system comprises a primary phase detector for receiving an input data signal, and for combining the input data signal with a feedback signal to generate a phase difference signal.

Abstract: Disclosed is a PLL circuit that makes fractional frequency division possible without causing spurious components to be produced in the output of a VCO. The PLL circuit comprises a frequency dividing circuit for frequency-dividing the output of a VCO; a phase adjusting circuit, to which are input two clocks of different phases obtained by frequency division performed by the frequency dividing circuit, for producing an output signal having a delay time defined by a time that is the result of internally dividing a timing difference between the two clocks; a charge pump for generating a voltage conforming to a phase difference output from the phase comparator circuit; and a loop filter for smoothing the voltage conforming to the phase difference and applying the voltage to the VCO, wherein the dividing value of the timing difference in the phase adjusting circuit is represented by MF/MD, and an accumulation operation is performed in units of MF every frequency-divided clock.

Abstract: A phase controller is coupled to a voltage-controlled oscillator (VCO) in a feedback configuration, thereby reducing the phase noise introduced by the VCO. As a result, circuits using the VCO, such as phase-locked loops or delay locked loops, will exhibit reduced jitter in the resulting output signals. In one embodiment, the phase controller measures successive actual periods of the VCO output clock, and in response, generates a control voltage representative of deviations in the successive actual periods of the VCO output clock. The phase controller transmits the control voltage to the VCO as a feedback control voltage. The VCO adjusts the actual period of the VCO output clock in response to the control voltage. More specifically, the VCO adjusts the actual period of the VCO output clock such that deviations in the successive actual periods of the VCO output clock are reduced.

Abstract: An apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency. The apparatus generally includes a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal, a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock, and a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal.

Abstract: In order to solve the problem that since a loop filter constant suitable for asynchronous state cannot be selected in the conventional phase frequency synchronism circuit, it takes a long time to synchronize the input data and the clock signal from the asynchronous state, the present invention is to propose a phase frequency synchronism circuit including a phase comparator for generating a voltage according to the phase difference of the clock signal to the input signal, a frequency comparator for deciding if the frequency of the clock signal is higher or lower than the transmission rate of the input signal and generating a binary signal, a synchronous identifying unit for deciding if the input signal and the clock signal are synchronized in their phases and frequencies, a first switch that receives the output from the phase comparator and is closed and opened when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a second switch that receives the output f

Abstract: Is disclosed a method and a relative circuit adapted to transfer to a microwave transmission carrier the angle modulation of an intermediate frequency signal. The conveyor of angle modulation is a PLL (100) which VCO (2) generates the microwave carrier (RF) modulated like the intermediate frequency signal (S4), taken as reference for the phase comparator (10) of the PLL. The comparator receives moreover a copy of the signal generated by the VCO, converted at intermediate frequency (S3) by means of a subharmonic mixer, and it generates an error signal (S5). The PLL comprises further a regulator circuit (101) which maintains automatically constant relation K between the locked band of the PLL and the bandwidth of the reference signal (S4), the lanter being a signal susceptible of band width variations, generally due to the choice of different transmission speeds.

Abstract: A phase detector device and a clock regeneration device for phase centering when incoming data are sampled at a clock rate, which is in particular substantially half the size of the high clock rate of the incoming data, are provided. The device includes a plurality of flip-flops. The phase detector and the clock regeneration device further include correction devices for producing a correction signal. The correction signal can be passed to an integrator in which a control signal for an oscillator can be produced from the correction signal and the output signals of the first, second and third weighting devices. The clock rates of the first and the second clock signals correspond to substantially half the high clock rate. The phase of the first clock signals is shifted by 180° with respect to the phase of the second clock signals.

Abstract: A signal according to a phase difference in a first phase-locked loop is transferred to a power supply line as an operation power supply voltage for a first oscillation circuit included in the first phase-locked loop. The potential of the power supply line is supplied to a second oscillation circuit in a second phase-locked loop as an operation power supply voltage. The second phase-locked loop is used to generate a clock signal phase-synchronized to the input clock signal. Consequently, a clock generator is implemented that oscillates at a central frequency to generate a recovered clock signal even when a variation is caused in a manufacturing parameter.