Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: A frequency comparator includes a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively. The first and second detection signals are output for respective times based on a difference between the frequencies of the first and second clocks.

Abstract: An apparatus comprising a first circuit, a second circuit, and a logic circuit. The first circuit may be configured to generate one or more first control signals having a first data rate in response to an input signal having a second data rate and a clock signal having the first data rate. The second circuit may be configured to generate one or more second control signals in response to the input signal and the clock signal. The first logic circuit may be configured to generate the clock signal in response to the one or more first control signals, the one or more second control signals and a third control signal.

Abstract: An analog phase lock loop circuit having derivative control. The phase lock loop includes a phase detection circuit, main charge pump, a low pass filter, and a voltage controlled oscillator. The derivative control receives error signals from the phase detection circuit and outputs a derivative voltage to the voltage controlled oscillator to be included with the proportional and integral control of the low pass filter.

Abstract: A phase locked loop (PLL) and method for stable clock generation in applications of wide band channel clock recovery performs frequency detection and phase detection with respect to an eight to fourteen modulation (EFM) signal and a PLL clock signal, and adjusts the current based on the results of the frequency detection and the phase detection, thereby generating the PLL clock signal synchronized with the EFM signal. The PLL includes a charge pump, a first low-pass filter, a voltage controlled oscillator and a static phase error controller. The charge pump sources or sinks the current in response to the results of the frequency detection and the phase detection and outputs the result of sourcing or sinking the current. The first low-pass filter low-pass filters the signal output from the charge pump and outputs the filtered result as a direct current control voltage.

Abstract: A PLL circuit includes: a phase comparator for comparing the phase of an input signal with the phase of a reference input signal to output a signal according to the phase difference therebetween; a low pass filter for outputting a low frequency control voltage on the basis of the output of the phase comparator; a voltage control oscillator for controlling an oscillating frequency on the basis of the control voltage; and a characteristic control part for controlling the characteristic of oscillating frequency to control voltage of the voltage control oscillator on the basis of n+1 ranges of first through n+1-th ranges obtained by dividing a variable range of the control voltage by first through n-th (n≧2) thresholds which are different from each other. Thus, it is possible to widen the operating frequency range, and it is possible to inhibit the frequency variation due to noises.

Abstract: A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.

Abstract: A phase frequency detection circuit of a phase locked loop (PLL) for liquid crystal display which compares a phase between an external synchronous signal and an internal synchronous signal from the PLL to generate a phase difference detection signal, including: a dividing circuit for dividing the external synchronous signal and the horizontal synchronous signal; a phase difference detecting circuit for detecting the phase difference between the divided external synchronous signal and the divided horizontal synchronous signal from the dividing circuit; a phase discriminating circuit for discriminating whether the divided external synchronous signal is ahead of the divided horizontal synchronous signal and generating the phase discriminating signal; and a comparison device for receiving the phase difference detection signal from the phase difference detection circuit and the phase discriminating signal from the phase discriminating circuit to generate the phase frequency difference signal.

Abstract: A phase locked loop circuit includes an input comparator (2) capable of generating a deviation signal which can be used for driving an oscillator (5) so as to generate an output signal (CLKOUT) locked to the input signal. The oscillator (5) can operate according to a plurality of characteristics under the control of a control circuit (8) including searching circuits arranged to carry out a first search phase by scanning the family of characteristics admitted for the operation of the oscillator (5) by bands of progressively reduced width, according to a general, dichotomic procedure. Upon completion of this first search phase, additional circuits of fine search are destined to identify the optimum operating point, compensating possible fluctuations of the characteristics.

Abstract: The frequency divider output a2 is provided to the D input of a first D flip-flop and an input clock a1 to a first frequency divider is inversed by an inverter and is then provided to the C input of the first D flip-flop. The first frequency divider output b2 is provided to the D input of a second D flip-flop, and an input clock b1 to a second frequency divider is inversed by another inverter and then sent to the input C of the second D flip-flop. The Q output of the first D flip-flop and the Q output of the second D flip-flop are sent to a phase comparator as the output signal a3 and the output signal b3, respectively. In this way, the frequency divider outputs a2 and b2 are taken into the first and second D flip-flops at a point half behind the input clocks a1 and b2 and are provided to the phase comparator as the output signals a3 and b3.

Abstract: An over-sampling type clock recovery circuit includes a phase difference determining section and a phase adjusting section. The phase difference determining section determines a phase difference between a data signal and a plurality of clock signals using majority determination, to produce a phase adjustment signal. The phase adjusting section adjusts phases of the plurality of clock signals based on the phase adjustment signal.

Abstract: An apparatus comprising a first circuit and a clock circuit. The first circuit may be configured to generate an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal. The clock circuit may be configured to generate the first and second clock signals in response to the output signal.

Abstract: An apparatus for limiting intermediate frequency variation in a multiple conversion phase locked loop includes a reference oscillator and a voltage controlled oscillator (VCO). The reference oscillator generates a first reference frequency, while the VCO generates an output frequency. The output frequency is divided by a first VCO divider and mixed with the first reference frequency to generate a first intermediate frequency. A second VCO divider also divides the output frequency and mixes it with the first intermediate frequency to generate a second intermediate frequency, which is filtered and used to control the VCO. An algorithm processor generates the division constants of the first and second VCO dividers as a function of the reference frequency and the output frequency to limit intermediate frequency variation.

Abstract: A user network interface device for interfacing between synchronous optical network (SONET)/synchronous digital hierarchy (SDH) which is characterized by a continuous stream of frames of data and an asynchronous transfer mode (ATM) characterized by a non-continuous stream of cells of data. The user network interface device includes an integral phase lock loop circuit to recover clock and data from an encoded incoming stream of data. In another embodiment, the network interface device synthesizes a high speed transmit clock from a low frequency reference source.

Abstract: A phase noise optimization circuit (208) minimizes phase noise for a voltage controlled oscillator (VCO) (202). Control circuitry (214) locates a minimum phase noise region for VCO operation based on the slope of the VCO's changing control voltage (206) versus changing bias voltage (204) for a bias voltage range. The control circuitry (214) then adjusts the bias input so that the VCO operates in a region of minimum phase noise.

Abstract: In a phase locked loop, when seeking loop locking the control variable (S2) arriving from the loop filter (54) is not admitted as such to the oscillator's (55) control input, but it is attenuated so that it will vary within a small range at the middle of its range of variation. At the same time, the loop's output frequency (fVCO) is compared to the frequency of an external frequency source (53), which is sufficiently close to the nominal frequency of the input signal. When the regulating element finds that the oscillator's output frequency is not in a predetermined frequency window, it will add to or reduce the additional control (VCO Cntrl) which it supplies to the oscillator's control input. When the oscillator's (55) frequency has entered the frequency window, the additional control is frozen and the attenuation is removed from the control variable (S2) arriving from the loop filter.

Abstract: An architecture comprising a detector, a first pump circuit, a second pump circuit and a comparator. The detector may present a first active operating signal in response to one or more reference signals. In one example, the first active operating signal may be generated in response to a feedback signal having a parameter within a predetermined range. The first pump circuit may be configured to provide a replica pump signal in response to a current adjustment signal and either (i) at least one of the one or more reference signals or (ii) the first active operating signal. The second pump circuit may be configured to provide a voltage control signal in response to the current adjustment signal and either (i) the first active operating signal or (ii) a second, independent active operating signal. The comparator may be configured to provide the current adjustment signal in response to the replica pump signal and the voltage control signal.

Abstract: The invention provides a phase locked loop circuit, a reproduction apparatus and a phase locking method by which a capture range and a lock range can be widened. Before a phase locked loop circuit is locked, an output clock of a voltage controlled oscillator is counted with reference to a reference clock of a quartz oscillator, and an error component between run length limited codes reproduced from a disk and the reference clock is extracted. Then, the PLL circuit is constructed based on a result of addition of the counted value of the output clock and the extracted error component. After the phase locked loop circuit is locked, a phase error of the output clock of the voltage controlled oscillator against the run length limited codes reproduced from the disk is detected, and the PLL circuit is constructed based on the detected phase error.

Abstract: In a phase locked loop (PLL) circuit, a phase comparator compares an input signal and a feed back signal in phase to generate a phase difference voltage signal. A loop filter filters the phase difference voltage signal, and generates a filter output voltage signal. A bias signal generating section automatically generates a bias signal. A voltage controlled oscillating section generates an oscillation output signal based on the filter output voltage signal and the bias signal. The voltage controlled oscillating section generates the oscillation output signal having a same frequency as that of the input signal based on the bias signal. A counter generates the feed back signal based on the oscillation output signal.

Abstract: A master and slave arrangement of processors includes a clock signal synchronization apparatus. The clock signals of two (processor) assemblies in micro-synchronous operation are only allowed to exhibit an extremely slight phase difference. A system clock signal is generated by a voltage controlled oscillator, which is fed by phase detectors with a filter at the output of each phase detector. Switches are provided between the filter output and the voltage controlled oscillator input. The phase detectors compare the system clock signal and a reference clock signal. A delay is provided at the input of one phase detector.

Abstract: In a PLL circuit, a phase comparator compares phases between a data signal train and a regenerated clock generated within the PLL circuit based on a clock with which the data signal train is synchronizing, and outputs a phase error signal. A frequency comparator compares frequencies between the data stream signal and the regenerated clock and outputs a frequency error signal. When the frequency difference between the both is large, only the frequency system loop operates to carry out a frequency pull in operation of the regenerated clock. When the frequency difference becomes smaller than a predetermined value, an operation by the phase system loop is added to carry out a phase pull in operation. When the phase difference becomes a predetermined value, the phase is locked. When the frequency difference exceeds the predetermined value again during the phase locked period, the operation of the phase system loop is suspended and only the frequency system loop carries out the frequency pull in operation.

Abstract: An over-sampling type clock recovery circuit includes a phase difference detecting section, a phase adjusting section and a signal selecting section. The phase difference detecting section detects a phase difference between a data signal and each of a plurality of active sets of clock signals, and generates a phase adjustment signal from a plurality of phase difference data corresponding to the detected phase differences using a majority determination. The phase adjusting section generates N (N is an integer equal to or larger than 2) sets of clock signals and adjusts phases of clock signals of the N sets based on the phase adjustment signal. The signal selecting section selects a part or all of the N sets of clock signals based on the detected phase differences from the phase difference detecting section. The selected sets of clock signals are supplied to the phase difference detecting section as the plurality of active sets of clock signals.

Abstract: An over-sampling type clock recovery circuit includes a phase difference detecting section (TIPD, CP, LFP), a phase adjusting section (VCO, VD, FD) and a signal selecting section (LDEC, SW). The phase difference detecting section (TIPD, CP, LFP) detects a phase difference between a data signal and each of a plurality of active sets of clock signals, and generates a phase adjustment signal from a plurality of phase difference data corresponding to the detected phase differences. The phase adjusting section (VCO, VD, FD) generates N (N is an integer equal to or larger than 2) sets of clock signals and adjusts phases of clock signals of the N sets based on the phase adjustment signal. The signal selecting section (LDEC, SW) selects a part or all of the N sets of clock signals based on the detected phase differences from the phase difference detecting section. The selected sets of clock signals are supplied to the phase difference detecting section as the plurality of active sets of clock signals.

Abstract: The disclosure describes a multi-stage phase comparator and a phase-locked loop incorporating such a comparator. The comparator measures a phase difference between a reference signal and an output signal using a periodic clock. The comparator is a two stage comparator comprising a fine and coarse comparator. The coarse comparator measures the number of full clock periods between a transition of the reference signal and the output signal. The fine comparator comprises a delay line generator that generates a plurality of delayed clocks. The delayed clocks are used to over sample the reference signal to determine a fine phase difference representing a remaining fraction of the clock period, between transitions of the reference and output signals. A phase locked loop using the multi-stage comparator allows for more accurate phase locking.

Abstract: In order to tune a radio receiver (10) to an optimal tuning frequency it is found the critical frequency closest to the current tuning frequency (60) at which the radio receiver loses the locking to the clock frequency of the received signal, and, if necessary (62), the tuning frequency is corrected away from the critical frequency found. The control block (13) of the radio receiver comprises means for adjusting the tuning of the reception part (11) in response to the information (17) indicating whether the locking to the clock frequency is on. The search for the critical frequency may be performed in on or two stages and alternately on both sides of the current tuning frequency or first on one side and then on the other.

Abstract: A Phase-Locked Loop (PLL) system (30) and a method for modifying the output transition time of the PLL system (30). The PLL system has an input stage (36) connected to a PLL (37). The input stage (36) includes a phase detector stage (47), a phase difference threshold stage (48), and a phase difference modification stage (49). The input stage (36) receives a reference input signal and a feedback input signal and determines the phase difference between these two input signals. If the phase difference is greater than a predetermined value, then the input stage (36) decreases the phase difference between the reference input signal and the feedback input signal. If the phase difference is less than the predetermined value, then the phase difference between the reference input signal and the feedback input signal is not modified.

Abstract: The object of the invention is to provide a lock-in process and device for a YIG-tuned oscillator which takes into account ageing and hysteresis of the YIG-tuned oscillator. This object is attained in that during a predetermined frequency change, the frequency of the YIG-tuned oscillator (1) is preset by means of a microprocessor (17) that progressively changes the current (I.sub.SP) in the main tuning coil (13) of the YIG-tuned oscillator (1) by an iterative capture routine, until the capture range (.DELTA.FM) of the switched-on frequency-locked loop, which changes with the coil current (I.sub.SP), includes the new operating frequency (f.sub.SET). The switched-on frequency-locked loop then pulls the oscillator frequency into the capture range of the PLL and the PLL locks-in the oscillator frequency to the new operating frequency (f.sub.SET). The microprocessor (17) interrupts the capture routine when a PLL-LOCK detector (11) announces to the microprocessor (17) that the new operating frequency (f.sub.

Abstract: A frequency and phase locking apparatus for a phase alignment of a plurality of temporal frames, such as synchronous optical network (SONET) frames, includes a phase locked loop 6 coupled to lock the phase of the first frame, a first frame device 8a capable of receiving the first frame and coupled to provide a synchronous frame frequency to the phase locked loop 6, subsequent frame devices 8b . . . 8n capable of receiving frames subsequent to the first frame, and a drop clock device 22 coupled to the subsequent frame devices 8b . . . 8n to set the phases of the subsequent frames in alignment with the phase of the first frame.

Abstract: The present invention provides an apparatus for setting the free-running frequency of a VCO to a reference frequency. The apparatus comprises frequency range means for setting the VCO within a VCO frequency range among a plurality of VCO frequency ranges. First counting means are operable to count to a first value at the VCO frequency rate and to provide a first ending signal when the first value is reached. Second counting means are operable to count to a second value at the reference frequency rate and to provide a second ending signal when the second value is reached. The second counting means are also operable to provide a reference count value when the first value is reached by the first counting means. A state machine is responsive to the first and second counting means for selecting a VCO frequency range among the plurality of VCO frequency ranges such that the VCO free-running frequency obtained through the selected range gives the closest value to the reference frequency.

Abstract: In a phase-locked loop with reference, feedback, and error signals, the trade-off between lock-up time and power dissipation is improved by one of the following methods: supplying a continuous error signal, instead of an intermittent error signal, to a charge pump during lock acquisition; employing a half-integer frequency divider and making multiple phase-and-frequency comparisons during each reference signal cycle; employing a prescaled feedback signal and making multiple phase-and-frequency comparisons during each reference signal cycle; providing multiple feedback loops and employing a selectable number of the loops during lock acquisition; and employing multiple feedback loops with prescaling of the reference and feedback signals.

Abstract: A new architecture for such a type of synthesizer is proposed not having the drawbacks of such known synthesizers and having the same phase noise properties as ordinary integer divide by N synthesizers. The novel architecture has a main PLL with a first integer frequency divider in its feedback loop and further an auxiliary PLL having a second integer frequency divider in its feedback loop.

Abstract: An integrated processor includes a microprocessor core and a bus interface unit. The integrated processor receives a reference clock signal and an external clock signal. The frequency of the reference clock signal is compared to the frequency of the external clock signal. Based upon this comparison, the appropriate frequency for the internal clock signal that controls the bus interface unit is determined. A clock generation circuit, such as a phase-locked loop, generates the appropriate frequency for the internal clock signal based upon the comparison of the reference clock signal and external clock signal.

Abstract: A frequency standard generator includes a voltage controlled crystal oscillator (VCXO) for generating high stability output signal, a radio wave receiver to receive a radio wave which includes a high accuracy reference time signal, a time interval measuring circuit which measures a phase difference between the reference time signal and the output signal of the VCXO; a frequency control processor which determines control data based on the phase difference data to phase lock the output signal of the VCXO to the reference time signal, a frequency deviation data generator for compiling the phase difference data to obtain frequency deviation trend data of the VCXO, and a compensation data generator for generating compensation data based on the frequency deviation trend data to compensate frequency changes in said VCXO when the reference time signal is unavailable.

Abstract: A phase-locked loop circuit for locking the phase of an oscillator to the phase of a reference signal includes a multi-cycle phase detector (11) for detecting a phase difference between an input signal and said reference signal through multiple clock cycles and for sending a corresponding phase adjustment signal, and, a multiple current source charge pump (12) connecting to said phase detector for receiving said phase adjustment signal and sending a current signal depending upon said phase adjustment signal.

Abstract: A circuit comprising an oscillator, a multiplexer, a half rate clock circuit and a full rate clock circuit. The oscillator may be configured to generate a first clock signal and a second clock signal in response to a control signal. The multiplexer may be configured to generate the control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal. The half rate clock circuit may be configured to generate the half rate clock signal in response to the first and second clock signals. The full rate clock circuit may be configured to generate the full rate clock in response to (i) one of the first and second clock signals and (ii) a reference clock.

Abstract: A high operational speed clock extraction circuit, which can be manufactured to be compact at low cost. In order to reduce the operational speed of a phase comparator, phases are compared between a signal obtained by frequency-dividing an inputted non-return zero signal by m and a signal obtained by frequency-dividing an extracted clock signal outputted from a voltage control oscillator by n. In addition, in order to correctly compare phases between the frequency-divided signals, edge pulses used for phase comparison and produced based on the frequency-divided input signals are divided by an edge pulse selecting circuit according to cases, specifically between a case of performing phase comparison for the rising edge of a frequency-divided clock and a case of performing phase comparison for the falling edge of the same. Then, phase comparison is performed based on each of the edge pulses. The output of each phase comparison is passed through a low pass filter to control the voltage control oscillator.

Abstract: A PLL response time is accelerated with a frequency detector counter. The PLL utilizes both a phase frequency detector and the frequency detector counter. Initially, the operation of the PLL is controlled by the frequency detector counter and the output of phase frequency detector does not affect the PLL system. During this period, the PLL synchronizes to an input clock frequency. After the PLL reaches a predetermined frequency range, the frequency detector counter stops working. Thereafter, the phase frequency detector controls the operation of the PLL. During this period, the PLL synchronizes to both the frequency and the phase of the input signal.

Abstract: Apparatus and methods for controlling the frequency spectrum of a clock signal, for example, to reduce EMI emissions. A PLL circuit receives a reference signal and generates an output clock signal. A modulating circuit is coupled to the PLL and generates a modulating signal. The PLL receives the modulating signal and accordingly varies the frequency spectrum of the output clock signal.

Abstract: A method is described for the digital control of a phase-locked loop consisting in the separate estimation of both phase and frequency errors of the data source as compared with those of the local oscillator and in the separate and adaptive filtering of the two signals. The value of the VCO control voltage is calculated on the basis of the two filtered signals. The phase and frequency error estimation and the frequency and phase error filtering are carried out in such a way as to eliminate the time-varying random components titter and noise) without delaying the feedback signals, since the portion of the signals that varies with time because of the variation of the commands, is subtracted before estimations and filterings.

Abstract: A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like a normal phase locked loop (PLL) and locks to the input signal, and a frequency loop that uses a reference frequency to influence the phase loop and effectively confines the output frequency of the phase loop and the SFPLL to be in a range of frequencies close to the reference frequency. The reference frequency is chosen to be very close to the input signal frequency that it is desired the SFPLL lock to. The SFPLL comprises a phase detector (10), a frequency detector (22), first and second gain components (12, 24), first, second and third filter components (14, 18, 26), a summer (16) and a voltage controlled oscillator (VCP)(20). By a judicious choice of the gains in the phase and frequency loops the SFPLL can be designed so that the range of frequencies to which the SFPLL will lock can be confined to an arbitrarily small region around the reference frequency (.omega.'.sub.r).

Abstract: A hybrid multi-frequency synthesizer is comprised of an analog phase lock loop, a digital phase lock loop and a phase lock loop monitor. The digital phase lock loop provides an accelerated, accurate frequency acquisition mode for the synthesizer. The analog phase lock loop provides a robust operating mode after frequency acquisition is achieved. The phase lock loop monitor provides a control circuit that monitors the synthesizer for frequency and phase perturbations. The phase lock loop monitor controls an electronic switch that selects either the analog or digital phase lock loop. The invention is further characterized by programmable band pass filtering, peak sensitivity detection and a fast lock feature.

Abstract: A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five "window" intervals. The "window" intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth.

Abstract: A video display apparatus comprises a phase-locked loop receiving a horizontal synchronous signal for generating an oscillation signal following the frequency of the horizontal synchronous signal, a tracking circuit for generating a tracking control signal for moving the frequency of the oscillation signal into a predetermined capture range of the phase-locked loop when the frequency of the horizontal synchronous signal changes, so that the frequency of the oscillation signal follows the frequency of the horizontal synchronous signal, and an output circuit receiving and amplifying the oscillation signal to output a horizontal output signal.

Abstract: The present invention provides a reliable method for oscillating an oscillator having an oscillator output without fail. The method includes steps of detecting whether the oscillator is regularly oscillating, and releasing the oscillator to oscillate when the oscillator is regularly oscillating, and holding the oscillator from oscillating until an enough control voltage is built-up therefor when the oscillator is not regularly oscillating. The present invention also provides a start up circuit for an oscillator having an oscillator output having a first state in a first instance and a second state in a second instance.

Abstract: A receiver has an oscillator for generating an oscillating signal at an oscillating frequency in accordance with an oscillation control signal, and receives a radio signal at a tuning frequency corresponding to the oscillating signal to demodulate the received radio signal. The receiver further includes a first frequency control loop system for generating a first control signal indicative of the difference in phase between a comparison signal generated by dividing the oscillating signal on the basis of the information on a channel selection frequency and a reference signal, and a second frequency control loop system for generating a second control signal indicative of a frequency difference between the oscillating frequency of the oscillating signal and the channel selection frequency. Either the first control signal or the second control signal is selectively supplied to the oscillator as an oscillation control signal.

Abstract: A feed forward apparatus and method discipline a clock signal by a reference signal in digital telecommunication networks. A synthesizer correction term within the feed forward apparatus and method includes a frequency correction term so that when one frequency correction term is selected in place of another frequency correction term the phase of the clock signal remains free from extraneous frequency or phase variations during the transition between frequency correction terms. Alternatively, the synthesizer correction term includes a phase correction term so that phase coherence between the reference signal and the clock signal results.

Abstract: A first phase comparator 22 of digital type and a second phase comparator 32 of sampling type are provided. Near a lock phase, an output current Iout2 is fed from the second phase comparator 32 to a voltage-controlled oscillator 14 through a change-over switch 40. In other phases, an output current Iout1 is fed thereto from the first phase comparator 22. When a reference signal fs is missing, a complementing circuit 50 complements a pulse to at least the reference signal fs input to the first phase comparator 22. A noise detecting/removing circuit 60 detects and removes noise from the reference signals fs, permits the reference signals fs to be fed to the first and second phase comparators 22 and 23, and halts the operations of the two phase comparators 22 and 32 for only a predetermined period of time after the noise has been detected.

Abstract: A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

Abstract: A phase locked loop (PLL) circuit includes a phase comparator that compares the phases of an input signal and a feedback signal and generates UP and DOWN pulses that are related to the phase difference. A charge pump receives the UP and DOWN pulses from the phase comparator and either charges or discharges the tuning voltage of a loop filter. The voltage controlled oscillator (VCO) provides an output signal that has a frequency that is related to the tuning voltage. A frequency divider then divides the frequency of the VCO output by a factor of N and provides the output as the feedback signal to the phase comparator. The PLL includes pre-lock circuitry that responds to an active state of a pre-lock input signal by narrowing the dynamic range of the VCO to a pre-lock range that is centered around a predetermined final frequency and that deactivates upon achieving the pre-lock range.

Abstract: A phase-locked loop design is provide that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.