Abstract: A phase lock loop having an bandwidth that does not depend upon N. The phase lock loop comprising: a controlled oscillator, a frequency divider by N, a phase detector for producing an error signal ER, and an adjustable converter, coupled to the phase detector and to the current controlled oscillator, for receiving ER and providing the controlled oscillator a control signal such that that the (Fico/N) ranges between a minimum value of Fmin and a maximal value of Fmax, wherein Fref=(Fmin+Fmax)/2.

Abstract: A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.

Abstract: A frequency synthesizer is provided with a prescaler 2 and a counter 3, which output a signal having a frequency generated by frequency-dividing an output signal of a VCO 1; a reference frequency divider 5 for frequency-dividing a frequency of a reference signal of a reference signal source 4; a frequency adjusting meas 9 operated in such that a frequency error between the output signal of the counter 5 and the output signal of the reference frequency divider 5 is detected, and in response to this detection result, such a signal is outputted by which either a capacitor value or an inductor value employed in a resonant circuit of the VCO 1 is switched; and also a bias control means for applying an arbitrary voltage V1 to a control voltage terminal of the VCO 1 so as to bring an output signal of a charge pump 7 into a high impedance state when the frequency adjusting means 9 is operated.

Abstract: A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the clock pulses. The frequency of such clock pulses changes in accordance with a control signal. Each one of the clock pulses has four sequential, one-quarter period phases. Adjacent phases are separated by boundaries to divide each clock pulse period into four quadrants. A frequency detector is fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data. A lock-out circuit prevents subsequent production of the control signal until a subsequently detected data edge crosses a different one of the boundaries.

Abstract: In a frequency synthesizer 1 that has a high spurious component elimination ratio, if the integer frequency division value is changed and a fractional frequency division value is to be generated, rounding circuit 6 rounds the random number generated by random number generation circuit 7. Based on the integer value that is thereby generated, frequency division value control circuit 5 generates an integer frequency division value. Because the integer frequency division value changes based on a random number, there is no regularity, and spurious components are never generated in output signal OUT. Even if compensation circuit 37 generates a compensation current and superimposes it on the output of charge pump circuit 35, the influence of the ripple current output from charge pump circuit 35 cannot be completely eliminated.

Abstract: A phase-locked loop (PLL) circuit having a voltage-controlled oscillator (VCO) is automatically calibrated for VCO center frequency and VCO gain during power up or responsive to a calibration signal. The VCO has several input voltage versus output frequency operating curves. During a calibration phase, proper VCO center frequency is selected by selecting one of the operating curves. VCO gain is then determined using the selected VCO operating curve. If the value of VCO gain is not within predetermined limits, VCO gain is adjusted accordingly, and the process of selecting a VCO operating curve and determining VCO gain is repeated.

Abstract: A recording clock generation circuit includes a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal; a first filter for smoothing an output from the first phase comparator; a VCO circuit for oscillating in accordance with the output smoothed by the first filter; a frequency divider for dividing a frequency of an output from the VCO circuit; a phase adjusting circuit for adjusting a phase of an output from the frequency divider; and a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.

Abstract: The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, the convergence time required for frequency detection of a frequency detection circuit is short and wrong operation of the frequency detection circuit with a control signal is less likely to occur. A clock generator produces, based on an oscillation frequency clock of a VCO, a first clock signal of the same phase, a second clock signal having a phase delayed by 90 degrees from that of the first clock signal, and a third clock signal having a phase delayed by 45 degrees from that of the first clock signal. A phase detection circuit performs phase control based on the phase difference between the third clock signal and an input signal, and a frequency detection circuit fetches the first and second clock signals in synchronism with the input signal and performs frequency control based on the fetched signals.

Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step.

Abstract: A phase locked loop (PLL) and method for stable clock generation in applications of wide band channel clock recovery performs frequency detection and phase detection with respect to an eight to fourteen modulation (EFM) signal and a PLL clock signal, and adjusts the current based on the results of the frequency detection and the phase detection, thereby generating the PLL clock signal synchronized with the EFM signal. The PLL includes a charge pump, a first low-pass filter, a voltage controlled oscillator and a static phase error controller. The charge pump sources or sinks the current in response to the results of the frequency detection and the phase detection and outputs the result of sourcing or sinking the current. The first low-pass filter low-pass filters the signal output from the charge pump and outputs the filtered result as a direct current control voltage.

Abstract: The present invention provides a phase-locked loop apparatus which extends a capture range in clock reproduction when digital data is reproduced and performs a high-speed and stable phase locking. A phase error is detected by a phase error detector 6 from a signal obtained by the sampling. Further, a frequency error is detected by a frequency error detector 8 on the basis of an inclination of a phase curve obtained by phase error information. A phase-locked loop circuit is controlled on the basis of these obtained phase error and frequency error.

Abstract: A phase-offset detecting phase comparator for comparing a reference signal and an auxiliary comparison signal which is a frequency-divided VCO output in terms of a phase to detect phase offset, and producing first and second delay control signals corresponding to the phase offset; a first delay element for adding delay to the auxiliary comparison signal by the first delay control signal to produce a comparison signal; a second delay element for adding delay to the VCO output by the second delay control signal to produce a PLL output; and a dummy frequency divider for adding delay corresponding to a frequency divider to the PLL output are provided.

Abstract: A system and method for synchronizing a plurality of synchronizable oscillators are disclosed. The method includes monitoring a respective output signal of each synchronizable oscillator, each output signal having a respective frequency, generating a synchronization signal based on the output signal having the highest frequency of all of the output signals, and providing the synchronization signal to all of the synchronizable oscillators.

Abstract: The VCO of a synthesizer operates with a coarse tuning and a fine tuning. During the coarse tuning, a binary search method is used to match the VCO frequency to one of a finite number of discrete reference frequencies. The coarse tuning operates without frequency division and phase comparison in a closed feedback loop, thereby speeding up the settling time and increasing the lock-in range. The fine tuning operates as a conventional analog PLL.

Abstract: A system and method for clock recovery from an input data stream recovers the clock signal in a manner that preserves the signal strength of the input signal. The measure of signal strength, referred to herein as the “signal strength indicator” is in turn used to normalize the output of a phase detector in a phaselocked loop (PLL), and the normalized signal is used as an input to the PLL oscillator to recover the clock signal from the input data signal. In this manner, the phaselocked loop is used to perform narrow band filtering, while baseband amplifiers are used to compensate for reference signal power variations. In one aspect, the present invention is directed to a clock recovery system for recovering a clock signal from an input data signal. The system comprises a primary phase detector for receiving an input data signal, and for combining the input data signal with a feedback signal to generate a phase difference signal.

Abstract: A mode control circuit of a PLL circuit for switching the PLL circuit from a high-speed mode to a normal mode. The PLL circuit compares the phase of a reference signal and the phase of a comparison signal to generate a first pulse signal and a second pulse signal, and generates based on the first and second pulse signals a frequency signal that is locked at a desired frequency. The mode control circuit receives the first and second pulse signals from the PLL circuit, generates a mode switch signal representing the normal mode when a difference between a phase of the first pulse signal and a phase of the second pulse signal is within a predetermined range, and, after the mode is switched from the high-speed mode to the normal mode, generates the mode switch signal such that the normal mode is maintained.

Abstract: An oscillation frequency of a VCXO is controlled based on a phase difference between a reference phase signal outputted from a reference phase generation circuit and a feedback phase signal outputted from a feedback phase generation circuit, an oscillation frequency of a VCO is controlled based on a phase difference between an output clock of the VCXO and an audio clock obtained from a divider circuit, and a clock outputted from the VCO is determined as a restored audio clock.

Abstract: A polyphase, noise-shaping, fractional-N frequency synthesizer utilizes multiple, parallel fractional-N divider channels to deliberately decorrelate noise and improve spectral purity. The synthesizer comprises a voltage controlled oscillator (VCO), a reference signal source to produce a plurality of different reference signals, a loop integrator, a plurality of desynchronized divider channels and a signal summer. Each divider channel comprises a frequency divider, a fractional-N control logic and a phase detector. Each divider channel divides an output signal from the VCO by a variable division factor and compares the divided signal to a different reference signal to produce an error signal. The signal summer combines the error signals from the desynchronized divider channels into a combined error signal. The loop integrator integrates the combined error signal to produce a control voltage that is applied to the VCO.

Abstract: A tuning circuit includes an oscillator that receives an oscillating input signal and a control signal, and generates an oscillating output signal. The control signal is obtained from a frequency control circuit that compares the phases of the oscillating output signal and a reference signal. The control signal controls the transconductance of a transconductance element in the oscillator, thereby controlling the oscillator output frequency. The oscillating input signal is obtained from an amplitude control circuit that detects an amplitude limit of the oscillator output. The oscillator output amplitude is responsive to the oscillating input signal. Frequency control and amplitude control in this tuning circuit are mutually independent, so their respective control loops remain stable under all frequency and amplitude combinations.

Abstract: A phase locked loop system for use with a synchronous dynamic random access memory (SDRAM) or a multi-rate high speed serial transmission buffer is disclosed. The invention includes a phased lock loop having a control voltage for controlling a voltage-controlled oscillator (VCO) that is adjusted, based upon whether the control voltage is within a specific voltage range and whether the VCO frequency is within a specific frequency range. If the control voltage is greater than a voltage maximum and the frequency is not beyond a frequency maximum, the VCO sensitivity is increased. If the control voltage is less than a voltage minimum and the frequency is not below a frequency minimum, the VCO sensitivity is decreased. This ensures that any signal noise or jitter does not have a proportionately large portion of the signal, and therefore minimizes its effect.

Abstract: An oscillating circuit removes a phase difference from between an input signal variable in frequency and a free-running oscillation signal through a two-step voltage-to-frequency control, wherein a frequency comparator, a detector, a flip flop circuit cooperates with a counter so as to vary a control range of the voltage-controlled oscillator in the vicinity of the input frequency, and, thereafter, a phase comparator makes the free-running oscillation signal synchronous with the input signal through the phase comparison therebetween, even if the voltage-to-frequency characteristics of the voltage-controlled oscillator is deviated from a design range, the deviation is taken up through the first-step control so that the manufacturer can delete an external regulator from the oscillating circuit.

Abstract: A voltage controlled oscillator (VCO) is tunable over a wide frequency range while exhibiting low phase noise by dynamically switching between two or more voltage/frequency operating curves. Reference voltages establish switching thresholds for each operating curve. A control circuit compares the VCO tuning voltage to the reference threshold voltages, and based on that comparison and its previous outputs, generates switching signals effective to selectively couple and decouple one or more frequency altering devices to the VCO.

Abstract: A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator; a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter.

Abstract: Coherent combining apparatus and methods that do not require training to adapt combining weights. The approach employed in the present invention uses phase-lock loops to demodulate input signals. The phase-lock loops are coupled so that their outputs are phase coherent. The outputs of the phase-lock loops are summed to obtain a coherent combining of the input signals. Exemplary embodiments of the present invention comprise two or more phase-lock loops having signal inputs and I and Q data outputs. A combiner sums the I and Q data output by the two or more phase-lock loops. A common decision circuit feeds back the summed output of the combiner to the two or more phase-lock loops and generates phase coherent output signals.

Abstract: A voltage-controlled oscillator frequency range detector is disclosed that detects when the voltage-controlled oscillator frequency within a phase-locked loop is out of range and indicates the required direction of the frequency adjustment. The voltage-controlled oscillator frequency range detector includes a comparator circuit, which receives a voltage-controlled oscillator control voltage signal, and a frequency detector circuit, which receives a reference clock signal and a voltage-controlled oscillator clock signal. Decision logic circuitry, coupled to the comparator circuit and to the frequency detector circuit, receives at least one output from the comparator circuit and an output from the frequency detector circuit and indicates whether an adjustment to a voltage-controlled oscillator frequency is required and its direction.

Abstract: A voltage controlled oscillator (VCO) is tunable over a wide frequency range while exhibiting low phase noise by dynamically switching between two or more voltage/frequency operating curves. Reference voltages establish switching thresholds for each operating curve. A control circuit compares the VCO tuning voltage to the reference threshold voltages, and based on that comparison and its previous outputs, generates switching signals effective to selectively couple and decouple one or more frequency altering devices to the VCO.

Abstract: A system and method have been provided for a phase-locked loop (PLL) circuit to use a selectable VCO frequency range during the acquisition of a signal, with a larger VCO frequency sweep window once the signal is being tracked. The circuit uses a frequency detector during acquisition, and the VCO is limited to operation is a plurality of discrete frequency bands. Each frequency band is sequentially searched using the low VCO gain. Upon acquisition, the frequency band is locked in, a phase detector is utilized, and the VCO sweep window is increased for tracking purposes.

Abstract: A tunable oscillator for producing an output signal includes an input for receiving a first voltage that is a function of the output signal, a controllable oscillator, and a voltage element that produces a second voltage and has a first leak current. The controllable oscillator produces the output signal based upon the first and second voltages, and the first leak current causes the second voltage to fluctuate. The tunable oscillator also includes a current generator operatively coupled with the input. The current generator produces a generator current that is a function of the first voltage, where the first voltage is responsive to fluctuations in the second voltage. The generator current compensates for the fluctuations in the second voltage.

Abstract: A polyphase, noise-shaping, fractional-N frequency synthesizer utilizes multiple, parallel fractional-N divider channels to deliberately decorrelate noise and improve spectral purity. The synthesizer comprises a voltage controlled oscillator (VCO), a reference signal source to produce a plurality of different reference signals, a loop integrator, a plurality of desynchronized divider channels and a signal summer. Each divider channel comprises a frequency divider, a fractional-N control logic and a phase detector. Each divider channel divides an output signal from the VCO by a variable division factor and compares the divided signal to a different reference signal to produce an error signal. The signal summer combines the error signals from the desynchronized divider channels into a combined error signal. The loop integrator integrates the combined error signal to produce a control voltage that is applied to the VCO.

Abstract: For controlling frequency and phase of an output clock signal dependent on a reference signal, a digital phase locked loop comprises a ring oscillator connected to a switch-over unit for generating the output clock signal. The ring oscillator has a plurality of serially arranged delay units. A phase comparator for comparing the phase of the reference signal and of the output clock signal. At least one switchable frequency divider unit is provided between the phase comparator and the output clock signal. A control unit controls the ring oscillator frequency by cut-in or cut-outs of delay units with the assistance of the switchover unit.

Abstract: A multi-channel clock recovery circuit is provided that generates pairs of recovered half-speed clocks. Each pair of half-speed clocks has a relative phase relationship of 180° and are capable of registering input data of a data channel at the eye of the input data. The multi-phase clock recovery circuit includes a voltage controlled oscillator outputting a plurality of half-speed reference clocks. Each of a plurality of clock recovery circuits include a phase locked loop having a phase multiplexor, the phase multiplexor receiving the plurality of half-speed reference clocks and selectively outputting four recovered half-speed clocks each having a half-speed frequency relative to the input data. The four recovered clocks are used as a feedback reference clocks in the phase locked loop and two of the four recovered half-speed clocks are used to synchronize input data.

Abstract: A phase-locked loop (PLL) circuit having a voltage-controlled oscillator (VCO) is automatically calibrated for VCO center frequency and VCO gain during power up or responsive to a calibration signal. The VCO has several input voltage versus output frequency operating curves. During a calibration phase, proper VCO center frequency is selected by selecting one of the operating curves. VCO gain is then determined using the selected VCO operating curve. If the value of VCO gain is not within predetermined limits, VCO gain is adjusted accordingly, and the process of selecting a VCO operating curve and determining VCO gain is repeated.

Abstract: A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.

Abstract: In a PLL device with a plurality of phase comparators, when one phase comparator has reached a locked state, this phase comparator is allowed to keep on delivering an output, while outputs of the other phase comparators are disabled. Accordingly, power consumption can be reduced. Furthermore, an error current output from a charge pump (109) connected to the phase comparators to output an error signal is reduced when lock approaches. Accordingly, lock failure can be avoided. Furthermore, a time constant of a low-pass filter (220) that receives the output of the charge pumps connected to the phase comparators is altered following alteration of the number of the phase comparators (212 to 219) that deliver their outputs. Accordingly, power consumption can be reduced, and also stability and converging speed are improved. Using distribution means (318) instead of frequency dividers provided for the phase comparators individually makes LSI implementation easy.

Abstract: A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite phase frequency detector (PFD) has both a digital phase frequency detector (digital PFD) and an analog phase detector (analog PD) with the digital PFD compensating for large phase differences and the analog PD compensating for smaller phase differences. The PLL automatically chooses between these two components in the composite PFD by controlling the pulse width of the divider output. This is accomplished by synchronizing the dead zone of the digital PFD with the active pulse width of the divider output and by similarly synchronizing the phase detector window of the analog PD to be within both the dead zone of the digital PFD and the active pulse width of the divider output.

Abstract: A frequency comparator includes a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively. The first and second detection signals are output for respective times based on a difference between the frequencies of the first and second clocks.

Abstract: A frequency detector embodying the invention includes circuitry for comparing first (e.g., a reference) and second (e.g., a recovery clock) signals having first and second frequencies, respectively, and for producing an output signal having: (a) a first condition characterized as a “dead zone” when their frequency difference is within a predetermined frequency range; (b) a second condition when the frequency of the first signal is greater than that of the second signal by the predetermined range; and (c) a third condition when the frequency of the second signal is greater than that of the first by the predetermined range. Frequency detectors embodying the invention are suitable for use in frequency tuning systems.

Abstract: A phase locked loop includes at least one control circuit, where a voltage-controlled oscillator provides an output frequency which is arranged to strive to follow an input frequency. The phase locked loop also includes an outer, slow, negative feedback control circuit, having the input frequency as a setpoint, the output frequency as a process value and an outer output signal. The phase locked loop also includes an inner, fast, negative feedback control circuit, having the sum of a reference frequency from a stable oscillator and the outer output signal as a setpoint, the output frequency as the process value and an inner output signal for controlling the voltage controlled oscillator.

Abstract: A phase synchronous circuit includes a comparing unit for comparing an output of a low-pass filter with a reference voltage which causes the central frequency of a voltage-controlled oscillator to be set as well as generating a compared output voltage by integrating a compared output current, a frequency oscillator for generating a frequency signal to frequency-modulate an output of the voltage-controlled oscillator and a switching unit for, in the presence of an input signal to the phase synchronous circuit, causing the compared output voltage to provide negative-feedback to a second control terminal of the voltage-controlled oscillator, whereas, in the absence of the input signal, to the phase synchronous circuit, causing the frequency signal to be input to the second control terminal of the voltage-controlled oscillator.

Abstract: The invention relates to reference handover in clock signal generation systems and similar applications. The idea according to the invention is to introduce a so-called “virtual” delay in the control loop of a PLL for the purpose of forcing the control loop to shift the phase of the PLL output clock signal, while still maintaining the mandatory phase lock condition of the PLL relative to a primary reference signal, towards a predetermined target phase relation with the primary reference signal. By utilizing a virtual delay, the problems associated with explicit delay elements such as passive or active delay lines are avoided, and a more robust and accurate clock phasing mechanism is obtained. Preferably, the virtual is introduced by superimposing an external phasing control signal in the control loop of the PLL on the output signal/input signal of a control loop element.

Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined by counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step.

Abstract: A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.

Abstract: The Phase Locked Loop circuit of this invention has both a short locking time and a stable operation. This Phase Locked Loop circuit has two phase comparators. The inputs to these two comparators are a reference signal Vf and a feedback signal Vc. The first phase comparator has two separate outputs depending on the phase difference &dgr; between the signals Vf and Vc. The first output is a signal up1 when &dgr; is smaller than −&tgr;1, and the second output is a signal dn1 when &dgr; is larger than −&tgr;1. The second phase comparator also has two outputs depending on the phase difference &dgr; between the signals Vf and Vc. The first output is a signal up2 when &dgr; is smaller than −&tgr;2 (&tgr;2>&tgr;1), and the second output is a signal dn2 when &dgr; is larger than &tgr;2. The signals up1 and up2 are output when the &dgr; has positive polarity and large absolute value. When &dgr; has positive polarity and a small absolute value, only signal up1 is output.

Abstract: An oscillating signal of a VCO (7), after being divided by a divider (2), is input by a phase comparator (3). The phase difference between the divider (2) and a reference signal is detected by the phase comparator (3), and phase error is smoothed by a loop filter (4) to yield a phase error signal. The oscillating signal of the VCO 7 is also input by a frequency detector (9) and is detected to determine whether it is equal to a predetermined value or in a predetermined range. On the basis of this detection result, a frequency error signal is output. The frequency error signal and the phase error signal, after being added together, are input by the VCO (7) as a control signal so that the oscillation frequency is controlled.

Abstract: A spread spectrum modulation technique uses digital control logic to switch back and forth between two feedback divider ratios so that the PLL spreads output clock frequency between two limits determined by the ratios. The spread spectrum control logic can be integrated into any PLL frequency synthesizer.

Abstract: A self-aligned clock recovery circuit for synchronizing a local clock with an input data signal includes a sampling type phase detector for generating an output signal based on the phase difference between the local clock and the data signal timing. The phase detector obtains samples of consecutive data symbols at sampling times corresponding to transitions of the local clock, and obtains a data crossover sample at a sampling instant in between those of the consecutive data symbol samples. A phase shifter is employed to phase shift the local clock by an amount corresponding to a time varying modulation signal so as to obtain each data crossover sample at a variable sampling instant relative to the associated consecutive symbol samples.

Abstract: A mode control circuit of a PLL circuit for switching the PLL circuit from a high-speed mode to a normal mode. The PLL circuit compares the phase of a reference signal and the phase of a comparison signal to generate a first pulse signal and a second pulse signal, and generates based on the first and second pulse signals a frequency signal that is locked at a desired frequency. The mode control circuit receives the first and second pulse signals from the PLL circuit, generates a mode switch signal representing the normal mode when a difference between a phase of the first pulse signal and a phase of the second pulse signal is within a predetermined range, and, after the mode is switched from the high-speed mode to the normal mode, generates the mode switch signal such that the normal mode is maintained.

Abstract: A PLL is provided with separate phase and frequency adjustment circuits to adjust the frequency of a produced internal clock independently from adjusting its phase. The phase adjustment circuit determines a phase error between the internal clock and an external clock, and averages the phase error over a predetermined time period to produce the corresponding control current. The frequency adjustment circuit detects the difference between the frequency of the internal clock and the frequency of the external clock to determine a frequency error. An accumulator accumulates the frequency error during the predetermined time period to produce the corresponding control current. Based on values of the control currents produced by the phase and frequency adjustment circuits, a current calculator calculates a resulting value of the control current to be applied to a CCO to modify its frequency so as reduce the frequency and phase differences.

Abstract: A frequency synthesizer is provided with a prescaler 2 and a counter 3, which output a signal having a frequency generated by frequency-dividing an output signal of a VCO 1; a reference frequency divider 5 for frequency-dividing a frequency of a reference signal of a reference signal source 4; a frequency adjusting meas 9 operated in such that a frequency error between the output signal of the counter 5 and the output signal of the reference frequency divider 5 is detected, and in response to this detection result, such a signal is outputted by which either a capacitor value or an inductor value employed in a resonant circuit of the VCO 1 is switched; and also a bias control means for applying an arbitrary voltage V1 to a control voltage terminal of the VCO 1 so as to bring an output signal of a charge pump 7 into a high impedance state when the frequency adjusting means 9 is operated.