Abstract: The capacitance of the capacitor with the constant capacitance is equivalently reduced in the capacitance of a resonant capacitor in a voltage control oscillator to increase the variable amount of the capacitance of the resonant capacitor, and to expand an oscillation frequency range. There are provided a differential negative conductance generator circuit having two resonation nodes for differential output, a differential resonant circuit having a variable capacitance that is controlled by voltage control and an inductance connected in parallel to each other, and a differential negative impedance circuit. A resonant circuit and a negative impedance circuit are connected between the resonation nodes. The capacitor with the constant capacitance that occurs between the resonation nodes is reduced by the negative impedance of the negative impedance circuit.

Abstract: A tunable oscillator includes a first transistor, a second transistor connected in parallel with the first transistor, a noise feedback and bias network coupled to the first and second transistors, a planar coupled resonator network coupled to the transistors and a means for dynamically tuning the resonant frequency of the planar coupled network and the junction capacitance of the transistors.

Abstract: A voltage controlled oscillator has an amplifier circuit which includes an inductor and a variable capacitance element, and outputs an oscillation signal of an oscillation frequency corresponding to an oscillation frequency control voltage supplied to the variable capacitance element; and a power supply circuit which supplies an operation current to the amplifier circuit, wherein by changing the operation current outputted from the power supply circuit in a state where the oscillation frequency control voltage is fixed to a desired value, a value of the operation current at which the oscillation frequency of the oscillation signal takes a value in the vicinity of a maximum value, is extracted, and the extracted value of the operation current is set as a value of the operation current outputted from the power supply circuit.

Abstract: A self-biasing negative transconductance LC oscillator that uses self-biasing circuitry to regulate a current source that feeds negative transconductance circuitry and direct current (DC) bias circuitry to apply a DC bias between control inputs and outputs of the negative transconductance circuitry is disclosed. A current source setpoint is based on the voltage swing of the oscillator, which can then be controlled by the DC power supply that powers the oscillator. In one embodiment of the present invention, the negative transconductance circuitry includes a pair of p-type metal oxide semiconductor (PMOS) cross-coupled field effect transistors (FETs), which have a limit applied to their gate to source voltages. Limiting the gate to source voltages of the FETs limits the percentage of the oscillation cycle that the FETs spend in the triode region and thus reduces the noise contribution of the FETs and allows for less power consumption for a given noise requirement.

Abstract: An oscillation circuit includes a constant current source, a current mirror circuit configured to receive a constant input current from the constant current source and to output a current proportional to the constant input current, a first inverter configured to be driven with a quartz resonator to oscillate, an operational amplifier configured to supply a power to the first inverter with a voltage equal to an input voltage thereof and a second inverter having a power supply terminal connected to the current mirror circuit and to the operational amplifier and configure to generate the input voltage for the operational amplifier.

Abstract: A voltage-controlled oscillator (VCO) includes: an oscillation unit, for generating an oscillation signal according to a biasing current; a current mirror, for providing the biasing current, the current mirror comprising: at least one first transistor, coupled between a first voltage level and a current source; at least one second transistor, coupled to the first voltage level, a gate of the second transistor is coupled to a gate of the first transistor and the current source; a switch module, coupled to the current mirror; and a control module, coupled to the switch module, for controlling the switch module to adjust the biasing current.

Abstract: 1st to nth pairs of transistors (n=an odd number) are connected in parallel, and each pair of transistors has an upper transistor and a lower transistor connected in series. A point between the upper transistor and the lower transistor of a preceding pair of transistors is connected to a gate of the lower transistor of a subsequent transistor, and the point between the upper transistor and the lower transistor of nth pair of transistors is connected to the gate of the first lower transistor. A capacitor is inserted between the lower transistor and a direct power source. A current regulating circuit connected to gates of the upper transistors, wherein the current regulating circuit supplies a gate voltage to each gate of the each upper transistor.

Abstract: An electronic circuit device includes a negative resistance generating circuit, a second transistor and a path. The negative resistance generating circuit has a first transistor having a control terminal coupled to a resonator. The second transistor has a control terminal coupled to an output terminal of the first transistor and has an output terminal coupled to a DC bias terminal. The path is coupled to between the DC bias terminal and an output terminal of the first transistor through the second transistor and provides a bias to the first transistor.

Abstract: A phase locked loop circuit includes a voltage controlled oscillator having an oscillating characteristic value changed by a switching signal. A characteristic controller supplies the switching signal to the voltage controlled oscillator to increase the oscillating characteristic value according to elapse of time. The voltage controlled oscillator oscillates according to both of the oscillating characteristic value and a frequency control signal. Even if the frequency control signal is equal to a power source level at the beginning of supplying electric power, the phase locked loop can be locked in a target frequency.

Abstract: The invention provides an oscillator circuit that reduces the dependence of an oscillation frequency on a power supply voltage. A charging and discharging circuit is a circuit switchable between an initializing operation setting an initial voltage for discharge and a discharging operation, and outputs a clock when the discharge is completed. The clock is inputted to a set terminal of a RS flip-flop. A signal formed by delaying an output signal of the RS flip-flop by a delay circuit is inputted to a reset terminal of the RS flip-flop. The output signal of the RS flip-flop is inverted to a discharge enable signal by an inverter, and the discharge enable signal is inputted to a switching circuit of the charging and discharging circuit. With this structure, the charging and discharging circuit alternately repeats the initializing operation and the discharging operation, and by the initialization the discharging operation is always started from the power supply voltage.

Abstract: A voltage controlled oscillator circuit includes a ring oscillator including a plurality of delay circuits that are connected like a ring and a voltage to current converter circuit for controlling current flowing in the ring oscillator so as to change an oscillation frequency thereof. The voltage to current converter circuit 11 is provided with a shunt circuit for shunting a part of current obtained by converting input voltage, and the shunted part of the current is used for controlling the current flowing in the ring oscillator.

Abstract: A voltage-controlled oscillator includes an LC bank, a negative resistor circuit, a DC block, an AC block including a source resistor, and a first bias circuit controlled by a junction node of a first and second transistor, wherein the first bias circuit provides a first feedback voltage to a first control node, and maintains a voltage at the junction node of the first and second transistors, and a second bias circuit controlled by the junction node, wherein the second bias circuit provides a second feedback voltage to a second control node and maintains a voltage at the junction node.

Abstract: A tunable, low power clock generator employs a voltage regulator, one or current generators and a variable resistor bank that, together, produce a control voltage for trimming a VCO. The control voltage is arranged to also compensate, at least, for the variables of temperature, supply voltage and fabrication processes as they affect the VCO output frequency. The current generator is well characterized over the variables discussed and the resistor bank is a flexible series/parallel array of resistors made from differing materials exhibiting different temperature coefficients. The resistor bank provides for various overlapping resistance values simultaneously with various overlapping temperature coefficients wherein the temperature coefficient profile of the clock generator over frequency and temperature is controlled.

Abstract: An oscillation control apparatus is provided with: an oscillating unit for oscillating an oscillating element; an output amplifying circuit having two pieces of same types of transistors series-connected to each other, for outputting a signal from a junction point between the two transistors in response to an oscillation signal outputted from the oscillating unit; a bias unit for generating two DC bias voltages having different levels from each other, which are applied to either respective gates or respective bases of the two transistors; a constant voltage power supply unit for applying a constant voltage to the oscillating unit; and an inverter unit provided between the oscillating unit and any one of either the gates or the bases of the two transistors, for inverting a phase of the oscillation signal outputted from the oscillating unit.

Abstract: An oscillation stabilization detecting circuit comprises a T flip flop receiving a pulse-type oscillation signal generated by oscillating a crystal oscillator and then dividing the oscillation signal to output; a pulse control unit including inverters and transistors, the pulse control unit converting the signal output from the T flip flop into a pulse-type signal starting from a high level and then outputting the converted signal; and an oscillation stabilization detecting unit including a capacitor charged with the signal output from the pulse control unit; and a plurality of transistors. The oscillation stabilization detecting unit controls charging time of the capacitor by adjusting a bias current and, after the charging time passes, outputs a stabilization signal to a CPU, the stabilization signal representing that the oscillation signal is stabilized.

Abstract: An ultra-low power crystal oscillator architecture that draws less than 2 ?A during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 ?A.

Abstract: The present invention relates to an oscillating apparatus. The oscillating apparatus includes a biasing circuit, a multi-vibrator, a detecting circuit, and a selecting circuit. The biasing circuit is for generating a bias signal, wherein the biasing circuit includes a connecting port for using an impedance device to control an oscillating frequency or for directly connecting to external clock source as a reference clock. The multi-vibrator coupled to the biasing circuit for generating the oscillating frequency according to the quantity of the biasing signal. The detecting circuit coupled to the connecting port for generating a detecting signal whether the connecting port is coupled to the impedance device or the external clock source. The selecting circuit includes an AND gate coupled to the multi-vibrator and the selection signal and an OR gate coupled to the AND gate and the connecting port.

Abstract: The integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A real time clock circuit provides a system clock for the processing core. The real time clock further comprises an internal oscillator that generates the system clock for the integrated circuit package. The internal oscillator has a factory calibrated bias current. An internal oscillator control register controls the operation of the internal oscillator responsive to control bits of the programmable load capacitor array controlled by the processing core.

Abstract: A voltage controlled oscillator includes a first NMOS transistor having a base terminal configured to receive an input signal INP and a drain terminal connected to an output node OUTN, a second NMOS transistor having a base terminal configured to receive an input signal INN and a drain terminal connected to an output node OUTP, a third NMOS transistor having a source terminal connected to a low voltage supply VSS and a drain terminal connected to source terminals of the first NMOS transistor and the second NMOS transistor. A first PMOS transistor includes a base terminal connected to the output node OUTP and a drain terminal connected to the output node OUTN. A second PMOS transistor includes a base terminal connected to the output node OUTN and a drain terminal connected to the output node OUTP.

Abstract: A FET oscillator with increased frequency stability. This is accomplished by using a controlled voltage supply with error correction to power the amplifier stage of the oscillator. This voltage changes as the oscillator temperature increases in order to reduce the variation in frequency, caused by the amplifier and other frequency determining components changes. By using this compensated amplifier as the active section of an oscillator, the oscillator frequency stability is increased.

Abstract: Integrated circuit including a phase-locked loop (PLL) circuit having a first mode and a second mode of operation. Operating the PLL circuit in the first mode may generate a constant frequency responsive to a programmable bias. Operating the PLL circuit in the second mode may generate a frequency tracking a reference signal coupled to an input of the PLL circuit.

Abstract: A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down current. For each delay cell, the gate of the biased nMOSFET is biased by the control voltage provided by the phase locked loop, and the gate of the biased pMOSFET is biased at a bias voltage provided by the feedback loop. The biasing of the pMOSFETs is adjusted so that the pull-up and pull-down currents for each delay cell are matched, thereby providing a 50% duty cycle and good jitter performance over process, supply voltage variations, and temperature variations. Because only the feedback loop has non-zero static current, low power is expected. Other embodiments are described and claimed.

Abstract: The oscillation circuit includes an output current mirror, a P-N complementary current mirror, a P-type current mirror and an N-type current mirror. The P-N complementary current mirror has the same structure as the output current mirror but has current that is only 1/k times the current of the output current mirror, wherein k is greater than 1. The P-type current mirror connects to the P-N complementary current mirror, and has current that is m times the current of the P-N complementary current mirror, where m is greater than 1. The N-type current mirror has one end connected to the P-type current mirror and another end connected to the output current mirror. The N-type current mirror has current that is n times the current of the P-type current mirror, where m × n k ? 1 , and n is greater than 1.

Abstract: A voltage controlled oscillator includes at least one input port for receiving a control voltage and at least one voltage-to-current coupled to the input port for generating a control current in response to the control voltage. At least one current controlled oscillator generates an oscillating frequency output in response to the control current. At least one compensation branch is coupled to the voltage-to-current converter for generating a compensation current that increases the control current when the control voltage exceeds a predetermined value.

Abstract: An oscillator for use within an implantable medical device is provided. The oscillator includes a resonator and a first switch coupled to a first resistive network. The first resistive network provides a first electrical path through the first switch and a second electrical path not going through the switch. The oscillator additionally includes a second switch coupled to a second resistive network. The second resistive network provides a third electrical path through the second switch and a fourth electrical path not going through the switch. Furthermore, the oscillator includes a transistor, the base terminal coupled with the first resistive network and the resonator and the emitter terminal coupled to the fourth resistor. The second electrical path with the first switch opened has a substantially higher resistance than the first electrical path when the first switch is closed.

Abstract: The circuit for controlling the oscillation frequency of an oscillation loop (66) has among others the following components—a first tunable capacitor unit (80) for providing a selectable amount of capacitance to the oscillator loop in accordance with a stored setting, and for controlling the oscillation frequency of the oscillator loop, and—a volatile storage unit (84) adaptated to store the setting of the tunable capacitor unit. The circuit further comprises a supply line (52) to the volatile storage unit and at least one other supply line (44) for the other components of said circuit. The supply line to the volatile storage unit is independent of said at least one other supply line, so that the volatile storage unit can be powered independently of other components of said circuit.

Abstract: The cathode of a first varactor diode (VD1) is connected to a resonator element (XD) of an oscillator (2) via a capacitor (C1) and is connected to a triangular wave generator circuit (3) via an inductor (RFC1) and a resistor element (R1), whereas the anode is connected to the cathode of a second varactor diode (VD2) via a capacitor (C2) and is grounded via an inductor (RFC3). The cathode of a zener diode (ZD1) is connected to a node of the inductor (RFC1) and the resistor element (R1), whereas the anode is grounded via a resistor element (R2). The cathode of the second varactor diode (VD2) is connected to a node of the zener diode (ZD1) and the resistor element (R2) via an inductor (RFC2), whereas the anode is grounded. In other embodiments, certain component(s) may be omitted and/or a fixed supply potential may be substituted for the ground potential.

Abstract: A method and apparatus for varactor bank switching for a voltage controlled oscillator is disclosed. Varactor bank switching involves generating a negative bias voltage signal as a control signal for a varactor bank switch in an off-state, the varactor bank switch comprising a pass-gate circuit including switching transistors. Generating the negative bias voltage signal includes employing an active rectifier circuit running at the speed of an oscillation signal, the negative bias voltage signal maintaining the gate-source voltage of the pass-gate circuit below a threshold voltage to prevent said switching transistors from becoming conductive in an off-state.

Abstract: According to an example embodiment, there is a testing device for testing a phase locked loop having a power supply input. The testing device comprises a power supply unit for providing a power supply signal VDD having a variation profile to the power supply input of the phase locked loop, wherein a width and height of said variation profile are formed in such a way, that the voltage controlled oscillator is prevented from outputting an oscillating output signal. There is a means for disabling a feedback signal to a phase comparator of the phase locked loop such that said phase locked loop is operated in an open loop mode, and a meter for measuring a measurement signal of the phase locked loop, while said power supply signal is provided to the power supply input.

Abstract: A PLL frequency synthesizer circuit includes a voltage-controlled oscillator circuit provided with a capacitor, an inductor, and a variable capacitor element oscillating using the resonance frequencies of the capacitor and inductor, for outputting the oscillation frequency signal of a variable capacitor element, a negative feedback loop circuit capable of looping the signal output from the voltagecontrolled oscillator circuit and performing a frequency acquisition operation for adjusting the frequency of the signal to a desired locking frequency, a tuning circuit for performing tuning so that the oscillation frequency approaches the locking frequency, by modulating the capacitance value of the capacitor of the voltage-controlled oscillator circuit prior to the frequency acquisition operation, and a reference potential application circuit for applying a reference potential to the variable capacitor element of the voltage-controlled oscillator circuit during the tuning operation performed by the tuning circuit.

Abstract: A charge pump that generates a bias input to affect an output voltage of the charge pump is described herein. The charge pump may include a charge pump stage, a replica charge pump stage, and a self-biased differential amplifier. In some instances, the charge pump may be incorporated into a delay locked loop or a phase locked loop.

Abstract: An oscillator is provided having an oscillator circuit including at least one oscillator circuit inductor and a first oscillator circuit capacitor, whereby the value of the first oscillator circuit capacitor is reversible by means of the first control voltages between different stages. The oscillator is characterized by a first control voltage source, which applies first control voltages with at least three stepwise different values to the first oscillator circuit capacitor. Preferably, the control voltages are generated over a network of current sources and resistors, whereby the network compensates for the thermal response of the oscillator. Further, a method for operating this type of oscillator is presented.

Abstract: A method and an apparatus to sense supply voltage have been disclosed. In one embodiment, the apparatus includes a resistor having a first end and a second end, the first end coupled to a voltage supply and a ring oscillator sensor coupled between the second end of the resistor and ground, the ring oscillator sensor having an output coupled to a computational element. Other embodiments have been claimed and described.

Abstract: A voltage controlled oscillator with anti supply voltage variation and/or process variation includes an oscillation circuit for outputting an oscillatory signal; a current source coupled to the oscillation circuit for providing an input current to the oscillation circuit; and a variation compensation circuit for compensating the variations generated by the supply voltage and process. The variation compensation circuit includes a peak detector for generating a peak voltage proportional to the amplitude of the oscillatory signal; a compensating voltage generator for generating a reference voltage according to the process variation so that the oscillation circuit achieves the same working conditions under the process variation; and a comparator for comparing the peak voltage and the reference voltage to generate a control voltage. When the variation compensation circuit includes an amplifier, the supply voltage can be compensated.

Abstract: A semiconductor circuit for reducing flicker noise includes a negative-conductance generator and a body bias voltage supplying circuit. The negative-conductance generator includes a pair of cross-coupled field effect transistors in order to generate negative-conductance, wherein each field effect transistor includes a body. In order to remove flicker noise generated by the pair of the field effect transistors, the body bias voltage supplying circuit supplies a body bias voltage to the body of each of the pair of the field effect transistors so that a forward bias voltage is supplied to the body and source of each of the pair of the field effect transistors. The field effect transistors are preferably NMOS transistors or CMOS transistors. The semiconductor circuit is used in a voltage controlled oscillator (VCO) or a phase-locked loop (PLL).

Abstract: A circuit can include an oscillator core that outputs, in response to a bias signal, a periodic signal having an oscillation frequency; a bias circuit that, when powered, provides the bias signal (e.g., a voltage) to the oscillator core; and a switching circuit that periodically powers the bias circuit at a second frequency and provides the bias signal to the oscillator core when the bias circuit is not powered. The switching circuit can include a storage element that stores energy when the bias circuit is powered and uses stored energy to provide the bias signal when the bias circuit is not powered. The switching circuit can include a divider circuit that divides the oscillation frequency of the periodic signal to generate a control signal having the second frequency, and the bias circuit can be periodically powered at the second frequency in response to the control signal.

Abstract: A real time clock integrated circuit (RTC IC) and an electronic apparatus thereof are provided. In the RTC IC, only a low-power oscillator is used for generating a standard clock for a real time counter, and the standard clock with a frequency drift of the low-power oscillator is compensated through table lookup. Accordingly, the power consumption, fabrication cost and design complexity of the RTC IC are reduced and the counting operation duration of the RTC IC is prolonged.

Abstract: The invention relates to a high frequency heating apparatus and provides a tracking method of a frequency modulation in order to prevent an extension of the harmonic current component of an oscillation threshold ebm which varies from moment to moment in accordance with a change in the temperature of a magnetron. A driving signal for driving a first semiconductor switching element (3) and a second semiconductor switching element (4) is transmitted to a driving control IC unit (14), and an input reference signal Ref is used to perform an input current fixed control. In this case, a variation amount of the input current of the input reference signal Ref is understood as an accumulation information POW and a constant is optimally configured in a resistor network in an ebm-tracking bias circuit (20).

Abstract: Current sources are selectively coupled to a current controlled frequency determining circuit of an oscillator. A buffer amplifier has an input coupled to the current controlled frequency determining circuit of the oscillator and the buffer amplifier output is selectively coupled to the current sources not coupled to the frequency determining circuit of the oscillator. The buffer amplifier output maintains substantially the voltage of the current controlled frequency determining circuit on each of the current sources not coupled to the frequency determining circuit so that when any current source is coupled thereto, there is substantially no voltage difference therebetween. This substantially prevents generation of undesirable frequency spikes during coupling of the current sources to the frequency determining circuit of the oscillator.

Abstract: An electrical oscillator circuit (301, 302) comprising: a resonator (303) comprised in the first subcircuit (301); and an active device (309) comprised in the second subcircuit (302) connected to energize the resonator (303) to provide an oscillating electrical signal transmitted as a differential signal via electrical conductors (306, 307) to the second subcircuit (302). The oscillator is characterized in that the second subcircuit (302) comprises means (311, 312, 313, 314) for receiving the differential signal transmitted via the electrical conductors (306, 307) and converting the differential signal to a single-ended signal with reference to the signal ground reference (G2) of the second subcircuit (302). Thereby a noise robust oscillator signal is provided with the use of very few components. Particularly suitable for oscillators embodied in an integrated circuit with the resonator mounted on a printed circuit board, PCB. And an integrated circuit.

Abstract: An oscillator circuit may be used with controller circuits that are designed to operate with crystals, with no modifications to the pinout or firmware of the controller circuit. In some embodiments, the oscillator circuit includes an enable input that is responsive to low-amplitude transitions, which may be coupled to and driven by the crystal output signal of the controller circuit. When transitions are present on the crystal output signal, the oscillator circuit enables its clock output signal. When the controller circuit disables its crystal output signal, the oscillator circuit no longer detects transitions on the crystal output signal coupled to the oscillator circuit enable input, and disables the clock output signal.

Abstract: Voltage controlled oscillator (VCO) circuitry with low phase noise and a wide range of operating frequencies is presented. The VCO circuitry includes circuitry with two or more VCO sub-circuits, each sub-circuit being optimized to produce output clock signals with low phase noise and with frequencies in a different range. Sub-circuits with gear inputs may be operative to produce output clock signals in a lower range of frequencies, while sub-circuits optimized for high speed operation may be used to produce output signals in a higher range of frequencies. A control circuit may be used to produce a control signal coupled to all sub-circuits. The control signal may set the operating frequency of the sub-circuits.

Abstract: An external signal detection circuit includes an input port, to which a first end of a circuit including a pull-up resistor connected in series with a first switch portion is connected, the input port receiving an input of an external signal; an input detection portion connected to the input port for receiving an input of the external signal and an input of an input detection signal that sets a timing for intermittently detecting the input of the external signal; and a connection control portion turning on the first switch portion in time with the timing at which the external signal is detected.

Abstract: It is therefore the object of the present invention to disclose a device for power calibration of an oscillator in the high-frequency range, which has a reduced number of components and/or has less-expensive components. A method for power calibration of an oscillator is also to be disclosed, which eliminates the disadvantages of the known methods, that is, determining the output power of the oscillator via an additional, expensive component. To that end, the input (31) of the control module (40) is embodied as electrically connectable to the HF switch (comprising (22) and (24)) and the output (34) of the control module (40) is embodied as electrically connectable to the HF switch and/or to the amplifier.

Abstract: An apparatus for providing an oscillating signal to a load comprises: a phase locked loop, PLL, comprising a feedback loop; a power control means for manipulating oscillating signal power; an isolator for isolating the feedback loop from the load; and a mode selector coupled to the power control means and the isolator, for controlling the power control means and the isolator so that in a steady state power mode, oscillation power is supplied to the load and in a reduced power mode, power is isolated by the isolator from the load to the feedback loop so that phase lock is maintained when the oscillation power is reduced.

Abstract: In one embodiment, the present invention includes methods and apparatus for providing initial control values to programmable load capacitors of an oscillator, such as that of a real time clock circuit. Using the initial values, the real time clock circuit may begin operation, enabling additional circuitry within an integrated circuit to begin operation. This additional circuitry may cause operating values to program the load capacitors to provide a desired reference clock based on a given system's requirements.

Abstract: The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.

Abstract: Methods and circuits for chain ring oscillators having a constant delay time over variations of temperature and variations of semiconductor manufacturing process while requiring low operating voltage only have been disclosed. A system current source includes a constant voltage circuit generating a constant voltage and hence a constant current via a resistance element. Main parts of the constant voltage circuit are an operational amplifier and a bandgap reference circuit. Using a series of current mirrors the constant currents are mirrored to current sources contained in each of n-inverter stages of the chain ring oscillator.

Abstract: An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

Abstract: In an oscillation apparatus formed by a ring oscillator including an odd number of inverters (more than two inverters) connected in a ring, each of the inverters having one drive MOS transistor and one load MOS transistor, a constant voltage generating circuit is adapted to generate a constant voltage corresponding to a threshold voltage of the drive MOS transistor, and a voltage-to-current converting circuit is adapted to convert the constant voltage into load currents. Each of the load currents flows through the load MOS transistor of one of the inverters.