Abstract: A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

Abstract: The present invention provides circuitry for maintaining the desired phase noise across the tuning range of a frequency synthesizer by compensating the voltage controlled oscillator (VCO) bias current according to various tuning parameters available within the frequency synthesizer, thereby reducing overall current drain and inductor quality factor requirements. In general, the present invention includes a VCO bias circuit capable of controlling the VCO bias current in response to a control signal provided by additional circuitry based on the operating frequency of the frequency synthesizer. Further, the VCO bias current changes in response to changing the operating frequency of the frequency synthesizer.

Abstract: A method and apparatus for tuning a VCO circuit to provide desired modulations is described. In one embodiment, the method of the present invention uses a controlled voltage from a digital-to-analog converter to obtain VCO voltage/frequency characteristics. The VCO voltage/frequency characteristics are used to determine a VCO capacitance value as well as a charge pump current level for each frequency band of interest. For one embodiment, the VCO circuit includes a bank of switchable capacitors used to set the VCO capacitance value. The charge pump includes a number of switch-controlled current meters to set the charge pump current level. The VCO capacitors and charge pump current meters are controlled by an off-chip CPU.

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. ‘Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.

Abstract: A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an ‘open-loop’ tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.

Abstract: A method is provided for operating a voltage controlled oscillator, particularly in a portable communications appliance, when the oscillator is supplied with a variable control voltage, which is taken from an operating voltage, preferably from a constant voltage source, such that the variable control voltage is supplied via a capacitor to the oscillator, and the specific additional voltage is added to the variable control voltage when required in an operating phase, with the specific additional voltage being inclined to the capacitor in a preparation phase.

Abstract: A ring oscillator having a stable output signal without influence of MOS devices is disclosed. The ring-oscillator has a bias circuit to drive a plurality of delay cells. The bias circuit has a first loading unit with a p-n junction, a second loading unit with a p-n junction, and a resistor electrically connected to the p-n junction of the second loading unit. The second loading unit and the resistor are positioned at a current path of a current mirror, and the first loading unit is positioned at another current path of the current mirror. The area of the p-n junction in the second loading unit is not equal to the area of the p-n junction in the first loading unit. The magnitudes of the current passing on the two current paths are only controlled by characteristics of the p-n junctions of the first and second loading units.

Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.

Abstract: A fast start up oscillator. The fast start-up oscillator includes a power-on-reset detect circuit, a bandgap circuit, a voltage detect circuit, a RC-oscillator, and a count two circuit. The fast start-up oscillator is provided with a fast stabilized voltage source to ensure oscillation accurate and quickly such that the system is woken up.

Abstract: A LC controllable oscillator (LCCO) according to the invention comprises a voltage-controlled oscillator (VCO) and a first voltage controlled current source (VCCS) of a first type for supplying a current to the VCO. The VCO is realized with a flit pair of VCCCS of the first type coupled with a second paw of VCCS of a second type end a LC resonator. The VCO generates a periodical oscillation frequency that is controllable by a control signal (V). The LCCO further comprises a replica scaled bias module (RSBM) supplied from the external voltage source. The RSBM is conceived to generate a control signal (BIAS CONTROL) for controlling the supplied current delivered by the first VCCS to the VCO.

Abstract: A receiver for reducing the diffraction of a noise from a quarts oscillator. An analog circuit 20, an oscillator 30, a logic circuit 32, and a power source circuit 34 which constitute the receiver are formed in a one-chip component 10. The power source circuit 34 generates two kinds of action voltages and supplies a first action voltage to the analog circuit 20, and a second action voltage lower than the first one to the oscillator 30 and the logic circuit 32.

Abstract: Disclosed is an oscillator circuit (1A) for use in a local oscillator of an RF communications device (100) that communicates over an RF channel. The oscillator circuit includes an oscillator circuit portion (2) and a bias circuit portion (3) coupled to the oscillator circuit portion for setting the operating point of the oscillator transistors. The oscillator circuit further includes a switch (6) for selectively one of connecting or disconnecting the bias circuit portion from the oscillator circuit portion, and a capacitance (5) for storing an output of the bias circuit portion during a time that the switch disconnects the bias circuit portion from the oscillator circuit portion, thereby maintaining control of the operating point of the oscillator transistors of the oscillator circuit portion. When the switch is open any noise generated by the biasing circuit portion is prevented from reaching the oscillator circuit portion, thereby reducing the overall noise floor of the oscillator circuit.

Abstract: A voltage controlled oscillator circuit is shown using multiple delay stages with the last stage looped back out of phase to the first stage. Each stage delay is formed by charging one or more capacitors. The circuitry uses active components demonstrating a square law relationship between a control voltage and a resulting current. The current is ultimately used to charge the delay capacitor. The net effect is a linear relationship of the VCO frequency and an input control voltage. The range of the linear relationship is extended by using square law current sources to provide suitable currents that extend the linear range when other active devices are no longer supporting the square law relationship. In addition bipolar device are used to compensate for temperature and batch to batch processing effects of FET devices.

Abstract: A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that, would utilize this square wave clock signal.

Abstract: A control voltage is fed to an oscillation circuit from a control terminal, and a power supply voltage is fed thereto from a power supply terminal. An output circuit is provided between the oscillation circuit and an output terminal. The power supply terminal is connected to a feedback terminal through a DC separating capacitor and an amplifier. A signal leaking out to the power supply terminal from the oscillation circuit is fed to the amplifier through the DC separating capacitor. The amplifier amplifies the signal leaking out to the power supply terminal, and feeds the amplified signal to the feedback terminal as a feedback signal Loop.

Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

Abstract: A clock oscillator circuit that includes an inverting amplifier and a resonator configured to generate an oscillating signal. The clock oscillator includes a bias circuit having a relatively constant current source configured to create a bias voltage to bias the amplifier in an operating state that can sustain the oscillating signal. The inverting amplifier and the bias circuit are configured to operate in a low power state.

Abstract: An oscillator for use in a preconditioner includes a rectifier, a converter receiving an input voltage and supplying an output voltage, and a control unit effecting peak current mode control. The oscillator has a switching frequency with a period dependent on the input voltage and the output voltage.

Abstract: An oscillator circuit (300) comprising: a resonator (Q) connected between an input (IN)and an output (OUT); an inverter having first and second driver transistors (MP, MN) connected in series via an output-coupled node; first and second biasing transistors (MPD, MND) for biasing the driver transistors; and first and second limiting means between the gate electrodes of the driver transistors respectively and the output. The CMOS circuit allows regulation of the oscillation amplitude without need for well-controlled DC current sources to polarize correctly the driver transistors, and without need for a start-up circuit to ensure that both driver transistors remain in saturation when the circuit is powered on. A simple oscillator circuit (600) has an inverter whose input is capacitively coupled to the input (IN), first limiting means coupled between the inverter input and the output (OUT), and second limiting means coupled between the input (IN) and the output (OUT).

Abstract: A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.

Abstract: An object of the present invention is to facilitate positioning of a metal member for mounting a high-frequency diode and of a dielectric strip, thereby remarkably improving control of oscillation characteristics and workability in production.

Abstract: Disclosed is an oscillator circuit (1A) for use in a local oscillator of an RF communications device (100) that communicates over an RF channel. The oscillator circuit includes an oscillator circuit portion (2) and a bias circuit portion (3) coupled to the oscillator circuit portion for setting the operating point of the oscillator transistors. The oscillator circuit further includes a switch (6) for selectively one of connecting or disconnecting the bias circuit portion from the oscillator circuit portion, and a capacitance (5) for storing an output of the bias circuit portion during a time that the switch disconnects the bias circuit portion from the oscillator circuit portion, thereby maintaining control of the operating point of the oscillator transistors of the oscillator circuit portion. When the switch is open any noise generated by the biasing circuit portion is prevented from reaching the oscillator circuit portion, thereby reducing the overall noise floor of the oscillator circuit.

Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

Abstract: A circuit generally comprising a tank circuit and an inverter circuit. The tank circuit may be configured to generate a first signal having a frequency of oscillation in response to a second signal. The inverter circuit may be configured to (i) generate the second signal in response to inverting the first signal and (ii) adjust a delay in generating the second signal in response to an input signal to change the frequency of oscillation.

Abstract: Voltage controlled oscillator assembly which includes at least one voltage controlled oscillator, and a regulator for regulating the output power from the at least one voltage controlled oscillator.

Abstract: A phase-locked loop configured to cause an output signal to tend toward a desired output frequency based on an applied reference signal. In a first configuration, the phase-locked loop includes a voltage controlled oscillator operatively coupled with a bias generator. The voltage controlled oscillator is configured to produce the output signal in response to a VCO current generated via application of a biasing signal from the bias generator. The VCO current produces a regulated VCO voltage within the voltage controlled oscillator, and the bias generator is configured so that the regulated bias generator voltage matches the regulated VCO voltage free of any direct coupling between the bias generator and the regulated VCO voltage. In another configuration, the phase-locked loop includes a charge pump system having semiconductor components that correspond to only a portion of a voltage controlled oscillator associated with the loop.

Abstract: A phase-locked loop system configured to cause an output signal to tend toward a desired output frequency. The phase-locked loop system includes a charge pump system and an oscillator operatively coupled with the charge pump system. The charge pump system is configured to selectively effect proportional control over the output signal by producing a correcting pulse having a duration and applying the correcting pulse to a proportional control path of the phase-locked loop system. The charge pump system includes a correcting circuit configured to store a correcting charge corresponding to the correcting pulse, and then output the correcting charge over a period of time that is greater than the duration of the correcting pulse. Other configurations of the phase-locked loop system employ programmable current mirrors, and other structures and methods, to reduce charge pump current within the phase-locked loop.

Abstract: A compensation circuit for current control oscillator to correct the frequency curve of an oscillator includes a compensation circuit which has a plurality of P transistors and N transistors to improve stabilization of output frequency of the digital current control oscillator and to prevent the digital current control oscillator from occurring unlatching phenomenon in certain frequency zones.

Abstract: A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

Abstract: A clock signal generator in an integrated circuit semiconductor device and a method of generating a clock signal, the clock signal generator comprising: a semiconductor substrate (2); an oscillator unit (4) which comprises at least one support member (10, 12) which is fixed relative to the substrate (2), an oscillator arm (6) which is oscillatably disposed to the at least one support member (10, 12) with regard a reference position, which oscillator arm (6) includes first and second conductive sections (6a, 6b) at positions extended from the at least one support member (10, 12), and at least one biasing element (14, 16) for biasing the oscillator arm (6) towards the reference position; a driver (18) which is disposed at the substrate (2) in spaced relation adjacent one of the conductive sections (6a) of the oscillator arm (6), which driver (18) is configured in use to drive the one of the conductive sections (6a) of the oscillator arm (6) towards or away therefrom when an electrical signal is applied thereto;

Abstract: A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that would utilize this square wave clock signal.

Abstract: A self-adaptive method for controlling a self-biased PLL system is disclosed. The method comprises providing an application-dependent input frequency; and providing an application-dependent number N representing the ratio between the output frequency and the application-dependent input frequency to the PLL system. In a system and method in accordance with the present invention, the bandwidth and damping factor are tracked, not only with the input frequency but with the divider ratio as well. Therefore, jitter is minimized for any operating condition (i.e., input frequency variations [N]). The charge-pump current is made to be proportional to the VCO current ID and inversely proportional to the frequency range N; and the loop filter resistor is made to be inversely proportional to the square root of the VCO current ID and proportional to N. In so doing, the bandwidth and damping factors can be tracked more comprehensively.

Abstract: The invention provides an improved high speed voltage controlled oscillator (VCO) buffer cell, with consistent output performance. According to one embodiment of the invention, the cell comprises a differential pair of transistors and a current mirror circuit. The differential pair has input terminals for receiving input signals and output terminals for providing differential voltage swing in response to the input signals. The current mirror circuit is operably coupled to the pair of transistors and is configured to receive a first external reference current and provide a mirrored current to an active one of the transistors. The differential voltage swing has a frequency which is determined based on the reference current. In a specific embodiment of the invention, the pair of transistors of the cell is bipolar transistors, and the current mirror circuit is composed of CMOS transistors.

Abstract: The invention provides an oscillator and a control method for controlling the oscillator which reliably oscillates even when the oscillator is driven at a low voltage. An oscillator repeats a startup operation and a suspension of the startup operation by turning on and off a switch with half a period of a Schmitt trigger oscillator circuit, until a piezoelectric oscillator circuit is put into a normal oscillation state. The oscillator thus creates a number of opportunities of transient response allowing the oscillation amplitude of the piezoelectric oscillator circuit to grow, and reliably oscillates.

Abstract: Amplitude-adjustable oscillator. The oscillator includes a feedback loop to control the amplitude of an oscillator output signal. The feedback loop includes a pair of clamping transistors, wherein base terminals of the clamping transistors are coupled to an adjustable voltage signal to prevent saturation of the oscillator circuit. The feedback loop also includes a filter to monitor the current flowing through the clamping transistors. The feedback loop also includes an amplifier to compare an output of the clamping transistors to a reference signal, and a reference generator to set an operating bias for the oscillator.

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.

Abstract: An oscillator with oscillator and voltage control circuitry for generating an oscillation signal having an amplitude that is automatically controlled for a selectively minimized phase noise. Automatic level control is used for controlling the amplitude of the oscillation signal such that the phase noise of the oscillation signal can be maintained at some selected level, e.g., minimized. The minimum signal voltage appearing across the oscillation circuit is monitored for controlling the bias of the circuit to prevent it from entering a saturation state, thereby avoiding adverse loading effects responsible for degraded phase noise performance.

Abstract: A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.

Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal, which is a selected multiple of an input reference signal. The PLL circuit includes an oscillator control circuit for increasing and decreasing the PLL output frequency signal, a frequency detector for detecting a phase shift between the reference signal and the PLL output signal and produces an error signal, and a fast lock circuit for detecting when the output frequency signal passes the selected multiple of the reference signal. This circuit design provides improved jitter performance, tolerates process variation, and extends the PLL operating frequency range.

Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

Abstract: A phase locked loop that includes a receiver that is adjustable to substantially match delay of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry are responsive to one or more bias signals that are adjustable using one or more adjustment circuits that are operatively connected to the receiver. The control of the one or more bias signals via the one or more adjustment circuits facilitates the generation of substantially delay matched system and feedback clocks.

Abstract: An object of the present invention is to facilitate positioning of a metal member for mounting a high-frequency diode and of a dielectric strip, thereby remarkably improving control of oscillation characteristics and workability in production.

Abstract: An integrated circuit chip includes an RC oscillator circuit. The frequency of the output signal generated by the oscillator output signal is set as a function of a value of an included internal resistor integrated on the chip. An external resistor may be connected to the chip to allow a user to manipulate the oscillator output signal frequency. A detection circuit on the chip detects the presence of the connected external resistor. Responsive to that detection, a substitution circuit operates to substitute the connected external resistor for the internal resistor in the RC oscillator circuit. This effectuates a change of the frequency of the oscillator output signal to instead be set as a function of a value of that connected external resistor.

Abstract: A voltage-controlled oscillator includes a varactor diode which is a capacitance element coupled to a resonance circuit. A control voltage is applied to one end of the varactor diode and the output voltage of a variable DC voltage source which is capable of changing a voltage value stepwise is applied to the other end of the varactor diode via a voltage divider. Accordingly, the voltage-controlled oscillator can be operated as a local oscillator used for two communication systems. Further, a switching element is not required and thus deterioration in the characteristics caused by a reduction in the Q factor of the resonance circuit can be prevented. In addition, the power consumption does not increase.

Abstract: A real-time clock circuit for saving real time information during removal of a battery is presented. The battery provides power to the clock circuit during a steady-state mode. The clock circuit includes an oscillator assembly for generating a periodic waveform. A counter accumulates real time information in response to the periodic waveform. An energy storage device is coupled to the counter to supply energy to the counter while the battery is removed. A switch is coupled between the battery and the energy storage device to prevent the energy storage device from supplying energy to components other than the counter during removal of the battery. The switch provides a path for energy to flow from the battery to the energy storage device, thereby charging the energy storage device.

Abstract: An oscillation circuit including a first electrostatic protection circuit connected between a signal path of the oscillation circuit and a constant-voltage side, and bypassing an electrostatic voltage of a first polarity that intrudes into the signal path to a side of a constant bypass voltage through a first semiconductor rectifier element. A second electrostatic protection circuit is connected between the signal path and a reference potential side, and bypassing an electrostatic voltage of a second polarity that intrudes into the signal path to the reference potential side through a second semiconductor rectifier element. The constant bypass voltage is set to a value such that the first and second semiconductor rectifier elements are not turned on by voltage change in the signal path caused by a leakage current, even when a leakage current is generated between the signal path and a power-supply voltage line.

Abstract: An oscillator circuit (300) comprising: a resonator (Q) connected between an input (IN)and an output (OUT); an inverter having first and second driver transistors (MP, MN) connected in series via an output-coupled node; first and second biasing transistors (MPD, MND) for biasing the driver transistors; and first and second limiting means between the gate electrodes of the driver transistors respectively and the output. The CMOS circuit allows regulation of the oscillation amplitude without need for well-controlled DC current sources to polarize correctly the driver transistors, and without need for a start-up circuit to ensure that both driver transistors remain in saturation when the circuit is powered on. A simple oscillator circuit (600) has an inverter whose input is capacitively coupled to the input (IN), first limiting means coupled between the inverter input and the output (OUT), and second limiting means coupled between the input (IN) and the output (OUT).

Abstract: A phase-locked loop (PLL) has a phase detector coupled to an output of the PLL and to a reference signal and a low pass filter including a first and a second charge pump coupled to an output of the phase detector. A capacitor is coupled to an output of the first charge pump, a first bias circuit coupled to the capacitor, the first bias circuit having a differential output. A voltage controlled ring oscillator has a plurality of differential inventer stages, each having a first input coupled to a first output of the first bias circuit and a second input coupled to a second output of the first bias circuit. A second bias circuit is coupled between the capacitor and the first bias circuit, an output of the second bias circuit being coupled to an input of the first bias circuit and to an output of the second charge pump. The PLL circuit exhibits a stable damping factor with respect to frequency.

Abstract: The invention provides an improved high speed voltage controlled oscillator (VCO) buffer cell, with consistent output performance. According to one embodiment of the invention, the cell comprises a differential pair of transistors and a current mirror circuit. The differential pair has input terminals for receiving input signals and output terminals for providing differential voltage swing in response to the input signals. The current mirror circuit is operably coupled to the pair of transistors and is configured to receive a first external reference current and provide a mirrored current to an active one of the transistors. The differential voltage swing has a frequency which is determined based on the reference current. In a specific embodiment of the invention, the pair of transistors of the cell is bipolar transistors, and the current mirror circuit is composed of CMOS transistors.

Abstract: In a voltage controlled oscillator (VCO) having a voltage-current conversion circuit, a ring oscillator, and a main power supply for feeding a power supply voltage to these components, it is constructed so that a voltage which is fed to the voltage-current conversion circuit and ring oscillator may be applied with an internal voltage via a regulator circuit, thus effecting an oscillation output having only slight variations to the variations of the power supply voltage. Therefore, a phase synchronous circuit such as PLL circuits may be maintained at a locked status. In some instances, such a VCO may be modified not only to stabilize the dynamic range to the VCO control voltage, but also to switch the dynamic range. Thus, the oscillation frequency oscillated and outputted by the ring oscillator may be stabilized even upon the occurrences of the variations of the power supply voltage Vcc which is fed at a locked status.