Abstract: Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.

Abstract: An oscillator includes a voltage controlled oscillator, a PLL circuit, a crystal unit and an oscillator circuit configured to generate a clock, a digital control circuit, and a clock switching unit. The digital control circuit is configured to set an oscillation parameter of the oscillator circuit, and a parameter of the PLL circuit. The clock switching unit is configured to supply an output signal of the voltage controlled oscillator to the digital control circuit as a clock signal so as to cause the digital control circuit to operate using the clock signal when powered on, and configured to supply an output signal of the oscillator circuit to the digital control circuit as a clock signal after the digital control circuit sets the oscillation parameter of the oscillator circuit. An initial voltage is supplied to the voltage controlled oscillator as a control voltage when the oscillator is powered on.

Abstract: Disclosed are control systems, and more specifically control systems which benefit from a long-gate time for measurement and a rapid sample time to enhance responsiveness and methods and systems for utilizing multiple-staggered, overlapping gates where the gate time is an integer multiple of the time between ends of adjacent gates. The system continuously counts at the wavefronts or zero-crossings of a frequency reference signal and temporarily records them in registers and compares the contents of registers separated by a gate time and outputs a sample after every sample time.

Abstract: A controlled oscillator is tuned to produce a desired, temperature independent frequency. A first frequency ratio is determined between a first frequency of the output signal generated by the controlled oscillator and a frequency of an output signal from another oscillator. The first frequency is determined based on a sensed temperature. A desired frequency of the output signal of the controlled oscillator is used to determine a desired frequency ratio between the desired frequency and the frequency of the output signal from the other oscillator. The controlled oscillator is tuned and the frequency ratio measured until the tuning has caused the desired frequency ratio to be achieved, thereby causing the controlled oscillator to provide the desired frequency.

Abstract: According to one aspect, embodiments herein provide a PVR comprising a resonator having an oscillation frequency, the resonator comprising at least one proof-mass, a mechanical reference, at least one drive plate located adjacent a first side of the at least one proof-mass, and at least one sense plate located adjacent a second side of the at least one proof-mass, a voltage source coupled to the drive and sense plates, a reference oscillator configured to provide a reference signal having a reference frequency to the voltage source; and an output, wherein the voltage source is configured to provide a bias voltage signal to the at least one drive and at least one sense plates of the resonator to drive the oscillation frequency of the resonator to match the reference frequency, and wherein the bias voltage signal is also provided to the output of the PVR as a voltage reference signal.

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract: A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing signal according to the oscillation signal; performing frequency division upon the self-mixing signal to obtain a down-converted self-mixing signal; obtaining a down-converted self-mixing frequency corresponding to a maximum power in a specific frequency range of the down-converted self-mixing signal; and computing a frequency offset of the oscillation frequency according to at least the oscillation frequency and the down-converted self-mixing frequency. A related circuit is also disclosed.

Abstract: The disclosed invention is intended to adjust the driving power of an oscillation circuit to be optimal with a simple circuit configuration. A chip includes an oscillation circuit, an amplifier, an effective value measuring circuit, and a control unit. The oscillation circuit includes an inverting amplifier and a resistor coupled in parallel to the inverting amplifier. The oscillation circuit in which the inverting amplifier is coupled to a crystal oscillator outside the chip generates an oscillation circuit by driving the crystal oscillator. The effective value measuring circuit measures an effective value of an oscillation signal produced by the oscillation circuit. The control unit controls the gain of the inverting amplifier so that the effective value will be equal to a target voltage.

Abstract: A phase frequency detector realizes a highly linear conversion from noise-shaped ?? modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.

Abstract: A frequency generation device is provided. The frequency generation device includes a voltage generation unit configured to receive an input signal having an input frequency and to generate a feedback voltage based on the input signal, wherein the feedback voltage is proportional to the input frequency; and a feedback unit connected to the voltage generation unit and a reference voltage source, wherein the feedback unit is configured to receive a reference voltage from the reference voltage source and the feedback voltage from the voltage generation unit, so as to generate a feedback signal having a feedback frequency.

Abstract: A signal generation circuit including a phase locked loop circuit that uses an oscillation section as a reference signal source and a switching section capable of switching a state in which a periodic signal from the oscillation section is outputted to a state in which a signal from the phase locked loop circuit is outputted.

Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

Abstract: An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.

Abstract: Various configurations and arrangements of systems and methods for compensating for variations in VCO output frequencies are described. A system in accordance with the disclosure can include an oscillator circuit including an oscillator, a first variable capacitance diode coupled to the oscillator and a second variable capacitance diode coupled to the oscillator. The system further includes a voltage source configured to apply a first voltage to the oscillator circuit to cause the output signal to comprise a selected frequency, the selected frequency being based on a received reference voltage. The system further includes a controller circuit configured to compare an operating voltage of the oscillator to the reference voltage while the first voltage is applied to the oscillator; and apply a second voltage to the oscillator circuit based on the comparison. The second voltage compensates for a difference between the reference voltage and the first voltage.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator.

Abstract: An oscillator, comprising: a pair of transistors to which source terminals are interconnected and to which drain and gate terminals are coupled by a positive feedback loop comprising an oscillator tank, wherein the source terminals of the transistors are connected to a current source configured to control physical parameters of the oscillator.

Abstract: An oscillation device corrects a setting value of an output frequency based on a detection result of an ambient temperature of a crystal unit. The oscillation device includes: an oscillation circuit; a temperature detection portion that detects the ambient temperature and outputs a digital value corresponding to the temperature detection value; an accumulator that accumulates the digital value; a rounding processing portion that performs rounding for the digital value accumulated in the accumulator; a digital filter that receives the digital value obtained from the rounding processing portion and obtains a step response gradually increasing from “0” and converging to a step value; and a correction value obtaining portion that obtains a frequency correction value of the oscillation frequency of the oscillation circuit caused by a difference between the ambient temperature and a reference temperature, wherein the setting value of the output frequency is corrected based on the frequency correction value.

Abstract: Aspects of the embodiments include a method for synchronizing a device having an oscillator to a reference signal. A correction signal can be determined based on the reference signal. A mathematical model of the oscillator can be trained based at least upon the correction signal. A predicted correction signal for the trained mathematical model can be determined. A time error using the predicted correction signal can be generated to assess suitability of the trained mathematical model for disciplining drift in the oscillator and synchronizing the device when the reference signal is not available.

Abstract: A circuit arrangement for generation of radio frequency output signals which form a broadband frequency ramp, with a reference oscillator, a phase detector, a loop filter, a VC oscillator for generating the output signals, a frequency divider, a step-down mixer and a local oscillator for generating a local oscillator signal. The reference oscillator, the phase detector, the loop filter, the VC oscillator, the frequency divider and the step-down mixer belong to a phase-locking loop. The frequency divider and the step-down mixer are in the feedback path of the phase-locking loop. The step-down mixer mixes the output signals and the local oscillator signal. The frequency of the output signal is adjustable by varying the division ratio of the frequency divider. Characteristics of the output signal are improved using the adjustable frequency of the local oscillator signal.

Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.

Abstract: A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.

Abstract: Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies.

Abstract: A microwave synthesizer is disclosed that may generate low phase noise and high frequency resolution microwave signals The microwave synthesizer may include a coarse-tuning loop, the coarse-tuning loop may be adopted to generate a first signal with coarsely adjustable frequency. The coarse-tuning loop may have a first voltage controlled oscillator (VCO). An output loop, the output loop may be adopted to generate a second signal with finely adjustable frequency. The output loop may have a second VCO. A frequency mixer may be configured to couple the coarse-tuning loop and the output loop. A frequency mixer may be adopted to subtract the first and second signals. A reference frequency source may be coupled to the coarse-tuning loop and the output loop to provide reference signal for the microwave synthesizer.

Abstract: Frequency synthesizers for use with oscillators that generate an arbitrary frequency are described, as well as related devices and methods. Divider information can be generated or otherwise accessed for use in configuring a phase lock loop device that is adapted for coupling with the oscillator, where the phase lock loop device can include a plurality of integer dividers without utilizing a fractional divider, where the divider information can include frequency deviations corresponding to groups of integer divider settings for the phase lock loop device, and where each deviation of the frequency deviations can be based on a frequency differential between a standard operating frequency and an output frequency for the phase lock loop utilizing one group of integer divider settings from the groups of integer divider settings.

Abstract: A calibration circuit includes a combinational gate configured to receive a voltage-controlled oscillator (VCO) output signal and a selected reference signal to detect a phase difference between the VCO output signal and the selected reference signal and generate an output binary signal, in which the VCO output signal has one or more unwanted frequency components. The calibration circuit also includes a loop filter configured to filter the output binary signal and generate a filtered calibration signal. The calibration circuit also includes an analog-to-digital converter configured to convert the filtered calibration signal from the analog domain to the digital domain and generate a converted calibration signal. The calibration circuit also includes a processor configured to compute the converted calibration signal and determine components of a baseband signal that cancels the one or more unwanted frequency components of the VCO output signal.

Abstract: The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.

Abstract: An oscillator and a self-calibration method thereof are provided. The oscillator includes: an oscillation unit for generating an oscillation signal; a converting unit for converting frequency of the oscillation signal into a voltage signal; a comparison unit for comparing the voltage signal with a first voltage corresponding to a higher frequency and a second voltage corresponding to a lower frequency, and outputting a comparison result signal; an adjusting unit for storing a calibration value, adjusting the calibration value based on the comparison result signal and outputting a calibration signal corresponding to the adjusted calibration value; and a calibration unit for calibrating the frequency of the oscillation signal based on the calibration signal. Self-calibration for the frequency of the oscillation signal may be achieved, which may ensure the stability of the frequency of the oscillation signal.

Abstract: The present invention provides a locking method and system, and the method includes: a locking system performing a phase discrimination and conversion process to an input signal Fi of an external standard source and a feedback output signal F0 of a local thermostatic crystal oscillator which pass through a frequency division, to generate a clock signal clk and a signal sign which is used to denote a frequency size relationship between the signal Fi and the signal F0, and performing a filtering process to the signal clk and the signal sign, and performing a voltage controlled oscillation process to a signal ahead used to denote that the frequency of the signal F0 is lower than the frequency of the signal Fi and a signal lag used to denote that the frequency of the signal F0 is higher than the frequency of the signal Fi, to implement a locking of the signal F0 and the signal Fi.

Abstract: An electronic device may include a voltage controlled oscillator (VCO) and a temperature sensor. The electronic device may also include a controller configured to cooperate with the VCO and the temperature sensor to determine both a temperature and a frequency error of the VCO for each of a plurality of most recent samples. Each of the most recent samples may have a given age associated therewith. The controller may also be configured to align the temperature, the frequency error, and the given age for each of most recent samples in a three-dimensional (3D) coordinate system having respective temperature, frequency error and age axes. The controller may also be configured to estimate a predicted frequency error of the VCO based upon the aligned temperature, frequency error, and given age of the most recent samples.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.

Abstract: An oscillation circuit is connected to a resonator element (crystal resonator) and oscillates a resonator element to output an oscillation signal. The oscillation circuit includes an amplification element (inverter), and a set of variable capacitive elements having at least two variable capacitive elements, which are connected to an oscillation loop from an output to an input of the amplification element and the capacitance values thereof are controlled with potential differences between reference voltages and a variable control voltage. In each variable capacitive element of a set of variable capacitive elements, the common control voltage is applied to one terminal, and the reference voltage which differs between the variable capacitive elements is input to the other terminal.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: There are provided a control circuit for a digitally controlled oscillator and a control apparatus for a digitally controlled oscillator using the same. The control circuit for a digitally controlled oscillator includes: a peak detection circuit detecting amplitude of a signal output from the digitally controlled oscillator; and a transconductance control circuit comparing an output of the peak detection circuit with a predetermined reference signal to control a transconductance value of a negative transconductance circuit included in the digitally controlled oscillator.

Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto.

Abstract: The proper operation of a phase locked loop is determined by monitoring certain signals within the loop for their phase relationship or duty cycle. If a malfunction of the loop is detected, proper operation may be imposed or restored by resetting a phase-frequency detector, or by flipping the output of the phase-frequency detector.

Abstract: A multi-phase clock signal generator, comprising: a ring phase shifting loop, including a plurality of controllable delay cells, for generating output clock signals having different phases via the controllable delay cells according to a input clock signal, wherein delay amount of the controllable delay cells are determined by a biasing voltage; a phase skew detecting circuit, for computing phase differences of the output clock signals to generate a phase skew detecting signal; and a biasing circuit, for providing the biasing voltage according to the phase skew detecting signal. The above-mentioned ring phase shifting loop can operate independently from the multi-phase clock signal generator, without receiving the biasing voltage, for phase-shifting a input clock signal to generate output clock signals with different phases, wherein the output clock signals are respectively output at different output terminals respectively located between the phase shifting units.

Abstract: A high-frequency oscillator comprises a reference-frequency generator and a high-frequency generator. The reference-frequency generator generates a variable reference frequency and supplies it to the high-frequency generator. The high-frequency generator comprises a phase-locked loop and generates a high-frequency signal from the variable reference frequency. The phase-locked loop comprises at least one first mixer, a second mixer and several switches. The first mixer, the second mixer and the switches are connected in series. The mixers are connected into the phase-locked loop individually in a selective manner by means of the switches.

Abstract: Die-to-die interconnect structures are leveraged to form the inductive component of an LC oscillator, thus yielding an LC tank distributed across multiple IC dies rather than lumped in a single die. By this arrangement, reliance on area/power-consuming on-chip inductors may be reduced or eliminated, and phase-aligned clocks may be extracted from the LC tank within each of the spanned IC dies, obviating multiple oscillator instances or complex phase alignment circuitry.

Abstract: A signal generator for generating an output signal with a frequency that is a multiple of a frequency of a reference signal, the signal generator including an oscillator configured to generate the output signal in dependence on the reference signal and a control signal and a control circuit configured to generate the control signal to comprise a series of pulses in which one or more of the pulses is offset in phase relative to the reference signal, the control circuit thereby being capable of controlling the frequency and/or phase of the output signal.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The second signal is used for disciplining the LO. The LO error corrector is capable of disciplining the LO using a source that is less accurate than a preferred second signal, if the preferred second signal is unavailable to discipline the LO.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input configured to receive a respective second signal having timing information, frequency information, phase information or combinations thereof. The prioritizer is configured to determine an accuracy of at least one second signal of the at least two second signals in relation to a second signal assigned to be a most accurate of the at least two second signals. The prioritizer is also configured to order the at least two second signals from most accurate to least accurate. The LO is disciplined to correct an offset error of the LO relative to a most accurate second signal that is available to the device, based on the order of the at least two second signals.

Abstract: In an example, a driver for a micro-electro-mechanical-system (MEMS) device can include a first input configured to receive a first command signal including an oscillatory command signal, a second input configured to receive a second command signal including a bias command signal, and an amplifier configured to receive a high voltage supply, to provide, to the MEMS device, a closed-loop output signal responsive to both the first command signal and the second command signal in a first state, and to provide an open loop output signal configured to substantially span a voltage range of the high voltage supply in a second state.

Abstract: In one exemplary implementation, an electronic apparatus includes: a reference clock source, for generating a reference clock; a global navigation satellite system (GNSS) receiver for receiving satellites signals and the reference clock, comprising: a monitoring circuit, for monitoring a status of the GNSS receiver to generate a monitoring result; and a compensating circuit, coupled to the reference clock source and the monitoring circuit, for compensating the reference clock according to the monitoring result.

Abstract: A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information.