Abstract: A wireless base station (11) includes a wireless communication unit (17) and a clock signal generation unit (20). The clock signal generation unit (20) includes a voltage-controlled oscillation unit (21) that outputs a clock signal of an oscillating frequency according to an inputted control voltage, a time information generation unit (22) that generates time information based on the clock signal, a time information comparison unit (23) that compares the time information with reference time information; and a control voltage instruction unit (24) that instructs a control voltage according to the comparison result to the voltage-controlled oscillation unit (21). Accordingly, the oscillating frequency of the clock signal can be kept easily and highly precisely.

Abstract: A technique for improving frequency synthesizer performance by frequency-compensating charge pump current in order to maintain a consistent loop bandwidth over a wide operating frequency range is described. A relationship between the capacitance value associated with a voltage controlled oscillator resonant tank and the magnitude of current pulses in a related charge pump is exploited to bound the loop bandwidth of the frequency synthesizer over both operating frequency and process variation. A control state machine generates digital coarse tune values that dynamically select a capacitance for the resonant tank, such that the voltage controlled oscillator operates within an optimal control voltage range. Each dynamically selected capacitance value is then used to determine the magnitude of current pulses in the charge pump.

Abstract: Provided is a phase-locked loop frequency synthesizer, including: a reference oscillator; a voltage controlled oscillator; a variable frequency divider that divides the high frequency signal in frequency to output a feedback signal; a phase comparator that compares the reference signal and the feedback signal with each other to output a phase comparison signal; a loop filter that outputs a control signal of the voltage controlled oscillator based on the phase comparison signal; and a frequency/phase control circuit that generates frequency division number control data in synchronism with any one of the feedback signal and the reference signal based on setting data which is input from an external to give an output frequency and setting data which is input from the external to give a phase to the reference signal, to thereby output the frequency division number control data to the variable frequency divider.

Abstract: A source of radiation comprises a first low frequency oscillator 200 for providing a reference signal and a plurality of phase shifters 210a, 210b, 210c coupled to the first oscillator. In addition there are a plurality of phase locked loops 230a, 230b, 230c, each phase locked loop having a respective Voltage Controlled Oscillator (VCO) 240a, 240b, 240c for outputting a signal. Each phased locked loop is coupled to a respective one of the phase shifters, so that in use each VCO is phase locked to a reference signal which has been phase shifted by a respective one of the phase shifters. In this way the phase of the radiation output by each VCO may be controlled indirectly by controlling the phase shift of the reference signal. In a preferred embodiment the phase shifters are adjustable to shift the phase by an adjustable amount.

Abstract: An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: An optical transmission apparatus according to the present invention connects a terminal apparatus side in which a transmission line is formed by, for example, SONET/SDH, and a WDM side in which a transmission line is formed by, for example, OTU3. The optical transmission apparatus according to the present invention includes a selector that, when an input signal is interrupted or switched, controls a PLL unit so as to switch and obtain a clock signal of a predetermined frequency oscillated by an OSC, corresponding to a frequency of a clock signal of the input signal before being divided to input into the PLL unit, as a clock signal to generate a PLL reference frequency.

Abstract: Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator.

Abstract: A charge pump circuit includes at least one switching transistor and a level-shifter. The level-shifter has a cross-coupled pair of transistors. The level-shifter shifts a voltage of a first input signal to generate a level-shifted signal. The level-shifted signal controls a conductive state of the switching transistor to regulate an output voltage of the charge pump. A feedback loop circuit includes a detector and a charge pump. The detector compares an input signal to a feedback signal to generate first and second output signals. The charge pump includes at least two thin-oxide switching transistors and a level-shifter in another embodiment. The level-shifter shifts a voltage of the first output signal of the detector to generate a level-shifted signal. The two switching transistors are driven by the level-shifted signal and the second output signal of the detector to regulate an output voltage of the charge pump.

Abstract: There is provided with a resonator which can correct the resonance frequency of a vibrator in a wide range and with a high accuracy and also provided with an oscillator using the resonator. In the resonator configured by the vibrator 101, electrodes 4, 5 disposed so as to oppose to parts of the surface of the vibrator 101 via gaps, and variable voltage sources 24, 25 for applying a voltage to both or one of the vibrator 101 and the electrodes 4, 5, each of the electrodes 4, 5 is configured by plural electrodes. The electrodes 4, 5 are respectively disposed via gaps close to the portions of the vibrator 101 having different vibration amplitudes. The DC voltages being applied are independently adjusted with respect to the electrodes 4, 5 which differ in distances from the shaft of the vibrator among the plural electrodes close to the vibrator 101.

Abstract: An object is to provide a PLL having a wide operating range. Another object is to provide a semiconductor device or a wireless tag which has a wide operating range in a communication distance or temperature by incorporating such a PLL. The semiconductor device or the wireless tag includes a first divider circuit; a second divider circuit; a phase comparator circuit to which an output of the first divider circuit and an output of the second divider circuit are provided; a loop filter to which an output of the phase comparator circuit is supplied and in which a time constant is switched in accordance with an inputted signal; and a voltage controlled oscillator circuit to which an output of the loop filter is supplied and which supplies an output to the second divider circuit.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: An oscillator is provided which comprises an array of capacitances. At least some capacitances in the array have different capacitance values.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: A difference between a reference clock and feedback clock is detected to generate a difference signal that is filtered to generate a voltage controlled oscillator control signal and produce an oscillation signal having an oscillation frequency. A first frequency dividing circuit divides the oscillation signal by a selected one of a number of first frequency divisors to generate an output signal at a selected frequency. A second frequency dividing circuit divides the output signal by a selected one of a number of second frequency divisors to generate the feedback clock. The frequency divisors are selected by a frequency selection signal. The first frequency dividing circuit samples the frequency selection signal at the rate of the oscillation signal divided by a least common multiple of the plurality of first frequency divisors. The second frequency dividing circuit samples the sampled frequency selection signal at the rate of the feedback clock.

Abstract: A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal, wherein a drive capability of the oscillator part is controlled in accordance with the control signal.

Abstract: In a voltage-controlled oscillator capable of broadening a variable frequency range while suppressing increase of conversion gain, a converter (12) converts an input voltage to a first physical quantity, a variable converter (13) supplies a second physical quantity that accords with the status of each switch of a switch group (13a). another variable converter (14), when the input voltage is contained within a prescribed voltage range, supplies a third physical quantity that accords with the input voltage and the status of each switch of another switch group (14a), and a variable-frequency oscillator (15) supplies a signal of a frequency that accords with the first physical quantity, the second physical quantity, and the third physical quantity.

Abstract: A frequency phase correction system and method are described that provides a receiver with a greater ability to lock onto relatively weak radio frequency signals by determining and estimating an amount of frequency error in a local frequency reference of the receiver, and using the error estimate to maintain frequency coherence with a received signal, thereby allowing tracking over a longer period of time, enabling longer integration times to capture weaker signals without losing frequency coherence.

Abstract: A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator.

Abstract: A method for operating a micro-electro-mechanical system (MEMS) scanner on a resonant mode frequency is provided. The method includes generating a drive signal for a MEMS scanner. A sensor signal is received from the MEMS scanner. The drive signal is compared to the sensor signal. An accumulated correction signal is generated based on the comparison of the drive signal and the sensor signal. The drive signal for the MEMS scanner is then adjusted based on the accumulated correction signal.

Abstract: Example embodiments of the present invention are directed to a compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. The values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and/or manufacturing variations of the microelectromechanical resonator. The frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital/frequency synthesizers and/or FLLs, as well as any combinations and permutations thereof.

Abstract: An embodiment of a communication system is provided, in which a high frequency oscillator generates a first high frequency signal upon receipt of no disable signal. The first high frequency signal is commonly shared by at least two modules. Each module coupled to the high frequency oscillator operates in either busy or idle mode, wherein the module operates at the first high frequency signal when in busy mode, and asserts a request signal when in idle mode. A disablement unit, coupled to the first and second modules, asserts the disable signal to the high frequency oscillator when all of the request signals are asserted, thereby forcing the high frequency oscillator to cease the generation of the first high frequency signal.

Abstract: A phase-locked loop frequency synthesizer including phase detector circuitry and divider circuitry producing a divided signal. The phase detector circuitry receives a reference signal, a divided signal fed back from the divider circuitry, and generates control pulses which control a charge pump in accordance with a frequency and phase relationship between the reference signal and the divided signal. The divider circuitry has a main divider which divides an input signal by a division ratio selected from a pair of dual modules division ratios, and outputs the divided input signal as an output signal and an auxiliary divider which produces serial output data, each bit of which serves as a dual modules selection signal to cause the main divider to operate using one of the pair of dual modules main division ratios. The auxiliary divider produces the divided signal once per cycle and outputs the pulse to the phase detector circuitry.

Abstract: A method and apparatus controlling the output phase of a VCO (Voltage Controlled Oscillator). The apparatus has a phase locked loop 20 having a first input 21 for receiving a reference signal and a second input 22 for receiving a feedback signal and the output for controlling of a VCO. A phase shifter 50 is provided on the feedback path between the VCO and the second input of the phase locked loop. The phase shifter is arranged for shifting the phase for feedback signal by controlled amount. The phase shifter may be a variable phase shifter for controlling and varying the amount by which the phase feedback signal is shifted.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.

Abstract: There is provided an analog phase locked oscillator comprising a sampling phase detector, a loop filter, a voltage controlled oscillator, a frequency multiplier and a feedback loop where the feedback loop connects the output of said oscillator with the input of said phase detector through said frequency multiplier. The sampling phase detector is adapted to perform a discrete phase comparison between a reference frequency and the multiplied feedback signal. The voltage controlled oscillator is adapted to give out a constant frequency at a multiply of the reference frequency divided with the multiplication factor of the multiplier.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input configured to receive a respective second signal having timing information, frequency information, phase information or combinations thereof. The prioritizer is configured to determine an accuracy of at least one second signal of the at least two second signals in relation to a second signal assigned to be a most accurate of the at least two second signals. The prioritizer is also configured to order the at least two second signals from most accurate to least accurate. The LO is disciplined to correct an offset error of the LO relative to a most accurate second signal that is available to the device, based on the order of the at least two second signals.

Abstract: A spread spectrum clock generator includes a voltage-controlled oscillator generating an operation clock, a feedback control unit, a modulated pulse generation unit generating a pulse signal obtained by performing a delta-sigma modulation on a component fluctuating a frequency of the operation clock, a level set unit setting an amplitude of the pulse signal, an adder adding a voltage generated by the feedback control unit and the pulse signal whose amplitude is set by the level set unit, and a low pass filter filtering a signal outputted from the adder and generating a control voltage applied to the voltage-controlled oscillator. The feedback control unit compares a phase of the operation clock with a phase of a reference clock, and based on results of the comparison, generates a voltage used as a reference to oscillate the voltage-controlled oscillator.

Abstract: Systems and methods are disclosed for recovering a clock or time reference for A/V systems. One method comprises receiving at least one input time reference generated using a first clock and generating, using a second clock asynchronous to the first clock, at least one time reference value representative of the at least one input time reference. The method further comprises outputting the generated time reference value used by the A/V system.

Abstract: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signals. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. In one exemplary embodiment, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In another exemplary embodiment, multiple signals may be transmitted over multiple cables. Additionally, multiple signals over one or more cables may be transmitted at or below 3 GHz.

Abstract: A device includes: a plurality of sampling phase detectors, each receiving a sampling signal and a VCO output signal and in response thereto outputting a beat signal representing a frequency and phase difference between the VCO output signal and the sampling signal; a frequency/phase detector receiving a reference signal and a combined beat signal produced by combining the beat signals, and in response thereto producing an error signal representing a phase difference between the reference signal and the combined beat signal; a loop integrator receiving the error signal and in response thereto producing the VCO control signal; a power detector detecting a power level of the combined beat signal; and at least one offset voltage generator adjusting a value of a bias voltage in response to the detected power level of the combined beat signal, and applying the adjusted bias voltage to one of the sampling phase detectors.

Abstract: A wireless communication device comprises a frequency generation circuit employing a crystal oscillator operably coupled to a fractional-based synthesiser and a voltage-controlled oscillator. The fractional-based synthesiser utilises a ratio between an integer value and a fractional value to set a radio frequency signal of the voltage-controlled oscillator. An automatic frequency control scaling sub-system is operably coupled to a fractional-based synthesiser and configured to receive and use an AFC word to frequency scale the fractional value in a multiplicative manner to set a radio frequency supported by the fractional-based synthesiser. Preferably, an automatic frequency generation sub-system utilises Absolute Radio Frequency Channel Number and the cyclical nature of the fractional value. In this manner, a saving on hardware and software overheads associated with frequency channel selection for fractional-N type synthesizers can be made.

Abstract: A system and method is disclosed that provides a technique for generating an accurate time base for MEMS sensors and actuators which has a vibrating MEMS structure. The accurate clock is generated from the MEMS oscillations and converted to the usable range by means of a frequency translation circuit.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. An input baseband signal is interpolated and upconverted in the digital domain to an IF. The LO operates at a frequency which is a n/m division of the target RF frequency fRF. The IF frequency is configured to ½ of the LO frequency. The upconverted IF signal is then converted to the analog domain via digital power amplifiers followed by voltage combiners. The output of the combiners is band pass filtered to extract the desired replica.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The signal is input to a synthesizer timed to a rational multiplier of the RF frequency fRF. The signal is then divided to generate a plurality of phases of the divided signal. A plurality of combination signals are generated which are then multiplied by a set of weights and summed to cancel out some undersired products. The result is filtered to generate the LO output signal.

Abstract: A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

Abstract: A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time.

Abstract: A mixed-mode PLL is disclosed. The mixed-mode PLL comprises an analog phase correction path and a digital frequency correction path. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit.

Abstract: A signal processing apparatus of an electronic device not only cuts off supply of power to a hardware unit from a power supply unit when a control signal associated with a power OFF command is supplied from an instruction input unit, but also turns OFF a switching circuit of an oscillation circuit unit, thereby cutting off supply of power to the oscillation circuit unit. The switching circuit is configured to be turned ON according to input of a signal from an interrupt port unit, and resumes supply of the power to the oscillation circuit unit upon supply of a control signal from the instruction input unit. When supply of a clock signal to a CPU circuit unit from the oscillation circuit unit is resumed, the CPU circuit unit resumes supply of power to the hardware unit from the power supply unit after operation of the CPU circuit unit is stabilized.

Abstract: In various embodiments, the invention provides a frequency controller to control and provide a stable resonant frequency of a clock generator and/or a timing and frequency reference. Such stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted.

Abstract: An oscillator control apparatus has a digitally-controlled oscillator which outputs an oscillation signal having an oscillation frequency in response to an oscillator adjusting signal, a counter which counts the oscillation signal and outputs a count in response to a reference signal in synchronism with the oscillation signal, a time-to-digital converter which calculates a phase difference between the oscillation signal and the reference signal, an adder which adds the count and the phase difference and outputs the added value as first phase information, a corrector which corrects the first phase information in response to a phase control signal for setting an oscillation frequency of the digitally-controlled oscillator when a time difference between a rising-up timing of the oscillation signal and a rising-up timing of the reference signal is less than a predetermined time, and outputs second phase information, and a filter for smoothing a difference between the phase control signal and the second phase info

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T/12 or zero based on the state of the controlled oscillator down-divided clock.

Abstract: An oscillator is disclosed that is tunable to discrete values, and includes a tuning element which can be connected via a switching device. A rectifier circuit is connected to the output of the oscillator and forms a clock signal from the oscillator signal. The oscillator circuit contains a phase delay circuit having a switching input, a clock signal input which is coupled to the output of the rectifier circuit, and a switching output coupled to the switching device. The phase delay circuit has a comparison circuit for comparison of a phase of the clock signal that is applied to the signal input with a reference phase. This phase delay circuit is designed to emit a switching signal after application of an activation signal to the switching input and after the phase of the clock signal which is applied to the signal input matches the reference phase.

Abstract: A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a predetermined division ratio and generate a division clock signal, a feedback loop that can perform a delay locked operation on the division clock signal and generate a delay clock signal, a half period delay unit that can delay the delay clock signal by a half period of the reference clock signal and generate a half period delay clock signal, and an operation unit that can combine the delay clock signal and the half period delay clock signal and generate an output clock signal.

Abstract: Provided is a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a trouble For solving the problem, as a result of monitoring the signal level of the external reference frequency signal, when its signal level falls within a set range, data regarding a phase difference created by a phase difference data creating means is used for the PLL control, but when the signal level does not fall within the set range, it is recognized that the supply of the signal has been stopped or the supplied signal has abnormality and the data regarding the phase difference stored in a storage unit, for example, the stored latest data or the pre-created data is used instead for the PLL control.